2 * This file needs a major cleanup. Too much #if 0 code
5 #include <console/console.h>
8 #include <device/device.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <device/hypertransport.h>
19 * set up basic things ...
20 * PAR should NOT go here, as it might change with the mainboard.
22 static void cpu_init(device_t dev)
24 unsigned long *l = (unsigned long *) 0xfffef088;
26 for(i = 0; i < 16; i++, l++)
27 printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
29 printk(BIOS_SPEW, "SC520 random fixup ...\n");
33 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
34 * there is no real northbridge, keep it here in cpu.
35 * Ron wins, he's writing the code.
37 static void sc520_enable_resources(struct device *dev) {
38 unsigned char command;
40 printk(BIOS_SPEW, "%s\n", __func__);
41 command = pci_read_config8(dev, PCI_COMMAND);
42 printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
43 command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
44 printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
45 pci_write_config8(dev, PCI_COMMAND, command);
46 command = pci_read_config8(dev, PCI_COMMAND);
47 printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
53 static void sc520_read_resources(device_t dev)
57 pci_dev_read_resources(dev);
59 res = new_resource(dev, 1);
62 res->limit = 0xffffUL;
63 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
65 res = new_resource(dev, 3); /* IOAPIC */
66 res->base = 0xfec00000;
67 res->size = 0x00001000;
68 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
72 static struct device_operations cpu_operations = {
73 .read_resources = sc520_read_resources,
74 .set_resources = pci_dev_set_resources,
75 .enable_resources = sc520_enable_resources,
81 static const struct pci_driver cpu_driver __pci_driver = {
82 .ops = &cpu_operations,
83 .vendor = PCI_VENDOR_ID_AMD,
87 static void pci_domain_set_resources(device_t dev)
91 printk(BIOS_SPEW, "%s\n", __func__);
92 pci_tolm = find_pci_tolm(dev->link_list);
93 mc_dev = dev->link_list->children;
95 unsigned long tomk, tolmk;
96 // unsigned char rambits;
100 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
102 reg = pci_read_config8(mc_dev, ramregs[i]);
103 /* these are ENDING addresses, not sizes.
104 * if there is memory in this slot, then reg will be > rambits.
105 * So we just take the max, that gives us total.
106 * We take the highest one to cover for once and future coreboot
107 * bugs. We warn about bugs.
112 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
115 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
116 tomk = rambits*8*1024;
119 /* Compute the top of Low memory */
120 tolmk = pci_tolm >> 10;
122 /* The PCI hole does does not overlap the memory.
126 /* Report the memory regions */
128 ram_resource(dev, idx++, 0, tolmk);
130 assign_resources(dev->link_list);
134 void sc520_enable_resources(device_t dev) {
136 printk(BIOS_SPEW, "%s\n", __func__);
137 printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
140 command = pci_read_config8(dev, PCI_COMMAND);
141 printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
142 command |= PCI_COMMAND_MEMORY;
143 printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
144 pci_write_config8(dev, PCI_COMMAND, command);
145 command = pci_read_config8(dev, PCI_COMMAND);
146 printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
148 enable_childrens_resources(dev);
149 printk(BIOS_SPEW, "%s\n", __func__);
153 static struct device_operations pci_domain_ops = {
154 .read_resources = pci_domain_read_resources,
155 .set_resources = pci_domain_set_resources,
157 * If enable_resources is set to the generic enable_resources
158 * function the whole thing will hang in an endless loop on
159 * the ts5300. If this is really needed on another platform,
160 * something is conceptually wrong.
162 .enable_resources = 0, //enable_resources,
164 .scan_bus = pci_domain_scan_bus,
168 static void cpu_bus_init(device_t dev)
170 printk(BIOS_SPEW, "cpu_bus_init\n");
173 static void cpu_bus_noop(device_t dev)
177 static struct device_operations cpu_bus_ops = {
178 .read_resources = cpu_bus_noop,
179 .set_resources = cpu_bus_noop,
180 .enable_resources = cpu_bus_noop,
181 .init = cpu_bus_init,
186 static void enable_dev(struct device *dev)
188 printk(BIOS_SPEW, "%s\n", __func__);
189 /* Set the operations if it is a special bus type */
190 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
191 dev->ops = &pci_domain_ops;
195 /* This is never hit as none of the sc520 boards have
196 * an APIC cluster defined
198 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
199 dev->ops = &cpu_bus_ops;
205 struct chip_operations cpu_amd_sc520_ops = {
206 CHIP_NAME("AMD Elan SC520 CPU")
207 .enable_dev = enable_dev,