src/cpu/amd/sc520/sc520.c

   1 #include <console/console.h>
   2 #include <arch/io.h>
   3 #include <stdint.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <device/hypertransport.h>
   8 #include <stdlib.h>
   9 #include <string.h>
  10 #include <bitops.h>
  11 #include "chip.h"
  12
  13
  14 /* hack for now */
  15 void sc520_udelay(int microseconds) {
  16         volatile int x;
  17         for(x = 0; x < 1000; x++)
  18                 ;
  19 }
  20
  21 /* looks like we define this now */
  22 void
  23 udelay(int microseconds) {
  24         sc520_udelay(microseconds);
  25 }
  26 /*
  27  * set up basic things ... PAR should NOT go here, as it might change with the mainboard.
  28  */
  29 static void cpu_init(device_t dev)
  30 {
  31   unsigned long *l = (unsigned long *) 0xfffef088;
  32   int i;
  33   for(i = 0; i < 16; i++, l++)
  34     printk_err("Par%d: 0x%lx\n", i, *l);
  35
  36   printk_spew("SC520 random fixup ...\n");
  37 }
  38
  39
  40 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
  41  * there is no real northbridge, keep it here in cpu.
  42  * Ron wins, he's writing the code.
  43  */
  44 void sc520_enable_resources(struct device *dev) {
  45         unsigned char command;
  46
  47         printk_spew("%s\n", __FUNCTION__);
  48         command = pci_read_config8(dev, PCI_COMMAND);
  49         printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
  50         command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  51         printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
  52         pci_write_config8(dev, PCI_COMMAND, command);
  53         command = pci_read_config8(dev, PCI_COMMAND);
  54         printk_spew("========>%s, command 0x%x\n", __FUNCTION__, command);
  55 /*
  56  */
  57
  58 }
  59
  60
  61 static struct device_operations cpu_operations = {
  62         .read_resources   = pci_dev_read_resources,
  63         .set_resources    = pci_dev_set_resources,
  64         .enable_resources = sc520_enable_resources,
  65         .init             = cpu_init,
  66         .enable           = 0,
  67         .ops_pci          = 0,
  68 };
  69
  70 static struct pci_driver cpu_driver __pci_driver = {
  71         .ops = &cpu_operations,
  72         .vendor = PCI_VENDOR_ID_AMD,
  73         .device = 0x3000
  74 };
  75
  76
  77
  78 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
  79
  80 static void pci_domain_read_resources(device_t dev)
  81 {
  82         struct resource *resource;
  83   printk_spew("%s\n", __FUNCTION__);
  84         /* Initialize the system wide io space constraints */
  85         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
  86         resource->limit = 0xffffUL;
  87         resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  88
  89         /* Initialize the system wide memory resources constraints */
  90         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
  91         resource->limit = 0xffffffffULL;
  92         resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
  93 }
  94
  95 static void ram_resource(device_t dev, unsigned long index,
  96         unsigned long basek, unsigned long sizek)
  97 {
  98         struct resource *resource;
  99   printk_spew("%s sizek 0x%x\n", __FUNCTION__, sizek);
 100         if (!sizek) {
 101                 return;
 102         }
 103         resource = new_resource(dev, index);
 104         resource->base  = ((resource_t)basek) << 10;
 105         resource->size  = ((resource_t)sizek) << 10;
 106         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
 107                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 108 }
 109
 110 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 111 {
 112         struct resource **best_p = gp;
 113         struct resource *best;
 114         best = *best_p;
 115         if (!best || (best->base > new->base)) {
 116                 best = new;
 117         }
 118         *best_p = best;
 119 }
 120
 121 static uint32_t find_pci_tolm(struct bus *bus)
 122 {
 123         struct resource *min;
 124         uint32_t tolm;
 125   printk_spew("%s\n", __FUNCTION__);
 126         min = 0;
 127         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 128         tolm = 0xffffffffUL;
 129         if (min && tolm > min->base) {
 130                 tolm = min->base;
 131         }
 132   printk_spew("%s returns 0x%x\n", __FUNCTION__, tolm);
 133         return tolm;
 134 }
 135
 136 static void pci_domain_set_resources(device_t dev)
 137 {
 138         device_t mc_dev;
 139         uint32_t pci_tolm;
 140   printk_spew("%s\n", __FUNCTION__);
 141         pci_tolm = find_pci_tolm(&dev->link[0]);
 142         mc_dev = dev->link[0].children;
 143         if (mc_dev) {
 144                 unsigned long tomk, tolmk;
 145                 //              unsigned char rambits;
 146                 // int i;
 147                 int idx;
 148 #if 0
 149                 for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) {
 150                         unsigned char reg;
 151                         reg = pci_read_config8(mc_dev, ramregs[i]);
 152                         /* these are ENDING addresses, not sizes.
 153                          * if there is memory in this slot, then reg will be > rambits.
 154                          * So we just take the max, that gives us total.
 155                          * We take the highest one to cover for once and future linuxbios
 156                          * bugs. We warn about bugs.
 157                          */
 158                         if (reg > rambits)
 159                                 rambits = reg;
 160                         if (reg < rambits)
 161                                 printk_err("ERROR! register 0x%x is not set!\n",
 162                                         ramregs[i]);
 163                 }
 164                 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 165                 tomk = rambits*8*1024;
 166 #endif
 167                 tomk = 32 * 1024;
 168                 /* Compute the top of Low memory */
 169                 tolmk = pci_tolm >> 10;
 170                 if (tolmk >= tomk) {
 171                         /* The PCI hole does does not overlap the memory.
 172                          */
 173                         tolmk = tomk;
 174                 }
 175                 /* Report the memory regions */
 176                 idx = 10;
 177                 ram_resource(dev, idx++, 0, tolmk);
 178         }
 179         assign_resources(&dev->link[0]);
 180 }
 181
 182 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
 183 {
 184   printk_spew("%s\n", __FUNCTION__);
 185         max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
 186         return max;
 187 }
 188
 189
 190 static void enable_resources(device_t dev) {
 191
 192         printk_spew("%s\n", __FUNCTION__);
 193         printk_spew("THIS IS FOR THE SC520 =============================\n");
 194
 195 /*
 196         command = pci_read_config8(dev, PCI_COMMAND);
 197         printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
 198         command |= PCI_COMMAND_MEMORY;
 199         printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
 200         pci_write_config8(dev, PCI_COMMAND, command);
 201         command = pci_read_config8(dev, PCI_COMMAND);
 202         printk_spew("%s, command 0x%x\n", __FUNCTION__, command);
 203  */
 204         enable_childrens_resources(dev);
 205         printk_spew("%s\n", __FUNCTION__);
 206 }
 207
 208 static struct device_operations pci_domain_ops = {
 209         .read_resources   = pci_domain_read_resources,
 210         .set_resources    = pci_domain_set_resources,
 211         .enable_resources = enable_resources,
 212         .init             = 0,
 213         .scan_bus         = pci_domain_scan_bus,
 214 };
 215
 216 static void cpu_bus_init(device_t dev)
 217 {
 218   printk_spew("cpu_bus_init\n");
 219 }
 220
 221 static void cpu_bus_noop(device_t dev)
 222 {
 223 }
 224
 225 static struct device_operations cpu_bus_ops = {
 226         .read_resources   = cpu_bus_noop,
 227         .set_resources    = cpu_bus_noop,
 228         .enable_resources = cpu_bus_noop,
 229         .init             = cpu_bus_init,
 230         .scan_bus         = 0,
 231 };
 232
 233 static void enable_dev(struct device *dev)
 234 {
 235   printk_spew("%s\n", __FUNCTION__);
 236         /* Set the operations if it is a special bus type */
 237         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 238                 dev->ops = &pci_domain_ops;
 239                 pci_set_method(dev);
 240         }
 241         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 242                 dev->ops = &cpu_bus_ops;
 243         }
 244 }
 245
 246
 247 struct chip_operations cpu_amd_sc520_ops = {
 248         CHIP_NAME("AMD SC520")
 249         .enable_dev = enable_dev,
 250 };