1 #include <console/console.h>
2 #include <device/device.h>
3 #include <cpu/x86/mtrr.h>
4 #include <cpu/amd/mtrr.h>
5 #include <cpu/x86/cache.h>
6 #include <cpu/x86/msr.h>
8 static unsigned long resk(uint64_t value)
10 unsigned long resultk;
11 if (value < (1ULL << 42)) {
12 resultk = value >> 10;
20 static unsigned fixed_mtrr_index(unsigned long addrk)
23 index = (addrk - 0) >> 6;
25 index = ((addrk - 8*64) >> 4) + 8;
28 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
30 if (index > NUM_FIXED_RANGES) {
31 index = NUM_FIXED_RANGES;
36 static unsigned int mtrr_msr[] = {
37 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
38 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
39 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
42 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
45 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
47 msr.lo = msr.hi = 0; /* Shut up gcc */
48 for (i = first; i < last; i++) {
49 /* When I switch to a new msr read it in */
50 if (fixed_msr != i >> 3) {
51 /* But first write out the old msr */
52 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
54 wrmsr(mtrr_msr[fixed_msr], msr);
58 msr = rdmsr(mtrr_msr[fixed_msr]);
61 msr.lo &= ~(0xff << ((i&3)*8));
62 msr.lo |= type << ((i&3)*8);
64 msr.hi &= ~(0xff << ((i&3)*8));
65 msr.hi |= type << ((i&3)*8);
68 /* Write out the final msr */
69 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
71 wrmsr(mtrr_msr[fixed_msr], msr);
77 unsigned long mmio_basek, tomk;
79 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
81 struct mem_state *state = gp;
83 unsigned int start_mtrr;
84 unsigned int last_mtrr;
86 topk = resk(res->base + res->size);
87 if (state->tomk < topk) {
90 if ((topk < 4*1024*1024) && (state->mmio_basek < topk)) {
91 state->mmio_basek = topk;
93 start_mtrr = fixed_mtrr_index(resk(res->base));
94 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
95 if (start_mtrr >= NUM_FIXED_RANGES) {
98 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
99 start_mtrr, last_mtrr);
100 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
104 extern void enable_fixed_mtrr(void);
106 void amd_setup_mtrrs(void)
108 unsigned long address_bits;
109 struct mem_state state;
114 /* Enable the access to AMD RdDram and WrDram extension bits */
116 msr = rdmsr(SYSCFG_MSR);
117 msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
118 wrmsr(SYSCFG_MSR, msr);
122 /* Initialized the fixed_mtrrs to uncached */
123 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
124 0, NUM_FIXED_RANGES);
125 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
127 /* Except for the PCI MMIO hole just before 4GB there are no
128 * significant holes in the address space, so just account
129 * for those two and move on.
131 state.mmio_basek = state.tomk = 0;
132 search_global_resources(
133 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
134 set_fixed_mtrr_resource, &state);
135 printk_debug("DONE fixed MTRRs\n");
137 if (state.mmio_basek > state.tomk) {
138 state.mmio_basek = state.tomk;
140 /* Round state.mmio_basek down to the nearst size that will fit in TOP_MEM */
141 state.mmio_basek = state.mmio_basek & ~TOP_MEM_MASK_KB;
142 /* Round state.tomk up to the next greater size that will fit in TOP_MEM */
143 state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
148 msr.hi = state.mmio_basek >> 22;
149 msr.lo = state.mmio_basek << 10;
152 if(state.tomk>(4*1024*1024)) {
154 msr.hi = state.tomk >> 22;
155 msr.lo = state.tomk << 10;
156 wrmsr(TOP_MEM2, msr);
159 /* zero the IORR's before we enable to prevent
160 * undefined side effects.
163 for(i = IORR_FIRST; i <= IORR_LAST; i++) {
167 /* Enable Variable Mtrrs
168 * Enable the RdMem and WrMem bits in the fixed mtrrs.
169 * Disable access to the RdMem and WrMem in the fixed mtrr.
171 msr = rdmsr(SYSCFG_MSR);
172 msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_TOM2En;
173 msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
174 wrmsr(SYSCFG_MSR, msr);
180 /* FIXME we should probably query the cpu for this
181 * but so far this is all any recent AMD cpu has supported.
185 /* Now that I have mapped what is memory and what is not
186 * Setup the mtrrs so we can cache the memory.
188 x86_setup_var_mtrrs(address_bits);