1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
6 #include <cpu/x86/lapic.h>
7 #include <cpu/x86/cache.h>
8 #include <cpu/amd/lxdef.h>
10 static void vsm_end_post_smi(void)
20 static void model_lx_init(device_t dev)
25 printk_debug("model_lx_init\n");
27 /* Turn on caching if we haven't already */
29 /* Instruction Memory Configuration register
30 * set EBE bit, required when L2 cache is enabled
32 msr = rdmsr(CPU_IM_CONFIG);
34 wrmsr(CPU_IM_CONFIG, msr);
36 /* Data Memory Subsystem Configuration register
37 * set EVCTONRPL bit, required when L2 cache is enabled in victim mode
39 msr = rdmsr(CPU_DM_CONFIG0);
41 wrmsr(CPU_DM_CONFIG0, msr);
43 /* invalidate L2 cache */
46 wrmsr(L2_CONFIG_MSR, msr);
51 wrmsr(L2_CONFIG_MSR, msr);
55 /* Enable the local cpu apics */
60 printk_debug("model_lx_init DONE\n");
63 static struct device_operations cpu_dev_ops = {
64 .init = model_lx_init,
67 static struct cpu_device_id cpu_table[] = {
68 { X86_VENDOR_AMD, 0x05A2 },
72 static struct cpu_driver driver __cpu_driver = {
74 .id_table = cpu_table,