src/cpu/amd/model_gx2/model_gx2_init.c

   1 #include <console/console.h>
   2 #include <device/device.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <cpu/cpu.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <cpu/x86/cache.h>
   8
   9 #if 0
  10 #include <cpu/amd/gx2def.h>
  11 #include <arch/io.h>
  12
  13 static void gx2_cpu_setup(void)
  14 {
  15         unsigned char rreg;
  16         unsigned char cpu_table[] = {
  17                 0xc1, 0x00,             /* NO SMIs */
  18                 0xc3, 0x14,             /* Enable CPU config register */
  19                 0x20, 0x00,             /* */
  20                 0xb8, GX_BASE>>30,      /* Enable GXBASE address */
  21                 0xc2, 0x00,
  22                 0xe8, 0x98,
  23                 0xc3, 0xf8,             /* Enable CPU config register */
  24                 0x00, 0x00
  25                 };
  26         unsigned char *cPtr = cpu_table;
  27
  28         while(rreg = *cPtr++) {
  29                 unsigned char rval = *cPtr++;
  30                 outb(rreg, 0x22);
  31                 outb(rval, 0x23);
  32                 }
  33
  34         outb(0xff, 0x22);               /* DIR1 -- Identification register 1 */
  35         if(inb(0x23) > 0x63) {          /* Rev greater than R3 */
  36                 outb(0xe8, 0x22);
  37                 outb(inb(0x23) | 0x20, 0x23);   /* Enable FPU Fast Mode */
  38
  39                 outb(0xf0, 0x22);
  40                 outb(inb(0x23) | 0x02, 0x23);   /* Incrementor on */
  41
  42                 outb(0x20, 0x22);
  43                 outb(inb(0x23) | 0x24, 0x23);   /* Bit 5 must be on */
  44                                                 /* Bit 2 Incrementor margin 10 */
  45
  46         }
  47 }
  48
  49 static void gx2_gx_setup(void)
  50 {
  51 unsigned long gx_setup_table[] = {
  52         GX_BASE + DC_UNLOCK,            DC_UNLOCK_MAGIC,
  53         GX_BASE + DC_GENERAL_CFG,               0,
  54         GX_BASE + DC_UNLOCK,            0,
  55         GX_BASE + BC_DRAM_TOP,          0x3fffffff,
  56         GX_BASE + BC_XMAP_1,            0x60,
  57         GX_BASE + BC_XMAP_2,            0,
  58         GX_BASE + BC_XMAP_3,            0,
  59         GX_BASE + MC_BANK_CFG,          0x00700070,
  60         GX_BASE + MC_MEM_CNTRL1,        XBUSARB,
  61         GX_BASE + MC_GBASE_ADD,         0xff,
  62         0,                              0
  63         };
  64
  65 unsigned long *gxPtr = gx_setup_table;
  66 unsigned long *gxdPtr;
  67 unsigned long addr;
  68
  69         while(addr = *gxPtr++) {
  70                 gxdPtr = (unsigned long *)addr;
  71                 *gxdPtr = *gxPtr++;
  72         }
  73 }
  74 #endif
  75
  76 static void model_gx2_init(device_t dev)
  77 {
  78         void do_vsmbios(void);
  79 #if 0
  80         gx2_cpu_setup();
  81         gx2_gx_setup();
  82 #endif
  83         printk_debug("model_gx2_init\n");
  84         /* Turn on caching if we haven't already */
  85         x86_enable_cache();
  86
  87         /* Enable the local cpu apics */
  88         setup_lapic();
  89
  90         do_vsmbios();
  91         printk_debug("model_gx2_init DONE\n");
  92 };
  93
  94 static struct device_operations cpu_dev_ops = {
  95         .init   = model_gx2_init,
  96 };
  97
  98 static struct cpu_device_id cpu_table[] = {
  99         { X86_VENDOR_CYRIX, 0x0540 },
 100         { 0, 0 },
 101 };
 102
 103 static struct cpu_driver driver __cpu_driver = {
 104         .ops      = &cpu_dev_ops,
 105         .id_table = cpu_table,
 106 };