1 #include <console/console.h>
2 #include <device/device.h>
3 #include <device/pci.h>
6 #include <cpu/x86/lapic.h>
7 #include <cpu/x86/cache.h>
10 #include <cpu/amd/gx2def.h>
13 static void gx2_cpu_setup(void)
16 unsigned char cpu_table[] = {
17 0xc1, 0x00, /* NO SMIs */
18 0xc3, 0x14, /* Enable CPU config register */
20 0xb8, GX_BASE>>30, /* Enable GXBASE address */
23 0xc3, 0xf8, /* Enable CPU config register */
26 unsigned char *cPtr = cpu_table;
28 while(rreg = *cPtr++) {
29 unsigned char rval = *cPtr++;
34 outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
35 if(inb(0x23) > 0x63) { /* Rev greater than R3 */
37 outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
40 outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
43 outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
44 /* Bit 2 Incrementor margin 10 */
49 static void gx2_gx_setup(void)
51 unsigned long gx_setup_table[] = {
52 GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
53 GX_BASE + DC_GENERAL_CFG, 0,
54 GX_BASE + DC_UNLOCK, 0,
55 GX_BASE + BC_DRAM_TOP, 0x3fffffff,
56 GX_BASE + BC_XMAP_1, 0x60,
57 GX_BASE + BC_XMAP_2, 0,
58 GX_BASE + BC_XMAP_3, 0,
59 GX_BASE + MC_BANK_CFG, 0x00700070,
60 GX_BASE + MC_MEM_CNTRL1, XBUSARB,
61 GX_BASE + MC_GBASE_ADD, 0xff,
65 unsigned long *gxPtr = gx_setup_table;
66 unsigned long *gxdPtr;
69 while(addr = *gxPtr++) {
70 gxdPtr = (unsigned long *)addr;
76 #include "cpureginit.c"
78 static void model_gx2_init(device_t dev)
80 void do_vsmbios(void);
85 printk_debug("model_gx2_init\n");
86 /* Turn on caching if we haven't already */
89 /* Enable the local cpu apics */
93 printk_debug("model_gx2_init DONE\n");
96 static struct device_operations cpu_dev_ops = {
97 .init = model_gx2_init,
100 static struct cpu_device_id cpu_table[] = {
101 { X86_VENDOR_CYRIX, 0x0540 },
105 static struct cpu_driver driver __cpu_driver = {
107 .id_table = cpu_table,