1 /* Needed so the AMD K8 runs correctly. */
2 #include <console/console.h>
3 #include <cpu/x86/msr.h>
4 #include <cpu/amd/mtrr.h>
5 #include <device/device.h>
6 #include <device/device.h>
7 #include <device/pci.h>
9 #include <cpu/x86/msr.h>
10 #include <cpu/x86/pae.h>
11 #include <pc80/mc146818rtc.h>
12 #include <cpu/x86/lapic.h>
13 #include "../../../northbridge/amd/amdk8/amdk8.h"
14 #include "../../../northbridge/amd/amdk8/cpu_rev.c"
16 #include <cpu/x86/cache.h>
17 #include <cpu/x86/mtrr.h>
18 #include <cpu/x86/mem.h>
19 #include "model_fxx_msr.h"
21 #define MCI_STATUS 0x401
23 static inline msr_t rdmsr_amd(unsigned index)
26 __asm__ __volatile__ (
28 : "=a" (result.lo), "=d" (result.hi)
29 : "c" (index), "D" (0x9c5a203a)
34 static inline void wrmsr_amd(unsigned index, msr_t msr)
36 __asm__ __volatile__ (
39 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
46 #define ZERO_CHUNK_KB 0x800UL /* 2M */
47 #define TOLM_KB 0x400000UL
54 struct mtrr mtrrs[MTRR_COUNT];
55 msr_t top_mem, top_mem2;
59 static void save_mtrr_state(struct mtrr_state *state)
62 for(i = 0; i < MTRR_COUNT; i++) {
63 state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
64 state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
66 state->top_mem = rdmsr(TOP_MEM);
67 state->top_mem2 = rdmsr(TOP_MEM2);
68 state->def_type = rdmsr(MTRRdefType_MSR);
71 static void restore_mtrr_state(struct mtrr_state *state)
76 for(i = 0; i < MTRR_COUNT; i++) {
77 wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
78 wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
80 wrmsr(TOP_MEM, state->top_mem);
81 wrmsr(TOP_MEM2, state->top_mem2);
82 wrmsr(MTRRdefType_MSR, state->def_type);
89 static void print_mtrr_state(struct mtrr_state *state)
92 for(i = 0; i < MTRR_COUNT; i++) {
93 printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
95 state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
96 state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
98 printk_debug("top_mem: %08x%08x\n",
99 state->top_mem.hi, state->top_mem.lo);
100 printk_debug("top_mem2: %08x%08x\n",
101 state->top_mem2.hi, state->top_mem2.lo);
102 printk_debug("def_type: %08x%08x\n",
103 state->def_type.hi, state->def_type.lo);
107 static void set_init_ecc_mtrrs(void)
113 /* First clear all of the msrs to be safe */
114 for(i = 0; i < MTRR_COUNT; i++) {
116 zero.lo = zero.hi = 0;
117 wrmsr(MTRRphysBase_MSR(i), zero);
118 wrmsr(MTRRphysMask_MSR(i), zero);
121 /* Write back cache the first 1MB */
123 msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
124 wrmsr(MTRRphysBase_MSR(0), msr);
126 msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
127 wrmsr(MTRRphysMask_MSR(0), msr);
129 /* Set the default type to write combining */
131 msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
132 wrmsr(MTRRdefType_MSR, msr);
134 /* Set TOP_MEM to 4G */
143 static void init_ecc_memory(void)
145 unsigned long startk, begink, endk;
147 struct mtrr_state mtrr_state;
148 device_t f1_dev, f2_dev, f3_dev;
150 int enable_scrubbing;
153 /* For now there is a 1-1 mapping between node_id and cpu_id */
156 f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
158 die("Cannot find cpu function 1\n");
160 f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2));
162 die("Cannot find cpu function 2\n");
164 f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3));
166 die("Cannot find cpu function 3\n");
169 /* See if we scrubbing should be enabled */
170 enable_scrubbing = 1;
171 get_option(&enable_scrubbing, "hw_scrubber");
173 /* Enable cache scrubbing at the lowest possible rate */
174 if (enable_scrubbing) {
175 pci_write_config32(f3_dev, SCRUB_CONTROL,
176 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
178 pci_write_config32(f3_dev, SCRUB_CONTROL,
179 (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
180 printk_debug("Scrubbing Disabled\n");
184 /* If ecc support is not enabled don't touch memory */
185 dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
186 if (!(dcl & DCL_DimmEccEn)) {
190 startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
191 endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
193 /* Don't start too early */
195 if (begink < CONFIG_LB_MEM_TOPK) {
196 begink = CONFIG_LB_MEM_TOPK;
198 printk_debug("Clearing memory %uK - %uK: ", startk, endk);
200 /* Save the normal state */
201 save_mtrr_state(&mtrr_state);
203 /* Switch to the init ecc state */
204 set_init_ecc_mtrrs();
207 /* Walk through 2M chunks and zero them */
208 for(basek = begink; basek < endk; basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
209 unsigned long limitk;
213 /* Report every 64M */
214 if ((basek % (64*1024)) == 0) {
215 /* Restore the normal state */
217 restore_mtrr_state(&mtrr_state);
220 /* Print a status message */
221 printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
223 /* Return to the initialization state */
224 set_init_ecc_mtrrs();
227 limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
231 size = (limitk - basek) << 10;
232 addr = map_2M_page(basek >> 11);
233 addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
234 if (addr == MAPPING_ERROR) {
238 /* clear memory 2M (limitk - basek) */
239 clear_memory(addr, size);
241 /* Restore the normal state */
243 restore_mtrr_state(&mtrr_state);
246 /* Set the scrub base address registers */
247 pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
248 pci_write_config32(f3_dev, SCRUB_ADDR_HIGH, startk >> 22);
250 /* Enable the scrubber? */
251 if (enable_scrubbing) {
252 /* Enable scrubbing at the lowest possible rate */
253 pci_write_config32(f3_dev, SCRUB_CONTROL,
254 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
257 printk_debug(" done\n");
260 static inline void k8_errata(void)
263 if (is_cpu_pre_c0()) {
265 msr = rdmsr(HWCR_MSR);
267 wrmsr(HWCR_MSR, msr);
270 msr = rdmsr_amd(BU_CFG_MSR);
271 msr.hi |= (1 << (45 - 32));
272 wrmsr_amd(BU_CFG_MSR, msr);
275 msr = rdmsr_amd(DC_CFG_MSR);
277 wrmsr_amd(DC_CFG_MSR, msr);
280 /* I can't touch this msr on early buggy cpus */
281 if (!is_cpu_pre_b3()) {
284 msr = rdmsr(NB_CFG_MSR);
287 if (!is_cpu_pre_c0()) {
288 /* Erratum 86 Disable data masking on C0 and
289 * later processor revs.
290 * FIXME this is only needed if ECC is enabled.
292 msr.hi |= 1 << (36 - 32);
294 wrmsr(NB_CFG_MSR, msr);
298 if (!is_cpu_pre_c0()) {
299 msr = rdmsr_amd(DC_CFG_MSR);
301 wrmsr_amd(DC_CFG_MSR, msr);
305 msr = rdmsr_amd(IC_CFG_MSR);
307 wrmsr_amd(IC_CFG_MSR, msr);
309 /* Erratum 91 prefetch miss is handled in the kernel */
312 void model_fxx_init(device_t dev)
314 unsigned long mmio_basek, tomk;
318 /* Turn on caching if we haven't already */
325 /* zero the machine check error status registers */
329 wrmsr(MCI_STATUS + (i*4),msr);
336 /* Is this a bad location? In particular can another node prefecth
337 * data from this node before we have initialized it?
341 /* Enable the local cpu apics */
345 static struct device_operations cpu_dev_ops = {
346 .init = model_fxx_init,
348 static struct cpu_device_id cpu_table[] = {
349 { X86_VENDOR_AMD, 0xf50 }, /* B3 */
350 { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
351 { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
352 { X86_VENDOR_AMD, 0xf48 },
354 { X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
355 { X86_VENDOR_AMD, 0xf4A },
356 { X86_VENDOR_AMD, 0xf7A },
357 { X86_VENDOR_AMD, 0xfc0 }, /* DH7-CG */
358 { X86_VENDOR_AMD, 0xfe0 },
359 { X86_VENDOR_AMD, 0xff0 },
360 { X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
361 { X86_VENDOR_AMD, 0xfb2 },
365 static struct cpu_driver model_fxx __cpu_driver = {
367 .id_table = cpu_table,