1 /* Needed so the AMD K8 runs correctly. */
2 /* this should be done by Eric
3 * 2004.11 yhlu add d0 e0 support
4 * 2004.12 yhlu add dual core support
5 * 2005.02 yhlu add e0 memory hole support
8 * 2005.08 yhlu add microcode support
10 #include <console/console.h>
11 #include <cpu/x86/msr.h>
12 #include <cpu/amd/mtrr.h>
13 #include <device/device.h>
14 #include <device/pci.h>
16 #include <cpu/x86/msr.h>
17 #include <cpu/x86/pae.h>
18 #include <pc80/mc146818rtc.h>
19 #include <cpu/x86/lapic.h>
21 #include "../../../northbridge/amd/amdk8/amdk8.h"
23 #include <cpu/amd/model_fxx_rev.h>
25 #include <cpu/x86/cache.h>
26 #include <cpu/x86/mtrr.h>
27 #include <cpu/x86/mem.h>
29 #include <cpu/amd/dualcore.h>
31 #include <cpu/amd/model_fxx_msr.h>
33 void cpus_ready_for_init(void)
35 #if MEM_TRAIN_SEQ == 1
36 struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
37 // wait for ap memory to trained
38 wait_all_core0_mem_trained(sysinfox);
43 #if K8_REV_F_SUPPORT == 0
44 int is_e0_later_in_bsp(int nodeid)
49 if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
50 return !is_cpu_pre_e0();
52 // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
54 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
56 val_old = pci_read_config32(dev, 0x80);
59 pci_write_config32(dev, 0x80, val);
60 val = pci_read_config32(dev, 0x80);
61 e0_later = !!(val & (1<<3));
62 if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
63 pci_write_config32(dev, 0x80, val_old); // restore it
70 #if K8_REV_F_SUPPORT == 1
71 int is_cpu_f0_in_bsp(int nodeid)
75 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
76 dword = pci_read_config32(dev, 0xfc);
77 return (dword & 0xfff00) == 0x40f00;
81 #define MCI_STATUS 0x401
83 static inline msr_t rdmsr_amd(unsigned index)
86 __asm__ __volatile__ (
88 : "=a" (result.lo), "=d" (result.hi)
89 : "c" (index), "D" (0x9c5a203a)
94 static inline void wrmsr_amd(unsigned index, msr_t msr)
96 __asm__ __volatile__ (
99 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
105 #define ZERO_CHUNK_KB 0x800UL /* 2M */
106 #define TOLM_KB 0x400000UL
113 struct mtrr mtrrs[MTRR_COUNT];
114 msr_t top_mem, top_mem2;
118 static void save_mtrr_state(struct mtrr_state *state)
121 for(i = 0; i < MTRR_COUNT; i++) {
122 state->mtrrs[i].base = rdmsr(MTRRphysBase_MSR(i));
123 state->mtrrs[i].mask = rdmsr(MTRRphysMask_MSR(i));
125 state->top_mem = rdmsr(TOP_MEM);
126 state->top_mem2 = rdmsr(TOP_MEM2);
127 state->def_type = rdmsr(MTRRdefType_MSR);
130 static void restore_mtrr_state(struct mtrr_state *state)
135 for(i = 0; i < MTRR_COUNT; i++) {
136 wrmsr(MTRRphysBase_MSR(i), state->mtrrs[i].base);
137 wrmsr(MTRRphysMask_MSR(i), state->mtrrs[i].mask);
139 wrmsr(TOP_MEM, state->top_mem);
140 wrmsr(TOP_MEM2, state->top_mem2);
141 wrmsr(MTRRdefType_MSR, state->def_type);
148 static void print_mtrr_state(struct mtrr_state *state)
151 for(i = 0; i < MTRR_COUNT; i++) {
152 printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
154 state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
155 state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
157 printk_debug("top_mem: %08x%08x\n",
158 state->top_mem.hi, state->top_mem.lo);
159 printk_debug("top_mem2: %08x%08x\n",
160 state->top_mem2.hi, state->top_mem2.lo);
161 printk_debug("def_type: %08x%08x\n",
162 state->def_type.hi, state->def_type.lo);
166 static void set_init_ecc_mtrrs(void)
172 /* First clear all of the msrs to be safe */
173 for(i = 0; i < MTRR_COUNT; i++) {
175 zero.lo = zero.hi = 0;
176 wrmsr(MTRRphysBase_MSR(i), zero);
177 wrmsr(MTRRphysMask_MSR(i), zero);
180 /* Write back cache the first 1MB */
182 msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
183 wrmsr(MTRRphysBase_MSR(0), msr);
185 msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
186 wrmsr(MTRRphysMask_MSR(0), msr);
188 /* Set the default type to write combining */
190 msr.lo = 0xc00 | MTRR_TYPE_WRCOMB;
191 wrmsr(MTRRdefType_MSR, msr);
193 /* Set TOP_MEM to 4G */
201 static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
203 unsigned long limitk;
207 /* Report every 64M */
208 if ((basek % (64*1024)) == 0) {
210 /* Restore the normal state */
212 restore_mtrr_state(mtrr_state);
215 /* Print a status message */
216 printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
218 /* Return to the initialization state */
219 set_init_ecc_mtrrs();
224 limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
226 /* couldn't happen, memory must on 2M boundary */
231 size = (limitk - basek) << 10;
232 addr = map_2M_page(basek >> 11);
233 if (addr == MAPPING_ERROR) {
234 printk_err("Cannot map page: %lx\n", basek >> 11);
238 /* clear memory 2M (limitk - basek) */
239 addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
240 clear_memory(addr, size);
243 static void init_ecc_memory(unsigned node_id)
245 unsigned long startk, begink, endk;
246 unsigned long hole_startk = 0;
248 struct mtrr_state mtrr_state;
250 device_t f1_dev, f2_dev, f3_dev;
251 int enable_scrubbing;
254 f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1));
256 die("Cannot find cpu function 1\n");
258 f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2));
260 die("Cannot find cpu function 2\n");
262 f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3));
264 die("Cannot find cpu function 3\n");
267 /* See if we scrubbing should be enabled */
268 enable_scrubbing = 1;
269 get_option(&enable_scrubbing, "hw_scrubber");
271 /* Enable cache scrubbing at the lowest possible rate */
272 if (enable_scrubbing) {
273 pci_write_config32(f3_dev, SCRUB_CONTROL,
274 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_NONE << 0));
276 pci_write_config32(f3_dev, SCRUB_CONTROL,
277 (SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
278 printk_debug("Scrubbing Disabled\n");
282 /* If ecc support is not enabled don't touch memory */
283 dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
284 if (!(dcl & DCL_DimmEccEn)) {
285 printk_debug("ECC Disabled\n");
289 startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
290 endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
292 #if HW_MEM_HOLE_SIZEK != 0
293 #if K8_REV_F_SUPPORT == 0
294 if (!is_cpu_pre_e0())
299 val = pci_read_config32(f1_dev, 0xf0);
301 hole_startk = ((val & (0xff<<24)) >> 10);
303 #if K8_REV_F_SUPPORT == 0
309 /* Don't start too early */
311 if (begink < CONFIG_LB_MEM_TOPK) {
312 begink = CONFIG_LB_MEM_TOPK;
315 printk_debug("Clearing memory %luK - %luK: ", begink, endk);
317 /* Save the normal state */
318 save_mtrr_state(&mtrr_state);
320 /* Switch to the init ecc state */
321 set_init_ecc_mtrrs();
324 /* Walk through 2M chunks and zero them */
325 #if HW_MEM_HOLE_SIZEK != 0
326 /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
327 if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
328 for(basek = begink; basek < hole_startk;
329 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
331 clear_2M_ram(basek, &mtrr_state);
333 for(basek = 4*1024*1024; basek < endk;
334 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
336 clear_2M_ram(basek, &mtrr_state);
341 for(basek = begink; basek < endk;
342 basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
344 clear_2M_ram(basek, &mtrr_state);
348 /* Restore the normal state */
350 restore_mtrr_state(&mtrr_state);
353 /* Set the scrub base address registers */
354 pci_write_config32(f3_dev, SCRUB_ADDR_LOW, startk << 10);
355 pci_write_config32(f3_dev, SCRUB_ADDR_HIGH, startk >> 22);
357 /* Enable the scrubber? */
358 if (enable_scrubbing) {
359 /* Enable scrubbing at the lowest possible rate */
360 pci_write_config32(f3_dev, SCRUB_CONTROL,
361 (SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
364 printk_debug(" done\n");
368 static inline void k8_errata(void)
371 #if K8_REV_F_SUPPORT == 0
372 if (is_cpu_pre_c0()) {
374 msr = rdmsr(HWCR_MSR);
376 wrmsr(HWCR_MSR, msr);
379 msr = rdmsr_amd(BU_CFG_MSR);
380 msr.hi |= (1 << (45 - 32));
381 wrmsr_amd(BU_CFG_MSR, msr);
384 msr = rdmsr_amd(DC_CFG_MSR);
386 wrmsr_amd(DC_CFG_MSR, msr);
389 /* I can't touch this msr on early buggy cpus */
390 if (!is_cpu_pre_b3()) {
393 msr = rdmsr(NB_CFG_MSR);
396 if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
397 /* D0 later don't need it */
398 /* Erratum 86 Disable data masking on C0 and
399 * later processor revs.
400 * FIXME this is only needed if ECC is enabled.
402 msr.hi |= 1 << (36 - 32);
404 wrmsr(NB_CFG_MSR, msr);
408 if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
409 msr = rdmsr_amd(DC_CFG_MSR);
411 wrmsr_amd(DC_CFG_MSR, msr);
415 if (is_cpu_pre_d0()) {
416 msr = rdmsr_amd(IC_CFG_MSR);
418 wrmsr_amd(IC_CFG_MSR, msr);
421 /* Erratum 91 prefetch miss is handled in the kernel */
423 /* Erratum 106 ... */
424 msr = rdmsr_amd(LS_CFG_MSR);
426 wrmsr_amd(LS_CFG_MSR, msr);
428 /* Erratum 107 ... */
429 msr = rdmsr_amd(BU_CFG_MSR);
430 msr.hi |= 1 << (43 - 32);
431 wrmsr_amd(BU_CFG_MSR, msr);
435 msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
437 wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
441 #if K8_REV_F_SUPPORT == 0
442 if (!is_cpu_pre_e0())
445 /* Erratum 110 ... */
446 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
448 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
452 msr = rdmsr(HWCR_MSR);
454 wrmsr(HWCR_MSR, msr);
456 #if K8_REV_F_SUPPORT == 1
458 msr = rdmsr(NB_CFG_MSR);
460 wrmsr(NB_CFG_MSR, msr);
465 extern void model_fxx_update_microcode(unsigned cpu_deviceid);
466 int init_processor_name(void);
468 #if CONFIG_USBDEBUG_DIRECT
469 static unsigned ehci_debug_addr;
472 void model_fxx_init(device_t dev)
476 struct node_core_id id;
477 #if CONFIG_LOGICAL_CPUS == 1
481 #if K8_REV_F_SUPPORT == 1
482 struct cpuinfo_x86 c;
484 get_fms(&c, dev->device);
487 #if CONFIG_USBDEBUG_DIRECT
489 ehci_debug_addr = get_ehci_debug();
493 /* Turn on caching if we haven't already */
498 #if CONFIG_USBDEBUG_DIRECT
499 set_ehci_debug(ehci_debug_addr);
502 /* Update the microcode */
503 model_fxx_update_microcode(dev->device);
507 /* zero the machine check error status registers */
511 wrmsr(MCI_STATUS + (i*4),msr);
516 /* Set SMMLOCK to avoid exploits messing with SMM */
517 msr = rdmsr(HWCR_MSR);
519 wrmsr(HWCR_MSR, msr);
521 /* Set the processor name string */
522 init_processor_name();
526 /* Enable the local cpu apics */
529 #if CONFIG_LOGICAL_CPUS == 1
530 siblings = cpuid_ecx(0x80000008) & 0xff;
533 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
535 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
537 msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
538 msr.lo = (siblings+1)<<16;
539 wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
541 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
542 msr.hi |= 1<<(33-32);
543 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
548 id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
550 /* Is this a bad location? In particular can another node prefecth
551 * data from this node before we have initialized it?
553 if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
555 #if CONFIG_LOGICAL_CPUS==1
556 /* Start up my cpu siblings */
557 // if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
562 static struct device_operations cpu_dev_ops = {
563 .init = model_fxx_init,
566 static struct cpu_device_id cpu_table[] = {
567 #if K8_REV_F_SUPPORT == 0
568 { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
569 { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
570 { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
571 { X86_VENDOR_AMD, 0xf58 }, /* SH-C0 (socket 940) */
572 { X86_VENDOR_AMD, 0xf48 }, /* SH-C0 (socket 754) */
573 { X86_VENDOR_AMD, 0xf5a }, /* SH-CG (socket 940) */
574 { X86_VENDOR_AMD, 0xf4a }, /* SH-CG (socket 754) */
575 { X86_VENDOR_AMD, 0xf7a }, /* SH-CG (socket 939) */
576 { X86_VENDOR_AMD, 0xfc0 }, /* DH-CG (socket 754) */
577 { X86_VENDOR_AMD, 0xfe0 }, /* DH-CG (socket 754) */
578 { X86_VENDOR_AMD, 0xff0 }, /* DH-CG (socket 939) */
579 { X86_VENDOR_AMD, 0xf82 }, /* CH-CG (socket 754) */
580 { X86_VENDOR_AMD, 0xfb2 }, /* CH-CG (socket 939) */
583 { X86_VENDOR_AMD, 0x10f50 }, /* SH-D0 (socket 940) */
584 { X86_VENDOR_AMD, 0x10f40 }, /* SH-D0 (socket 754) */
585 { X86_VENDOR_AMD, 0x10f70 }, /* SH-D0 (socket 939) */
586 { X86_VENDOR_AMD, 0x10fc0 }, /* DH-D0 (socket 754) */
587 { X86_VENDOR_AMD, 0x10ff0 }, /* DH-D0 (socket 939) */
588 { X86_VENDOR_AMD, 0x10f80 }, /* CH-D0 (socket 754) */
589 { X86_VENDOR_AMD, 0x10fb0 }, /* CH-D0 (socket 939) */
592 { X86_VENDOR_AMD, 0x20f50 }, /* SH-E0 */
593 { X86_VENDOR_AMD, 0x20f40 },
594 { X86_VENDOR_AMD, 0x20f70 },
595 { X86_VENDOR_AMD, 0x20fc0 }, /* DH-E3 (socket 754) */
596 { X86_VENDOR_AMD, 0x20ff0 }, /* DH-E3 (socket 939) */
597 { X86_VENDOR_AMD, 0x20f10 }, /* JH-E1 (socket 940) */
598 { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 (socket 940) */
599 { X86_VENDOR_AMD, 0x20f71 }, /* SH-E4 (socket 939) */
600 { X86_VENDOR_AMD, 0x20fb1 }, /* BH-E4 (socket 939) */
601 { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 (socket 754) */
602 { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 (socket 939) */
603 { X86_VENDOR_AMD, 0x20fc2 }, /* DH-E6 (socket 754) */
604 { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 (socket 940) */
605 { X86_VENDOR_AMD, 0x20f32 }, /* JH-E6 (socket 939) */
606 { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
609 #if K8_REV_F_SUPPORT == 1
613 * See Revision Guide for AMD NPT Family 0Fh Processors,
614 * Publication #33610, Revision: 3.30, February 2008.
616 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
618 { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 (socket F/1207) */
619 { X86_VENDOR_AMD, 0x40f70 }, /* SH-F0 (socket AM2) */
620 { X86_VENDOR_AMD, 0x40f40 }, /* SH-F0 (socket S1g1) */
621 { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 (socket F/1207) */
622 { X86_VENDOR_AMD, 0x40f31 }, /* JH-F1 (socket AM2) */
623 { X86_VENDOR_AMD, 0x40f01 }, /* JH-F1 (socket S1g1) */
625 { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 (socket F/1207) */
626 { X86_VENDOR_AMD, 0x40f32 }, /* JH-F2 (socket AM2) */
627 { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 (socket AM2) */
628 { X86_VENDOR_AMD, 0x40f82 }, /* BH-F2 (socket S1g1) */
629 { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 (socket AM2) */
630 { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 (socket AM2) */
631 { X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */
632 { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */
633 { X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */
634 { X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */
635 { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */
636 { X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */
637 { X86_VENDOR_AMD, 0x60f81 }, /* BH-G1 (socket S1g1) */
638 { X86_VENDOR_AMD, 0x60fb2 }, /* BH-G2 (socket AM2) */
639 { X86_VENDOR_AMD, 0x60f82 }, /* BH-G2 (socket S1g1) */
640 { X86_VENDOR_AMD, 0x70ff1 }, /* DH-G1 (socket AM2) */
641 { X86_VENDOR_AMD, 0x60ff2 }, /* DH-G2 (socket AM2) */
642 { X86_VENDOR_AMD, 0x60fc2 }, /* DH-G2 (socket S1g1) */
643 { X86_VENDOR_AMD, 0x70fc2 }, /* DH-G2 (socket S1g1) */
649 static const struct cpu_driver model_fxx __cpu_driver = {
651 .id_table = cpu_table,