2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <cpu/x86/msr.h>
22 #include <cpu/amd/mtrr.h>
23 #include <device/device.h>
24 #include <device/pci.h>
26 #include <cpu/x86/msr.h>
27 #include <cpu/x86/pae.h>
28 #include <pc80/mc146818rtc.h>
29 #include <cpu/x86/lapic.h>
30 #include "northbridge/amd/amdfam10/amdfam10.h"
31 #include <cpu/amd/model_10xxx_rev.h>
33 #include <cpu/x86/cache.h>
34 #include <cpu/x86/mtrr.h>
35 #include <cpu/amd/multicore.h>
36 #include <cpu/amd/model_10xxx_msr.h>
38 #define MCI_STATUS 0x401
40 msr_t rdmsr_amd(u32 index)
45 :"=a"(result.lo), "=d"(result.hi)
46 :"c"(index), "D"(0x9c5a203a)
51 void wrmsr_amd(u32 index, msr_t msr)
56 :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
60 static void model_10xxx_init(device_t dev)
64 struct node_core_id id;
65 #if CONFIG_LOGICAL_CPUS == 1
69 id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
70 printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
72 /* Turn on caching if we haven't already */
79 /* zero the machine check error status registers */
82 for (i = 0; i < 5; i++) {
83 wrmsr(MCI_STATUS + (i * 4), msr);
88 /* Enable the local cpu apics */
91 /* Set the processor name string */
92 init_processor_name();
94 #if CONFIG_LOGICAL_CPUS == 1
95 siblings = cpuid_ecx(0x80000008) & 0xff;
98 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
100 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
102 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
103 msr.hi |= 1 << (33 - 32);
104 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
106 printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
109 /* DisableCf8ExtCfg */
110 msr = rdmsr(NB_CFG_MSR);
111 msr.hi &= ~(1 << (46 - 32));
112 wrmsr(NB_CFG_MSR, msr);
114 msr = rdmsr(BU_CFG2_MSR);
115 /* Clear ClLinesToNbDis */
116 msr.lo &= ~(1 << 15);
117 /* Clear bit 35 as per Erratum 343 */
118 msr.hi &= ~(1 << (35-32));
119 wrmsr(BU_CFG2_MSR, msr);
121 /* Write protect SMM space with SMMLOCK. */
122 msr = rdmsr(HWCR_MSR);
124 wrmsr(HWCR_MSR, msr);
128 static struct device_operations cpu_dev_ops = {
129 .init = model_10xxx_init,
132 static struct cpu_device_id cpu_table[] = {
134 { X86_VENDOR_AMD, 0x100f00 }, /* SH-F0 L1 */
135 { X86_VENDOR_AMD, 0x100f10 }, /* M2 */
136 { X86_VENDOR_AMD, 0x100f20 }, /* S1g1 */
137 { X86_VENDOR_AMD, 0x100f21 },
138 { X86_VENDOR_AMD, 0x100f2A },
139 { X86_VENDOR_AMD, 0x100f22 },
140 { X86_VENDOR_AMD, 0x100f23 },
141 { X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
142 { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
143 { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
144 { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
145 { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
146 { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
147 { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
148 { X86_VENDOR_AMD, 0x100F81 }, /* HY-D1 */
152 static const struct cpu_driver model_10xxx __cpu_driver = {
154 .id_table = cpu_table,