2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
23 #ifndef FAM10_SET_FIDVID
24 #define FAM10_SET_FIDVID 1
27 #ifndef FAM10_SET_FIDVID_CORE0_ONLY
28 /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores,
29 Need to do every AP to set common FID/VID*/
30 #define FAM10_SET_FIDVID_CORE0_ONLY 0
33 static inline void print_initcpu8 (const char *strval, u8 val)
35 printk_debug("%s%02x\n", strval, val);
38 static inline void print_initcpu8_nocr (const char *strval, u8 val)
40 printk_debug("%s%02x", strval, val);
44 static inline void print_initcpu16 (const char *strval, u16 val)
46 printk_debug("%s%04x\n", strval, val);
50 static inline void print_initcpu(const char *strval, u32 val)
52 printk_debug("%s%08x\n", strval, val);
56 void update_microcode(u32 cpu_deviceid);
57 static void prep_fid_change(void);
58 static void init_fidvid_stage2(u32 apicid, u32 nodeid);
59 void cpuSetAMDMSR(void);
61 #if PCI_IO_CFG_EXT == 1
62 static inline void set_EnableCf8ExtCfg(void)
64 // set the NB_CFG[46]=1;
66 msr = rdmsr(NB_CFG_MSR);
67 // EnableCf8ExtCfg: We need that to access PCI_IO_CFG_EXT 4K range
68 msr.hi |= (1<<(46-32));
69 wrmsr(NB_CFG_MSR, msr);
72 static inline void set_EnableCf8ExtCfg(void) { }
77 #define PCI_MMIO_BASE 0xfe000000
78 /* because we will use gs to store hi, so need to make sure lo can start
79 from 0, So PCI_MMIO_BASE & 0x00ffffff should be equal to 0*/
81 static inline void set_pci_mmio_conf_reg(void)
85 msr = rdmsr(0xc0010058);
86 msr.lo &= ~(0xfff00000 | (0xf << 2));
87 // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space
88 msr.lo |= ((8+PCI_BUS_SEGN_BITS) << 2) | (1 << 0);
89 msr.hi &= ~(0x0000ffff);
90 msr.hi |= (PCI_MMIO_BASE >> (32-8));
91 wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
93 //mtrr for that range?
94 // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
98 msr.hi = (PCI_MMIO_BASE >> (32-8));
100 wrmsr(0xc0000101, msr); //GS_Base Reg
108 typedef void (*process_ap_t)(u32 apicid, void *gp);
110 //core_range = 0 : all cores
111 //core range = 1 : core 0 only
112 //core range = 2 : cores other than core0
114 static void for_each_ap(u32 bsp_apicid, u32 core_range,
115 process_ap_t process_ap, void *gp)
117 // here assume the OS don't change our apicid
122 u32 disable_siblings;
126 u32 ApicIdCoreIdSize;
128 /* get_nodes define in ht_wrapper.c */
131 disable_siblings = !CONFIG_LOGICAL_CPUS;
133 #if CONFIG_LOGICAL_CPUS == 1
134 if(read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) { // 0 mean quad core
135 disable_siblings = 1;
139 /* Assume that all node are same stepping, otherwise we can use use
140 nb_cfg_54 from bsp for all nodes */
141 nb_cfg_54 = read_nb_cfg_54();
143 ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf);
144 if(ApicIdCoreIdSize) {
145 siblings = ((1 << ApicIdCoreIdSize) - 1);
147 siblings = 3; //quad core
150 for (i = 0; i < nodes; i++) {
151 cores_found = get_core_num_in_bsp(i);
155 if (core_range == 2) {
161 if (disable_siblings || (core_range==1)) {
168 for (j = jstart; j <= jend; j++) {
169 ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64);
171 #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
172 #if LIFT_BSP_APIC_ID == 0
173 if( (i != 0) || (j != 0)) /* except bsp */
175 ap_apicid += APIC_ID_OFFSET;
178 if(ap_apicid == bsp_apicid) continue;
180 process_ap(ap_apicid, gp);
186 /* FIXME: Duplicate of what is in lapic.h? */
187 static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
192 lapic_wait_icr_idle();
193 lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
194 lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
198 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
199 } while (status == LAPIC_ICR_BUSY && timeout++ < 1000);
203 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
204 } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
208 if (status == LAPIC_ICR_RR_VALID) {
209 *pvalue = lapic_read(LAPIC_RRR);
216 /* Use the LAPIC timer count register to hold each cores init status */
217 #define LAPIC_MSG_REG 0x380
220 #if FAM10_SET_FIDVID == 1
221 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
224 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
226 printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
230 static unsigned wait_cpu_state(u32 apicid, u32 state)
236 if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) continue;
237 if ((readback & 0x3f) == state) {
239 break; //target cpu is in stage started
252 static void wait_ap_started(u32 ap_apicid, void *gp )
255 timeout = wait_cpu_state(ap_apicid, 0x13); // started
257 print_initcpu8_nocr("* AP ", ap_apicid);
258 print_initcpu(" didn't start timeout:", timeout);
261 print_initcpu8_nocr("AP started: ", ap_apicid);
266 static void wait_all_other_cores_started(u32 bsp_apicid)
268 // all aps other than core0
269 print_debug("started ap apicid: ");
270 for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
275 static void allow_all_aps_stop(u32 bsp_apicid)
277 /* Called by the BSP to indicate AP can stop */
279 /* FIXME Do APs use this?
280 Looks like wait_till_sysinfo_in_ram is used instead. */
282 // allow aps to stop use 6 bits for state
283 lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14);
286 static void enable_apic_ext_id(u32 node)
290 val = pci_read_config32(NODE_HT(node), 0x68);
291 val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
292 pci_write_config32(NODE_HT(node), 0x68, val);
296 static void STOP_CAR_AND_CPU()
298 disable_cache_as_ram(); // inline
303 #ifndef MEM_TRAIN_SEQ
304 #define MEM_TRAIN_SEQ 0
307 #if RAMINIT_SYSINFO == 1
308 static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo)
310 static u32 init_cpus(u32 cpu_init_detectedx)
315 struct node_core_id id;
318 * already set early mtrr in cache_as_ram.inc
321 /* enable access pci conf via mmio*/
322 set_pci_mmio_conf_reg();
324 /* that is from initial apicid, we need nodeid and coreid
326 id = get_node_core_id_x();
328 /* NB_CFG MSR is shared between cores, so we need make sure
329 core0 is done at first --- use wait_all_core0_started */
331 set_apicid_cpuid_lo(); /* only set it on core0 */
332 set_EnableCf8ExtCfg(); /* only set it on core0 */
333 #if (ENABLE_APIC_EXT_ID == 1)
334 enable_apic_ext_id(id.nodeid);
341 #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET > 0)
342 u32 initial_apicid = get_initial_apicid();
344 #if LIFT_BSP_APIC_ID == 0
345 if( initial_apicid != 0 ) // other than bsp
348 /* use initial apic id to lift it */
349 u32 dword = lapic_read(LAPIC_ID);
350 dword &= ~(0xff << 24);
351 dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff) << 24);
353 lapic_write(LAPIC_ID, dword);
356 #if LIFT_BSP_APIC_ID == 1
357 bsp_apicid += APIC_ID_OFFSET;
362 /* get the apicid, it may be lifted already */
365 // show our apicid, nodeid, and coreid
367 if (id.nodeid!=0) //all core0 except bsp
368 print_apicid_nodeid_coreid(apicid, id, " core0: ");
370 else { //all other cores
371 print_apicid_nodeid_coreid(apicid, id, " corex: ");
375 if (cpu_init_detectedx) {
376 print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
377 print_debug("\nIssuing SOFT_RESET...\n");
382 if(!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets?
383 distinguish_cpu_resets(id.nodeid); // Also indicates we are started
386 // Mark the core as started.
387 lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x13);
390 if(apicid != bsp_apicid) {
391 /* Setup each AP's cores MSRs.
392 * This happens after HTinit.
393 * The BSP runs this code in it's own path.
395 update_microcode(cpuid_eax(1));
399 #if FAM10_SET_FIDVID == 1
400 #if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1)
401 // Run on all AP for proper FID/VID setup.
402 if(id.coreid == 0 ) // only need set fid for core0
405 // check warm(bios) reset to call stage2 otherwise do stage1
406 if (warm_reset_detect(id.nodeid)) {
407 printk_debug("init_fidvid_stage2 apicid: %02x\n", apicid);
408 init_fidvid_stage2(apicid, id.nodeid);
410 printk_debug("init_fidvid_ap(stage1) apicid: %02x\n", apicid);
411 init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
416 /* AP is ready, Wait for the BSP to get memory configured */
417 /* FIXME: many cores spinning on node0 pci register seems to be bad.
418 * Why do we need to wait? These APs are just going to go sit in a hlt.
420 //wait_till_sysinfo_in_ram();
422 set_init_ram_access();
425 printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);
432 static u32 is_core0_started(u32 nodeid)
436 device = NODE_PCI(nodeid, 0);
437 htic = pci_read_config32(device, HT_INIT_CONTROL);
438 htic &= HTIC_ColdR_Detect;
443 static void wait_all_core0_started(void)
445 /* When core0 is started, it will distingush_cpu_resets
446 . So wait for that to finish */
448 u32 nodes = get_nodes();
450 printk_debug("Wait all core0s started \n");
451 for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
452 while(!is_core0_started(i)) {}
453 print_initcpu8(" Core0 started on node: ", i);
455 printk_debug("Wait all core0s started done\n");
457 #if CONFIG_MAX_PHYSICAL_CPUS > 1
459 * void start_node(u32 node)
461 * start the core0 in node, so it can generate HT packet to feature code.
463 * This function starts the AP nodes core0s. wait_all_core0_started() in
464 * cache_as_ram_auto.c waits for all the AP to be finished before continuing
467 static void start_node(u8 node)
471 /* Enable routing table */
472 printk_debug("Start node %02x", node);
475 /* For CAR_FAM10 support, we need to set Dram base/limit for the new node */
476 pci_write_config32(NODE_MP(node), 0x44, 0);
477 pci_write_config32(NODE_MP(node), 0x40, 3);
480 /* Allow APs to make requests (ROM fetch) */
481 val=pci_read_config32(NODE_HT(node), 0x6c);
483 pci_write_config32(NODE_HT(node), 0x6c, val);
485 printk_debug(" done.\n");
490 * static void setup_remote_node(u32 node)
492 * Copy the BSP Adress Map to each AP.
494 static void setup_remote_node(u8 node)
496 /* There registers can be used with F1x114_x Address Map at the
497 same time, So must set them even 32 node */
498 static const u16 pci_reg[] = {
499 /* DRAM Base/Limits Registers */
500 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c,
501 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78,
502 0x144, 0x14c, 0x154, 0x15c, 0x164, 0x16c, 0x174, 0x17c,
503 0x140, 0x148, 0x150, 0x158, 0x160, 0x168, 0x170, 0x178,
504 /* MMIO Base/Limits Registers */
505 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc,
506 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8,
507 /* IO Base/Limits Registers */
508 0xc4, 0xcc, 0xd4, 0xdc,
509 0xc0, 0xc8, 0xd0, 0xd8,
510 /* Configuration Map Registers */
511 0xe0, 0xe4, 0xe8, 0xec,
515 printk_debug("setup_remote_node: %02x", node);
517 /* copy the default resource map from node 0 */
518 for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) {
522 value = pci_read_config32(NODE_MP(0), reg);
523 pci_write_config32(NODE_MP(node), reg, value);
526 printk_debug(" done\n");
528 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
530 void AMD_Errata281(u8 node, u32 revision, u32 platform)
532 /* Workaround for Transaction Scheduling Conflict in
533 * Northbridge Cross Bar. Implement XCS Token adjustment
534 * for ganged links. Also, perform fix up for the mixed
541 u8 nodes = get_nodes();
543 if (platform & AMD_PTYPE_SVR) {
544 /* For each node we need to check for a "broken" node */
545 if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) {
546 for (i = 0; i < nodes; i++) {
547 if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) {
554 if ((revision & (AMD_DR_B0 | AMD_DR_B1)) || mixed) {
556 /* F0X68[22:21] DsNpReqLmt0 = 01b */
557 val = pci_read_config32(NODE_PCI(node, 0), 0x68);
560 pci_write_config32(NODE_PCI(node, 0), 0x68, val);
563 val = pci_read_config32(NODE_PCI(node, 3), 0x6C);
566 pci_write_config32(NODE_PCI(node, 3), 0x6C, val);
569 val = pci_read_config32(NODE_PCI(node, 3), 0x7C);
572 pci_write_config32(NODE_PCI(node, 3), 0x7C, val);
574 /* F3X144[3:0] RspTok = 0001b */
575 val = pci_read_config32(NODE_PCI(node, 3), 0x144);
578 pci_write_config32(NODE_PCI(node, 3), 0x144, val);
580 for (i = 0; i < 3; i++) {
581 reg = 0x148 + (i * 4);
582 val = pci_read_config32(NODE_PCI(node, 3), reg);
585 pci_write_config32(NODE_PCI(node, 3), reg, val);
592 void AMD_Errata298(void)
594 /* Workaround for L2 Eviction May Occur during operation to
595 * set Accessed or dirty bit.
601 u8 nodes = get_nodes();
603 /* For each core we need to check for a "broken" node */
604 for (i = 0; i < nodes; i++) {
605 if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2)) {
613 msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */
617 msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */
620 msr = rdmsr(OSVW_ID_Length);
621 msr.lo |= 0x01; /* OS Visible Workaround - MSR */
622 wrmsr(OSVW_ID_Length, msr);
624 msr = rdmsr(OSVW_Status);
625 msr.lo |= 0x01; /* OS Visible Workaround - MSR */
626 wrmsr(OSVW_Status, msr);
629 if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) {
630 msr = rdmsr(OSVW_ID_Length);
631 msr.lo |= 0x01; /* OS Visible Workaround - MSR */
632 wrmsr(OSVW_ID_Length, msr);
638 u32 get_platform_type(void)
642 switch(SYSTEM_TYPE) {
644 ret |= AMD_PTYPE_DSK;
647 ret |= AMD_PTYPE_MOB;
650 ret |= AMD_PTYPE_SVR;
656 /* FIXME: add UMA support. */
658 /* All Fam10 are multi core */
666 * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
667 * HT Phy operations are not valid on links that aren't present, so this
668 * prevents invalid accesses.
670 * Returns the offset of the link register.
672 BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset)
676 /* get start of CPU HT Host Capabilities */
677 val = pci_read_config32(NODE_PCI(node, 0), 0x34);
682 /* Traverse through the capabilities. */
684 val = pci_read_config32(NODE_PCI(node, 0), val);
685 /* Is the capability block a HyperTransport capability block? */
686 if ((val & 0xFF) == 0x08)
687 /* Is the HT capability block an HT Host Capability? */
688 if ((val & 0xE0000000) == (1 << 29))
690 val = (val >> 8) & 0xFF;
691 } while (cap_count && val);
695 /* If requested capability found val != 0 */
704 * AMD_checkLinkType - Compare desired link characteristics using a logical
707 * Returns the link characteristic mask.
709 u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff)
714 /* Check coherency */
715 val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x18);
719 linktype |= HTPHY_LINKTYPE_COHERENT;
722 linktype |= HTPHY_LINKTYPE_NONCOHERENT;
725 val = pci_read_config32(NODE_PCI(node, 0), regoff + 0x08);
727 if (((val >> 8) & 0x0F) > 6)
728 linktype |= HTPHY_LINKTYPE_HT3;
730 linktype |= HTPHY_LINKTYPE_HT1;
734 val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170);
737 linktype |= HTPHY_LINKTYPE_GANGED;
739 linktype |= HTPHY_LINKTYPE_UNGANGED;
746 * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update
747 * a phy setting for that link.
749 void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry)
755 /* Determine this link's portal */
759 phyBase = ((u32)link << 3) | 0x180;
762 /* Get the portal control register's initial value
763 * and update it to access the desired phy register
765 phyReg = pci_read_config32(NODE_PCI(node, 4), phyBase);
767 if (fam10_htphy_default[entry].htreg > 0x1FF) {
768 phyReg &= ~HTPHY_DIRECT_OFFSET_MASK;
769 phyReg |= HTPHY_DIRECT_MAP;
771 phyReg &= ~HTPHY_OFFSET_MASK;
774 /* Now get the current phy register data
775 * LinkPhyDone = 0, LinkPhyWrite = 0 is a read
777 phyReg |= fam10_htphy_default[entry].htreg;
778 pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
781 val = pci_read_config32(NODE_PCI(node, 4), phyBase);
782 } while (!(val & HTPHY_IS_COMPLETE_MASK));
784 /* Now we have the phy register data, apply the change */
785 val = pci_read_config32(NODE_PCI(node, 4), phyBase + 4);
786 val &= ~fam10_htphy_default[entry].mask;
787 val |= fam10_htphy_default[entry].data;
788 pci_write_config32(NODE_PCI(node, 4), phyBase + 4, val);
790 /* write it through the portal to the phy
791 * LinkPhyDone = 0, LinkPhyWrite = 1 is a write
793 phyReg |= HTPHY_WRITE_CMD;
794 pci_write_config32(NODE_PCI(node, 4), phyBase, phyReg);
797 val = pci_read_config32(NODE_PCI(node, 4), phyBase);
798 } while (!(val & HTPHY_IS_COMPLETE_MASK));
802 void cpuSetAMDMSR(void)
804 /* This routine loads the CPU with default settings in fam10_msr_default
805 * table . It must be run after Cache-As-RAM has been enabled, and
806 * Hypertransport initialization has taken place. Also note
807 * that it is run on the current processor only, and only for the current
812 u32 revision, platform;
814 printk_debug("cpuSetAMDMSR ");
816 revision = mctGetLogicalCPUID(0xFF);
817 platform = get_platform_type();
819 for(i = 0; i < sizeof(fam10_msr_default)/sizeof(fam10_msr_default[0]); i++) {
820 if ((fam10_msr_default[i].revision & revision) &&
821 (fam10_msr_default[i].platform & platform)) {
822 msr = rdmsr(fam10_msr_default[i].msr);
823 msr.hi &= ~fam10_msr_default[i].mask_hi;
824 msr.hi |= fam10_msr_default[i].data_hi;
825 msr.lo &= ~fam10_msr_default[i].mask_lo;
826 msr.lo |= fam10_msr_default[i].data_lo;
827 wrmsr(fam10_msr_default[i].msr, msr);
832 printk_debug(" done\n");
836 void cpuSetAMDPCI(u8 node)
838 /* This routine loads the CPU with default settings in fam10_pci_default
839 * table . It must be run after Cache-As-RAM has been enabled, and
840 * Hypertransport initialization has taken place. Also note
841 * that it is run for the first core on each node
844 u32 revision, platform;
848 printk_debug("cpuSetAMDPCI %02d", node);
850 revision = mctGetLogicalCPUID(node);
851 platform = get_platform_type();
853 for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) {
854 if ((fam10_pci_default[i].revision & revision) &&
855 (fam10_pci_default[i].platform & platform)) {
856 val = pci_read_config32(NODE_PCI(node,
857 fam10_pci_default[i].function),
858 fam10_pci_default[i].offset);
859 val &= ~fam10_pci_default[i].mask;
860 val |= fam10_pci_default[i].data;
861 pci_write_config32(NODE_PCI(node,
862 fam10_pci_default[i].function),
863 fam10_pci_default[i].offset, val);
867 for(i = 0; i < sizeof(fam10_htphy_default)/sizeof(fam10_htphy_default[0]); i++) {
868 if ((fam10_htphy_default[i].revision & revision) &&
869 (fam10_htphy_default[i].platform & platform)) {
870 /* HT Phy settings either apply to both sublinks or have
871 * separate registers for sublink zero and one, so there
872 * will be two table entries. So, here we only loop
873 cd t * through the sublink zeros in function zero.
875 for (j = 0; j < 4; j++) {
876 if (AMD_CpuFindCapability(node, j, &offset)) {
877 if (AMD_checkLinkType(node, j, offset)
878 & fam10_htphy_default[i].linktype) {
879 AMD_SetHtPhyRegister(node, j, i);
882 /* No more capabilities,
891 /* FIXME: add UMA support and programXbarToSriReg(); */
893 AMD_Errata281(node, revision, platform);
895 /* FIXME: if the dct phy doesn't init correct it needs to reset.
896 if (revision & (AMD_DR_B2 | AMD_DR_B3))
899 printk_debug(" done\n");
903 void cpuInitializeMCA(void)
905 /* Clears Machine Check Architecture (MCA) registers, which power on
906 * containing unknown data, on currently running processor.
907 * This routine should only be executed on initial power on (cold boot),
908 * not across a warm reset because valid data is present at that time.
915 if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */
916 msr = rdmsr(MCG_CAP);
917 if (msr.lo & MCG_CTL_P){ /* MCG_CTL_P bit is set? */
920 msr.lo <<= 2; /* multiply the count by 4 */
921 reg = MC0_STA + msr.lo;
923 for (i=0; i < 4; i++) {
925 reg -=4; /* Touch status regs for each bank */
933 * finalize_node_setup()
935 * Do any additional post HT init
938 void finalize_node_setup(struct sys_info *sysinfo)
941 u8 nodes = get_nodes();
944 #if RAMINIT_SYSINFO == 1
945 /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */
946 reg = pci_read_config32(NODE_HT(0), 0x64);
947 sysinfo->sblk = (reg>>8) & 7;
949 sysinfo->nodes = nodes;
950 sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
954 for (i = 0; i < nodes; i++) {
958 #if FAM10_SET_FIDVID == 1
959 // Prep each node for FID/VID setup.
963 #if CONFIG_MAX_PHYSICAL_CPUS > 1
964 /* Skip the BSP, start at node 1 */
965 for(i=1; i<nodes; i++) {
966 setup_remote_node(i);