2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * Default MSR and errata settings.
32 } fam10_msr_default[] = {
33 { TOP_MEM2, AMD_FAM10_ALL, AMD_PTYPE_ALL,
34 0x00000000, 0x00000000,
35 0xFFFFFFFF, 0xFFFFFFFF },
37 { SYSCFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
39 3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
41 { HWCR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
43 1 << 4, 0x00000000 }, /* [INVD_WBINVD]=1 */
45 { MC4_CTL_MASK, AMD_FAM10_ALL, AMD_PTYPE_ALL,
46 0xF << 19, 0x00000000,
47 0xF << 19, 0x00000000 }, /* [RtryHt[0..3]]=1 */
49 { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR,
50 0x00000000, 0x00000004,
51 0x00000000, 0x0000000C }, /* [REQ_CTR] = 1 for Server */
53 { DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
54 0x00000000, 0x00000000,
55 0x00000000, 0x00000C00 }, /* Errata 326 */
57 { NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
59 0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
61 { BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
63 1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
65 { DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
67 1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
69 { LS_CFG, AMD_FAM10_GT_B0, AMD_PTYPE_ALL,
71 1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
73 { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
75 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */
77 { BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
79 1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */
81 /* CPUID_EXT_FEATURES */
82 { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
84 1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
86 { CPUIDFEATURES, AMD_FAM10_ALL, AMD_PTYPE_DC,
87 0x00000000, 1 << (33-32),
88 0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
93 * Default PCI and errata settings.
102 } fam10_pci_default[] = {
104 /* Function 0 - HT Config */
106 { 0, 0x68, AMD_FAM10_ALL, AMD_PTYPE_ALL,
107 0x004E4800, 0x006E6800 }, /* [19:17] for 8bit APIC config,
108 [14:13] BufPriRel = 2h [11] RspPassPW set,
109 [22:21] DsNpReqLmt = 10b */
111 /* Errata 281 Workaround */
112 { 0, 0x68, (AMD_DR_B0 | AMD_DR_B1),
113 AMD_PTYPE_SVR, 0x00200000, 0x00600000 }, /* [22:21] DsNpReqLmt0 = 01b */
115 { 0, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
116 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
118 { 0, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
119 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
121 { 0, 0xC4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
122 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
124 { 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
125 0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
127 /* Link Global Retry Control Register */
128 { 0, 0x150, AMD_FAM10_ALL, AMD_PTYPE_ALL,
129 0x00073900, 0x00073F00 },
132 * System software should program the Link Extended Control Registers[LS2En]
133 * (F0x[18C:170][8]) to 0b for all links. System software should also
134 * program Link Global Extended Control Register[ForceFullT0]
135 * (F0x16C[15:13]) to 000b */
137 { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
138 0x00000000, 0x00000100 },
139 { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
140 0x00000000, 0x00000100 },
141 { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
142 0x00000000, 0x00000100 },
143 { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
144 0x00000000, 0x00000100 },
145 { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
146 0x00000000, 0x00000100 },
147 { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
148 0x00000000, 0x00000100 },
149 { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
150 0x00000000, 0x00000100 },
151 { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
152 0x00000000, 0x00000100 },
153 { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
154 0x00000000, 0x00000100 },
156 /* Link Global Extended Control Register */
157 { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
158 0x00000014, 0x0000003F }, /* [15:13] ForceFullT0 = 0b,
159 * Set T0Time 14h per BKDG */
162 /* Function 1 - Map Init */
164 /* Before reading F1x114_x2 or F1x114_x3 software must
165 * initialize the registers or NB Array MCA errors may
166 * occur. BIOS should initialize index 0h of F1x114_x2 and
167 * F1x114_x3 to prevent reads from F1x114 from generating NB
168 * Array MCA errors. BKDG Doc #3116 Rev 1.07
171 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
172 0x20000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
174 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
175 0x00000000, 0xFFFFFFFF }, /* Clear map */
177 { 1, 0x110, AMD_FAM10_ALL, AMD_PTYPE_ALL,
178 0x30000000, 0xFFFFFFFF }, /* Select extended MMIO Base */
180 { 1, 0x114, AMD_FAM10_ALL, AMD_PTYPE_ALL,
181 0x00000000, 0xFFFFFFFF }, /* Clear map */
183 /* Function 2 - DRAM Controller */
185 /* Function 3 - Misc. Control */
186 { 3, 0x40, AMD_FAM10_ALL, AMD_PTYPE_ALL,
187 0x00000100, 0x00000100 }, /* [8] MstrAbrtEn */
189 { 3, 0x44, AMD_FAM10_ALL, AMD_PTYPE_ALL,
190 0x4A30005C, 0x4A30005C }, /* [30] SyncOnDramAdrParErrEn = 1,
191 [27] NbMcaToMstCpuEn = 1,
192 [25] DisPciCfgCpuErrRsp = 1,
193 [21] SyncOnAnyErrEn = 1,
194 [20] SyncOnWDTEn = 1,
196 [4] SyncPktPropDis = 1,
197 [3] SyncPktGenDis = 1,
198 [2] SyncOnUcEccEn = 1 */
200 /* XBAR buffer settings */
201 { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
202 0x00018052, 0x700780F7 },
204 /* Errata 281 Workaround */
205 { 3, 0x6C, ( AMD_DR_B0 | AMD_DR_B1),
206 AMD_PTYPE_SVR, 0x00010094, 0x700780F7 },
208 { 3, 0x6C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
209 0x60018051, 0x700780F7 },
211 { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_ALL,
212 0x00041153, 0x777777F7 },
214 { 3, 0x70, AMD_FAM10_ALL, AMD_PTYPE_UMA,
215 0x61221151, 0x777777F7 },
217 { 3, 0x74, AMD_FAM10_ALL, AMD_PTYPE_UMA,
218 0x00080101, 0x000F7777 },
220 { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
221 0x00090914, 0x707FFF1F },
223 /* Errata 281 Workaround */
224 { 3, 0x7C, ( AMD_DR_B0 | AMD_DR_B1),
225 AMD_PTYPE_SVR, 0x00144514, 0x707FFF1F },
227 { 3, 0x7C, AMD_FAM10_ALL, AMD_PTYPE_UMA,
228 0x00070814, 0x007FFF1F },
230 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_ALL,
231 0x00800756, 0x00F3FFFF },
233 { 3, 0x140, AMD_FAM10_ALL, AMD_PTYPE_UMA,
234 0x00C37756, 0x00F3FFFF },
236 { 3, 0x144, AMD_FAM10_ALL, AMD_PTYPE_UMA,
237 0x00000036, 0x000000FF },
239 /* Errata 281 Workaround */
240 { 3, 0x144, ( AMD_DR_B0 | AMD_DR_B1),
241 AMD_PTYPE_SVR, 0x00000001, 0x0000000F },
242 /* [3:0] RspTok = 0001b */
244 { 3, 0x148, AMD_FAM10_ALL, AMD_PTYPE_UMA,
245 0x8000052A, 0xD5FFFFFF },
247 /* ACPI Power State Control Reg1 */
248 { 3, 0x80, AMD_FAM10_ALL, AMD_PTYPE_ALL,
249 0xE6002200, 0xFFFFFFFF },
251 /* ACPI Power State Control Reg2 */
252 { 3, 0x84, AMD_FAM10_ALL, AMD_PTYPE_ALL,
253 0xA0E641E6, 0xFFFFFFFF },
255 { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
256 0x00000080, 0x00000080 }, /* [7] PSIVidEnable */
258 { 3, 0xA0, AMD_FAM10_ALL, AMD_PTYPE_ALL,
259 0x00001800, 0x000003800 }, /* [13:11] PllLockTime = 3 */
261 /* Reported Temp Control Register */
262 { 3, 0xA4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
263 0x00000080, 0x00000080 }, /* [7] TempSlewDnEn = 1 */
265 /* Clock Power/Timing Control 0 Register */
266 { 3, 0xD4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
267 0xC0000F00, 0xF0000F00 }, /* [31] NbClkDivApplyAll = 1,
268 [30:28] NbClkDiv = 100b,[11:8] ClkRampHystSel = 1111b */
270 /* Clock Power/Timing Control 1 Register */
271 { 3, 0xD8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
272 0x03000016, 0x0F000077 }, /* [6:4] VSRampTime = 1,
273 [2:0] VSSlamTime = 6, [27:24] ReConDel = 3 */
276 /* Clock Power/Timing Control 2 Register */
277 { 3, 0xDC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
278 0x00005000, 0x00007000 }, /* [14:12] NbsynPtrAdj = 5 */
281 /* Extended NB MCA Config Register */
282 { 3, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
283 0x007003E2, 0x007003E2 }, /* [22:20] = SyncFloodOn_Err = 7,
284 [9] SyncOnUncNbAryEn = 1 ,
285 [8] SyncOnProtEn = 1,
286 [7] SyncFloodOnTgtAbtErr = 1,
287 [6] SyncFloodOnDatErr = 1,
288 [5] DisPciCfgCpuMstAbtRsp = 1,
289 [1] SyncFloodOnUsPwDataErr = 1 */
291 /* errata 346 - Fam10 C2
292 * System software should set F3x188[22] to 1b. */
293 { 3, 0x188, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL,
294 0x00400000, 0x00400000 },
296 /* L3 Control Register */
297 { 3, 0x1B8, AMD_FAM10_ALL, AMD_PTYPE_ALL,
298 0x00001000, 0x00001000 }, /* [12] = L3PrivReplEn */
300 /* IBS Control Register */
301 { 3, 0x1CC, AMD_FAM10_ALL, AMD_PTYPE_ALL,
302 0x00000100, 0x00000100 }, /* [8] = LvtOffsetVal */
307 * Default HyperTransport Phy and errata settings.
309 static const struct {
310 u16 htreg; /* HT Phy Register index */
316 } fam10_htphy_default[] = {
318 /* Errata 344 - Fam10 C2/D0
319 * System software should set bit 6 of F4x1[9C, 94, 8C, 84]_x[78:70, 68:60]. */
320 { 0x60, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
321 0x00000040, 0x00000040 },
322 { 0x61, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
323 0x00000040, 0x00000040 },
324 { 0x62, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
325 0x00000040, 0x00000040 },
326 { 0x63, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
327 0x00000040, 0x00000040 },
328 { 0x64, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
329 0x00000040, 0x00000040 },
330 { 0x65, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
331 0x00000040, 0x00000040 },
332 { 0x66, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
333 0x00000040, 0x00000040 },
334 { 0x67, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
335 0x00000040, 0x00000040 },
336 { 0x68, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
337 0x00000040, 0x00000040 },
339 { 0x70, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
340 0x00000040, 0x00000040 },
341 { 0x71, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
342 0x00000040, 0x00000040 },
343 { 0x72, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
344 0x00000040, 0x00000040 },
345 { 0x73, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
346 0x00000040, 0x00000040 },
347 { 0x74, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
348 0x00000040, 0x00000040 },
349 { 0x75, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
350 0x00000040, 0x00000040 },
351 { 0x76, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
352 0x00000040, 0x00000040 },
353 { 0x77, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
354 0x00000040, 0x00000040 },
355 { 0x78, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
356 0x00000040, 0x00000040 },
358 /* Errata 354 - Fam10 C2
359 * System software should set bit 6 of F4x1[9C,94,8C,84]_x[58:50, 48:40] for all links. */
360 { 0x40, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
361 0x00000040, 0x00000040 },
362 { 0x41, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
363 0x00000040, 0x00000040 },
364 { 0x42, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
365 0x00000040, 0x00000040 },
366 { 0x43, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
367 0x00000040, 0x00000040 },
368 { 0x44, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
369 0x00000040, 0x00000040 },
370 { 0x45, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
371 0x00000040, 0x00000040 },
372 { 0x46, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
373 0x00000040, 0x00000040 },
374 { 0x47, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
375 0x00000040, 0x00000040 },
376 { 0x48, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
377 0x00000040, 0x00000040 },
379 { 0x50, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
380 0x00000040, 0x00000040 },
381 { 0x51, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
382 0x00000040, 0x00000040 },
383 { 0x52, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
384 0x00000040, 0x00000040 },
385 { 0x53, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
386 0x00000040, 0x00000040 },
387 { 0x54, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
388 0x00000040, 0x00000040 },
389 { 0x55, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
390 0x00000040, 0x00000040 },
391 { 0x56, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
392 0x00000040, 0x00000040 },
393 { 0x57, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
394 0x00000040, 0x00000040 },
395 { 0x58, AMD_RB_C2 | AMD_DA_C2, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
396 0x00000040, 0x00000040 },
398 /* Errata 327 - Fam10 C2/D0
399 * BIOS should set the Link Phy Impedance Register[RttCtl]
400 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][31:29]) to 010b and
401 * Link Phy Impedance Register[RttIndex]
402 * (F4x1[9C, 94, 8C, 84]_x[D0, C0][20:16]) to 00100b */
403 { 0xC0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
404 0x40040000, 0xe01F0000 },
405 { 0xD0, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
406 0x40040000, 0xe01F0000 },
408 { 0x520A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
409 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
411 { 0x530A, AMD_RB_C2 | AMD_DA_C2 | AMD_HY_D0, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
412 0x00004000, 0x00006000 }, /* HT_PHY_DLL_REG */
414 { 0x520A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
415 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
417 { 0x530A, AMD_DR_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
418 0x00004400, 0x00006400 }, /* HT_PHY_DLL_REG */
420 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
421 0x00000000, 0x000000FF }, /* Provide clear setting for logical
424 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
425 0x00000000, 0x000000FF }, /* Provide clear setting for logical
428 { 0xCF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
429 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
431 { 0xDF, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
432 0x0000006D, 0x000000FF }, /* HT_PHY_HT1_FIFO_PTR_OPT_VALUE */
434 /* Link Phy Receiver Loop Filter Registers */
435 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
436 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
437 [21:14] LfcMin = 10h */
439 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT3,
440 0x08040000, 0x3FFFC000 }, /* [29:22] LfcMax = 20h,
441 [21:14] LfcMin = 10h */
443 { 0xD1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
444 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
445 [21:14] LfcMin = 08h */
447 { 0xC1, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_HT1,
448 0x04020000, 0x3FFFC000 }, /* [29:22] LfcMax = 10h,
449 [21:14] LfcMin = 08h */
451 { 0xC0, AMD_FAM10_ALL, AMD_PTYPE_ALL, HTPHY_LINKTYPE_ALL,
452 0x40040000, 0xe01F0000 }, /* [31:29] RttCtl = 02h,
453 [20:16] RttIndex = 04h */