1 /* 2004.12 yhlu add dual core support */
5 #define SET_NB_CFG_54 1
8 #include "cpu/amd/dualcore/dualcore_id.c"
9 #include <pc80/mc146818rtc.h>
11 static inline unsigned get_core_num_in_bsp(unsigned nodeid)
14 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8);
20 #if SET_NB_CFG_54 == 1
21 static inline uint8_t set_apicid_cpuid_lo(void)
23 #if CONFIG_K8_REV_F_SUPPORT == 0
24 if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
27 // set the NB_CFG[54]=1; why the OS will be happy with that ???
29 msr = rdmsr(NB_CFG_MSR);
30 msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
31 wrmsr(NB_CFG_MSR, msr);
37 static inline void set_apicid_cpuid_lo(void) { }
41 static inline void real_start_other_core(unsigned nodeid)
44 // set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
45 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
46 dword |= 1<<27; // NbMcaToMstCpuEn bit
47 pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
48 // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
49 dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
51 pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
54 //it is running on core0 of node0
55 static inline void start_other_cores(void)
60 if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0)) {
61 return; // disable multi_core
66 for(nodeid=0; nodeid<nodes; nodeid++) {
67 if( get_core_num_in_bsp(nodeid) > 0) {
68 real_start_other_core(nodeid);