1 /* 2004.12 yhlu add dual core support */
3 #include <console/console.h>
5 #include <cpu/x86/lapic.h>
6 #include <cpu/amd/dualcore.h>
7 #include <device/device.h>
8 #include <device/pci.h>
9 #include <pc80/mc146818rtc.h>
10 #include <smp/spinlock.h>
11 #include <cpu/x86/mtrr.h>
12 #include "../model_fxx/model_fxx_msr.h"
13 #include "../../../northbridge/amd/amdk8/cpu_rev.c"
15 static int first_time = 1;
16 static int disable_siblings = !CONFIG_LOGICAL_CPUS;
19 int is_e0_later_in_bsp(int nodeid)
24 if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
25 return !is_cpu_pre_e0();
27 // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
29 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
31 val_old = pci_read_config32(dev, 0x80);
34 pci_write_config32(dev, 0x80, val);
35 val = pci_read_config32(dev, 0x80);
36 e0_later = !!(val & (1<<3));
37 if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
38 pci_write_config32(dev, 0x80, val_old); // restore it
44 unsigned int read_nb_cfg_54(void)
47 msr = rdmsr(NB_CFG_MSR);
48 return ( ( msr.hi >> (54-32)) & 1);
51 struct node_core_id get_node_core_id(unsigned int nb_cfg_54) {
52 struct node_core_id id;
53 // get the apicid via cpuid(1) ebx[27:24]
55 // when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
56 id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
57 id.nodeid = (id.coreid>>1);
59 } else { // single core should be here too
60 // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
61 id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
62 id.coreid = (id.nodeid>>3);
70 static int get_max_siblings(int nodes)
76 //get max siblings from all the nodes
77 for(nodeid=0; nodeid<nodes; nodeid++){
79 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
80 j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
89 static void enable_apic_ext_id(int nodes)
94 //enable APIC_EXIT_ID all the nodes
95 for(nodeid=0; nodeid<nodes; nodeid++){
97 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
98 val = pci_read_config32(dev, 0x68);
99 val |= (1<<17)|(1<<18);
100 pci_write_config32(dev, 0x68, val);
105 unsigned get_apicid_base(unsigned ioapic_num)
109 unsigned apicid_base;
112 int bsp_apic_id = lapicid(); // bsp apicid
114 int disable_siblings = !CONFIG_LOGICAL_CPUS;
117 get_option(&disable_siblings, "dual_core");
119 //get the nodes number
120 dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
121 nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
123 siblings = get_max_siblings(nodes);
125 if(bsp_apic_id > 0) { // io apic could start from 0
127 } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
128 if(!disable_siblings) { return siblings + 1; }
132 nb_cfg_54 = read_nb_cfg_54();
135 //it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
136 if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
137 //we need to check if e0 single core is there
139 for(i=0; i<nodes; i++) {
140 if(is_e0_later_in_bsp(i)) {
148 //contruct apicid_base
150 if((!disable_siblings) && (siblings>0) ) {
151 /* for 8 way dual core, we will used up apicid 16:16, actualy 16 is not allowed by current kernel
152 and the kernel will try to get one that is small than 16 to make io apic work.
153 I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
155 //4:10 for two way 8:12 for four way 16:16 for eight way
156 //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
157 apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
164 if((apicid_base+ioapic_num-1)>0xf) {
165 // We need to enable APIC EXT ID
166 printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
167 enable_apic_ext_id(nodes);
173 void amd_sibling_init(device_t cpu)
175 unsigned i, siblings;
176 struct cpuid_result result;
178 struct node_core_id id;
180 /* On the bootstrap processor see if I want sibling cpus enabled */
183 get_option(&disable_siblings, "dual_core");
185 result = cpuid(0x80000008);
186 /* See how many sibling cpus we have */
187 /* Is dualcore supported */
188 siblings = (result.ecx & 0xff);
194 printk_debug("CPU: %u %d siblings\n",
195 cpu->path.u.apic.apic_id,
199 nb_cfg_54 = read_nb_cfg_54();
201 id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
203 /* See if I am a sibling cpu */
204 //if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
205 //if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
207 if (disable_siblings) {
214 /* I am the primary cpu start up my siblings */
216 for(i = 1; i <= siblings; i++) {
217 struct device_path cpu_path;
219 /* Build the cpu device path */
220 cpu_path.type = DEVICE_PATH_APIC;
221 cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
223 /* See if I can find the cpu */
224 new = find_dev_path(cpu->bus, &cpu_path);
225 /* Allocate the new cpu device structure */
227 new = alloc_dev(cpu->bus, &cpu_path);
229 new->initialized = 0;
233 printk_debug("CPU: %u has sibling %u\n",
234 cpu->path.u.apic.apic_id,
235 new->path.u.apic.apic_id);
237 /* Start the new cpu */
238 if(new->enabled && !new->initialized)