2 * 2006.3 yhlu add copy data from CAR to ram
4 #include "cpu/amd/car/disable_cache_as_ram.c"
6 static inline void print_debug_pcar(const char *strval, uint32_t val)
8 printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
11 /* from linux kernel 2.6.32 asm/string_32.h */
13 static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
16 asm volatile("cld ; rep ; movsl\n\t"
22 : "=&c" (d0), "=&D" (d1), "=&S" (d2)
23 : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src)
26 /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
28 static void vErrata343(void)
32 unsigned int uiMask = 0xFFFFFFF7;
34 msr = rdmsr(BU_CFG2_MSR);
35 msr.hi &= uiMask; // set bit 35 to 0
36 wrmsr(BU_CFG2_MSR, msr);
40 static void post_cache_as_ram(void)
45 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
51 print_debug_pcar("v_esp=", v_esp);
55 unsigned testx = 0x5a5a5a5a;
56 print_debug_pcar("testx = ", testx);
58 /* copy data from cache as ram to
59 ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
61 #if CONFIG_RAMTOP <= 0x100000
62 #error "You need to set CONFIG_RAMTOP greater than 1M"
65 /* So we can access RAM from [1M, CONFIG_RAMTOP) */
66 set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
68 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
69 print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
71 /* from here don't store more data in CAR */
74 memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
75 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
78 /* set new esp */ /* before CONFIG_RAMBASE */
80 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
81 /* discard all registers (eax is used for %0), so gcc redo everything
82 after the stack is moved */
83 : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
86 /* We can put data to stack again */
88 /* only global variable sysinfo in cache need to be offset */
89 print_debug("Done\r\n");
90 print_debug_pcar("testx = ", testx);
92 print_debug("Disabling cache as ram now \r\n");
93 disable_cache_as_ram_bsp();
95 print_debug("Clearing initial memory region: ");
96 #if CONFIG_HAVE_ACPI_RESUME == 1
97 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
98 memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
100 memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
102 print_debug("Done\r\n");
104 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
106 set_sysinfo_in_ram(1); // So other core0 could start to train mem
108 #if CONFIG_MEM_TRAIN_SEQ == 1
109 // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
111 // wait for ap memory to trained
112 // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
114 /*copy and execute coreboot_ram */
116 /* We will not return */
118 print_debug("should not be here -\r\n");