2 * 2006.3 yhlu add copy data from CAR to ram
4 #include "cpu/amd/car/disable_cache_as_ram.c"
6 #include "cpu/amd/car/clear_init_ram.c"
8 static inline void print_debug_pcar(const char *strval, uint32_t val)
10 #if CONFIG_USE_PRINTK_IN_CAR
11 printk_debug("%s%08x\r\n", strval, val);
13 print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
17 static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
23 : "S" (src), "D" (dest), "c" ((bytes)>>2)
26 /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
28 static void vErrata343(void)
32 unsigned int uiMask = 0xFFFFFFF7;
34 msr = rdmsr(BU_CFG2_MSR);
35 msr.hi &= uiMask; // set bit 35 to 0
36 wrmsr(BU_CFG2_MSR, msr);
40 static void post_cache_as_ram(void)
45 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
51 print_debug_pcar("v_esp=", v_esp);
55 unsigned testx = 0x5a5a5a5a;
56 print_debug_pcar("testx = ", testx);
58 /* copy data from cache as ram to
59 ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
61 #if CONFIG_RAMTOP <= 0x100000
62 #error "You need to set CONFIG_RAMTOP greater than 1M"
65 set_init_ram_access(); /* So we can access RAM from [1M, CONFIG_RAMTOP) */
67 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
68 print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
70 /* from here don't store more data in CAR */
79 memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
80 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
83 /* set new esp */ /* before CONFIG_RAMBASE */
86 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
87 ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
95 /* We can put data to stack again */
97 /* only global variable sysinfo in cache need to be offset */
98 print_debug("Done\r\n");
99 print_debug_pcar("testx = ", testx);
101 print_debug("Disabling cache as ram now \r\n");
102 disable_cache_as_ram_bsp();
104 print_debug("Clearing initial memory region: ");
105 clear_init_ram(); //except the range from [(CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE, (CONFIG_RAMTOP))
106 print_debug("Done\r\n");
108 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
110 #ifndef CONFIG_MEM_TRAIN_SEQ
111 #define CONFIG_MEM_TRAIN_SEQ 0
113 set_sysinfo_in_ram(1); // So other core0 could start to train mem
115 #if CONFIG_MEM_TRAIN_SEQ == 1
116 // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
118 // wait for ap memory to trained
119 // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
121 /*copy and execute coreboot_ram */
123 /* We will not return */
125 print_debug("should not be here -\r\n");