2 * 2006.3 yhlu add copy data from CAR to ram
5 #include <arch/stages.h>
6 #include <cpu/x86/mtrr.h>
7 #include "cpu/amd/car/disable_cache_as_ram.c"
8 #include "cpu/x86/mtrr/earlymtrr.c"
10 static inline void print_debug_pcar(const char *strval, uint32_t val)
12 printk(BIOS_DEBUG, "%s%08x\n", strval, val);
15 /* from linux kernel 2.6.32 asm/string_32.h */
17 static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
20 asm volatile("cld ; rep ; movsl\n\t"
26 : "=&c" (d0), "=&D" (d1), "=&S" (d2)
27 : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src)
30 /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
32 static void vErrata343(void)
36 unsigned int uiMask = 0xFFFFFFF7;
38 msr = rdmsr(BU_CFG2_MSR);
39 msr.hi &= uiMask; // set bit 35 to 0
40 wrmsr(BU_CFG2_MSR, msr);
44 static void post_cache_as_ram(void)
49 /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
55 print_debug_pcar("v_esp=", v_esp);
59 unsigned testx = 0x5a5a5a5a;
60 print_debug_pcar("testx = ", testx);
62 /* copy data from cache as ram to
63 ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
65 #if CONFIG_RAMTOP <= 0x100000
66 #error "You need to set CONFIG_RAMTOP greater than 1M"
69 /* So we can access RAM from [1M, CONFIG_RAMTOP) */
70 set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
72 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00);
73 print_debug("Copying data from cache to RAM -- switching to use RAM as stack... ");
75 /* from here don't store more data in CAR */
78 memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
79 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
82 /* set new esp */ /* before CONFIG_RAMBASE */
84 ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
85 /* discard all registers (eax is used for %0), so gcc redo everything
86 after the stack is moved */
87 : "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
90 /* We can put data to stack again */
92 /* only global variable sysinfo in cache need to be offset */
93 print_debug("Done\n");
94 print_debug_pcar("testx = ", testx);
96 print_debug("Disabling cache as ram now \n");
97 disable_cache_as_ram_bsp();
99 print_debug("Clearing initial memory region: ");
100 #if CONFIG_HAVE_ACPI_RESUME == 1
101 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
102 memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
104 memset((void*)0, 0, ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_SIZE));
106 print_debug("Done\n");
108 // dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
110 set_sysinfo_in_ram(1); // So other core0 could start to train mem
112 #if CONFIG_MEM_TRAIN_SEQ == 1
113 // struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
115 // wait for ap memory to trained
116 // wait_all_core0_mem_trained(sysinfox); // moved to lapic_init_cpus.c
118 /*copy and execute coreboot_ram */
120 /* We will not return */
122 print_debug("should not be here -\n");