2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #define CacheSize DCACHE_RAM_SIZE
21 #define CacheBase (0xd0000 - CacheSize)
23 /* leave some space for global variable to pass to RAM stage */
24 #define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
27 #define CacheSizeAPStack 0x400 /* 1K */
30 #include <cpu/x86/mtrr.h>
31 #include <cpu/amd/mtrr.h>
33 /* Save the BIST result */
36 /*for normal part %ebx already contain cpu_init_detected from fallback call */
43 /* hope we can skip the double set for normal part */
44 #if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
46 /* check if cpu_init_detected */
47 movl $MTRRdefType_MSR, %ecx
50 movl %eax, %ebx /* We store the status */
53 /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
55 /* Only BSP needed, for other nodes set during HT/memory init. */
56 /* So we need to check if it is BSP */
62 /* Enable RT tables on BSP */
63 movl $0x8000c06c, %eax
71 /* Setup temporary DRAM map: [0,16M) bit 0-23 */
72 movl $0x8000c144, %eax
79 movl $0x8000c140, %eax
91 /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
92 Re-enable it in after RAM is initialized and before CAR is disabled */
93 movl $0xc001102a, %ecx
99 /* Set MtrrFixDramModEn for clear fixed mtrr */
100 enable_fixed_mtrr_dram_modify:
101 movl $SYSCFG_MSR, %ecx
103 andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
104 orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
107 /* Clear all MTRRs */
109 movl $fixed_mtrr_msr, %esi
111 clear_fixed_var_mtrr:
114 jz clear_fixed_var_mtrr_out
120 jmp clear_fixed_var_mtrr
121 clear_fixed_var_mtrr_out:
123 #if CacheSize == 0x10000
124 /* enable caching for 64K using fixed mtrr */
125 movl $0x268, %ecx /* fix4k_c0000*/
127 movl $0x1e1e1e1e, %edx /* WB MEM type */
129 movl $0x06060606, %edx /* WB IO type */
138 #if CacheSize == 0xc000
139 /* enable caching for 16K using fixed mtrr */
140 movl $0x268, %ecx /* fix4k_c4000*/
142 movl $0x1e1e1e1e, %edx /* WB MEM type */
144 movl $0x06060606, %edx /* WB IO type */
148 /* enable caching for 32K using fixed mtrr */
149 movl $0x269, %ecx /* fix4k_c8000*/
151 movl $0x1e1e1e1e, %edx /* WB MEM type */
153 movl $0x06060606, %edx /* WB IO type */
160 #if CacheSize == 0x8000
161 /* enable caching for 32K using fixed mtrr */
162 movl $0x269, %ecx /* fix4k_c8000*/
164 movl $0x1e1e1e1e, %edx /* WB MEM type */
166 movl $0x06060606, %edx /* WB IO type */
172 #if CacheSize < 0x8000
173 /* enable caching for 16K/8K/4K using fixed mtrr */
174 movl $0x269, %ecx /* fix4k_cc000*/
175 #if CacheSize == 0x4000
177 movl $0x1e1e1e1e, %edx /* WB MEM type */
179 movl $0x06060606, %edx /* WB IO type */
182 #if CacheSize == 0x2000
184 movl $0x1e1e0000, %edx /* WB MEM type */
186 movl $0x06060000, %edx /* WB IO type */
189 #if CacheSize == 0x1000
191 movl $0x1e000000, %edx /* WB MEM type */
193 movl $0x06000000, %edx /* WB IO type */
200 /* enable memory access for first MBs using top_mem */
203 movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
205 #endif /* USE_FAILOVER_IMAGE == 1*/
208 #if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0))
216 #if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
217 /* enable write base caching so we can do execute in place
222 movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
226 movl $((1 << (CPU_ADDR_BITS - 32)) - 1), %edx /* AMD 40 bit for K8, 48 bit for GH */
227 movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
229 #endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
231 #if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
232 /* Set the default memory type and enable fixed and variable MTRRs */
233 movl $MTRRdefType_MSR, %ecx
235 /* Enable Variable and Fixed MTRRs */
236 movl $0x00000c00, %eax
239 /* Enable the MTRRs and IORRs in SYSCFG */
240 movl $SYSCFG_MSR, %ecx
242 orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
251 andl $0x9fffffff, %eax
256 /* So we need to check if it is BSP */
266 #if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
267 /* Read the range with lodsl*/
269 movl $CacheBase, %esi
270 movl $(CacheSize >> 2), %ecx
272 /* Clear the range */
273 movl $CacheBase, %edi
274 movl $(CacheSize >> 2), %ecx
278 #endif /*USE_FAILOVER_IMAGE == 1*/
280 /* set up the stack pointer */
281 movl $(CacheBase + CacheSize - GlobalVarSize), %eax
291 /* need to set stack pointer for AP */
292 /* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
293 /* So need to get the NodeID and CoreID at first */
294 /* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
296 /* store our init detected */
299 /* get the coreid bits at first */
300 movl $0x80000008, %eax
306 /* get the initial apic id */
311 /* get the nb cfg bit 54 */
312 movl $0xc001001f, %ecx /* NB_CFG_MSR */
314 movl %edi, %ecx /* CoreID bits */
320 /* calculate stack pointer */
321 movl $CacheSizeAPStack, %eax
323 movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
326 /* retrive init detected */
338 /* Restore the BIST result */
341 /* We need to set ebp ? No need */
343 pushl %ebx /* init detected */
344 pushl %eax /* bist */
345 call cache_as_ram_main
346 /* We will not go back */
348 movb $0xAF, %al /* Should never see this postcode */
352 .long 0x250, 0x258, 0x259
353 .long 0x268, 0x269, 0x26A
354 .long 0x26B, 0x26C, 0x26D
357 .long 0x200, 0x201, 0x202, 0x203
358 .long 0x204, 0x205, 0x206, 0x207
359 .long 0x208, 0x209, 0x20A, 0x20B
360 .long 0x20C, 0x20D, 0x20E, 0x20F
362 .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
364 .long 0xC001001A, 0xC001001D
365 .long 0x000 /* NULL, end of table */
367 cache_as_ram_setup_out: