1 source src/cpu/amd/Kconfig
2 source src/cpu/intel/Kconfig
3 source src/cpu/via/Kconfig
4 source src/cpu/x86/Kconfig
10 config DCACHE_RAM_BASE
13 config DCACHE_RAM_SIZE
16 config DCACHE_RAM_GLOBAL_VAR_SIZE
20 config MAX_PHYSICAL_CPUS
26 default y if MAX_CPUS != 1
29 This option is used to enable certain functions to make coreboot
30 work correctly on symmetric multi processor (SMP) systems.
35 Select MMX in your socket or model Kconfig if your CPU has MMX
36 streaming SIMD instructions. ROMCC can build more efficient
37 code if it can spill to MMX registers.
42 Select SSE in your socket or model Kconfig if your CPU has SSE
43 streaming SIMD instructions. ROMCC can build more efficient
44 code if it can spill to SSE (aka XMM) registers.
50 Select SSE2 in your socket or model Kconfig if your CPU has SSE2
51 streaming SIMD instructions. Some parts of coreboot can be built
52 with more efficient code if SSE2 instructions are available.
58 Unset this if you don't want the MTRR code to use