4 * CONFIG_DCACHE_RAM_BASE
11 * Bootstrap code for the STPC Consumer
12 * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
16 * Written by Johan Rydberg, based on work by Daniel Kahlin.
17 * Rewritten by Eric Biederman
18 * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
19 * 2006.05 yhlu tailed it to use it for AP code in cache
22 * We use ELF as output format. So that we can
23 * debug the code in some form.
31 . = CONFIG_DCACHE_RAM_BASE;
33 * First we place the code and read only data (typically const declared).
34 * This get placed in rom.
52 * After the code we place initialized data (typically initialized
53 * global variables). This gets copied into ram by startup code.
54 * __data_start and __data_end shows where in ram this should be placed,
55 * whereas __data_loadstart and __data_loadend shows where in rom to
64 * bss does not contain data, it is just a space that should be zero
65 * initialized on startup. (typically uninitialized global variables)
66 * crt0.S fills between _bss and _ebss with zeroes.
88 * This is all address of the memory resident copy of coreboot.
93 _bogus = ASSERT( ( _eram_seg <= ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE))) , "coreboot_apc is too big");