1 #######################################################
3 # Main options file for LinuxBIOS
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
62 comment "Default architecture is i386, options are alpha and ppc"
67 comment "This cpu supports the MOVNTI directive"
70 ###############################################
72 ###############################################
77 comment "Cross compiler prefix"
80 default "$(CROSS_COMPILE)gcc"
82 comment "Target C Compiler"
87 comment "Host C Compiler"
92 comment "Additional per-cpu CFLAGS"
95 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
97 comment "Objcopy command"
99 define LINUXBIOS_VERSION
103 comment "LinuxBIOS version"
105 define LINUXBIOS_EXTRA_VERSION
109 comment "LinuxBIOS extra version"
111 define LINUXBIOS_BUILD
112 default "$(shell date)"
117 define LINUXBIOS_COMPILE_TIME
118 default "$(shell date +%T)"
123 define LINUXBIOS_COMPILE_BY
124 default "$(shell whoami)"
127 comment "Who build this image"
129 define LINUXBIOS_COMPILE_HOST
130 default "$(shell hostname)"
136 define LINUXBIOS_COMPILE_DOMAIN
137 default "$(shell dnsdomainname)"
140 comment "Build domain name"
142 define LINUXBIOS_COMPILER
143 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
146 comment "Build compiler"
148 define LINUXBIOS_LINKER
149 default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
152 comment "Build linker"
154 define LINUXBIOS_ASSEMBLER
155 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
158 comment "Build assembler"
160 define CONFIG_CHIP_CONFIGURE
163 comment "Use new chip_configure method for configuring (non-pci) devices"
165 define CONFIG_USE_INIT
168 comment "Use stage 1 initialization code"
171 ###############################################
173 ###############################################
175 define HAVE_FALLBACK_BOOT
179 comment "Set if fallback booting required"
181 define USE_FALLBACK_IMAGE
185 comment "Set to build a fallback image"
191 comment "Default fallback image size"
197 comment "Size of your ROM"
199 define ROM_IMAGE_SIZE
203 comment "Default image size"
205 define ROM_SECTION_SIZE
206 default {FALLBACK_SIZE}
209 comment "Default rom section size"
211 define ROM_SECTION_OFFSET
212 default {ROM_SIZE - FALLBACK_SIZE}
215 comment "Default rom section offset"
218 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
221 comment "Default payload size"
224 default {PAYLOAD_SIZE}
227 comment "Base address of LinuxBIOS in ROM"
233 comment "Start address of LinuxBIOS in ROM"
239 comment "Hardware reset vector address"
241 define _EXCEPTION_VECTORS
242 default {_ROMBASE+0x100}
245 comment "Address of exception vector table"
251 comment "Default stack size"
257 comment "Default heap size"
263 comment "Base address of LinuxBIOS in RAM"
269 comment "Start address of LinuxBIOS in RAM"
271 define USE_DCACHE_RAM
274 comment "Use data cache as temporary RAM if possible"
276 define DCACHE_RAM_BASE
280 comment "Base address of data cache when using it for temporary RAM"
282 define DCACHE_RAM_SIZE
286 comment "Size of data cache when using it for temporary RAM"
288 define DCACHE_RAM_GLOBAL_VAR_SIZE
292 comment "Size of region that for global variable of cache as ram stage"
298 comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
304 comment "Size of area to cache during LinuxBIOS execution directly from ROM"
306 define CONFIG_COMPRESS
309 comment "Set for compressed image"
311 define CONFIG_UNCOMPRESSED
313 default {!CONFIG_COMPRESS}
315 comment "Set for uncompressed image"
317 define CONFIG_LB_MEM_TOPK
321 comment "Kilobytes of memory to initialized before executing code from RAM"
323 define HAVE_OPTION_TABLE
326 comment "Export CMOS option table"
328 define USE_OPTION_TABLE
330 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
332 comment "Use option table"
335 ###############################################
336 # CMOS variable options
337 ###############################################
338 define LB_CKS_RANGE_START
342 comment "First CMOS byte to use for LinuxBIOS options"
344 define LB_CKS_RANGE_END
348 comment "Last CMOS byte to use for LinuxBIOS options"
354 comment "Pair of bytes to use for CMOS checksum"
358 ###############################################
360 ###############################################
363 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
365 comment "Main initialization target"
368 ###############################################
369 # Debugging/Logging options
370 ###############################################
375 comment "Enable debugging code"
377 define CONFIG_CONSOLE_VGA
380 comment "Log messages to VGA"
382 define CONFIG_CONSOLE_VGA_MULTI
385 comment "Multi VGA console"
387 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
390 comment "Use onboard VGA instead of add on VGA card"
392 define CONFIG_CONSOLE_BTEXT
395 comment "Log messages to btext fb console"
397 define CONFIG_CONSOLE_LOGBUF
400 comment "Log messages to buffer"
402 define CONFIG_CONSOLE_SROM
405 comment "Log messages to SROM console"
407 define CONFIG_CONSOLE_SERIAL8250
410 comment "Log messages to 8250 uart based serial console"
412 define DEFAULT_CONSOLE_LOGLEVEL
415 comment "Console will log at this level unless changed"
417 define MAXIMUM_CONSOLE_LOGLEVEL
420 comment "Error messages up to this level can be printed"
422 define CONFIG_SERIAL_POST
425 comment "Enable SERIAL POST codes"
430 comment "Disable POST codes"
436 comment "Base address for 8250 uart for the serial console"
441 comment "Default baud rate for serial console"
447 comment "Allow UART divisor to be set explicitly"
453 comment "Default flow control settings for the 8250 serial console uart"
456 ###############################################
458 ###############################################
461 default "Mainboard_not_set"
463 comment "Mainboard name"
465 define MAINBOARD_PART_NUMBER
466 default "Part_number_not_set"
469 comment "Part number of mainboard"
471 define MAINBOARD_VENDOR
472 default "Vendor_not_set"
475 comment "Vendor of mainboard"
477 define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
480 comment "PCI Vendor ID of mainboard manufacturer"
482 define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
486 comment "PCI susbsystem device id assigned my mainboard manufacturer"
488 define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
491 comment "Default power on after power fail setting"
493 define CONFIG_SYS_CLK_FREQ
496 comment "System clock frequency in MHz"
498 define CONFIG_MAX_PCI_BUSES
501 comment "Maximum number of PCI buses to search for devices"
503 ###############################################
505 ###############################################
510 comment "Define if we support SMP"
512 define CONFIG_MAX_CPUS
515 comment "Maximum CPU count for this machine"
517 define CONFIG_MAX_PHYSICAL_CPUS
520 comment "Maximum physical CPU count for this machine"
522 define CONFIG_LOGICAL_CPUS
525 comment "Should multiple cpus per die be enabled?"
530 comment "Define to build an MP table"
532 define SERIAL_CPU_INIT
535 comment "Serialize CPU init"
537 define APIC_ID_OFFSET
540 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
542 define ENABLE_APIC_EXT_ID
545 comment "Enable APIC ext id mode 8 bit"
547 define LIFT_BSP_APIC_ID
550 comment "decide if we lift bsp apic id while ap apic id"
552 ###############################################
554 ###############################################
556 define CONFIG_IDE_STREAM
559 comment "Boot from IDE device"
561 define CONFIG_ROM_STREAM
564 comment "Boot image is located in ROM"
566 define CONFIG_ROM_STREAM_START
567 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
570 comment "ROM stream start location"
572 define CONFIG_COMPRESSED_ROM_STREAM
575 comment "compressed boot image is located in ROM and is assumed to be NRV2B (deprecated)"
577 define CONFIG_COMPRESSED_ROM_STREAM_NRV2B
580 comment "NRV2B compressed boot image is located in ROM"
582 define CONFIG_COMPRESSED_ROM_STREAM_LZMA
585 comment "LZMA compressed boot image is located in ROM"
587 define CONFIG_PRECOMPRESSED_ROM_STREAM
590 comment "boot image is already compressed"
592 define CONFIG_FS_STREAM
595 comment "Boot from a filesystem"
597 define CONFIG_FS_EXT2
600 comment "Enable ext2 filesystem support"
602 define CONFIG_FS_ISO9660
605 comment "Enable ISO9660 filesystem support"
610 comment "Enable FAT filesystem support"
612 define AUTOBOOT_DELAY
615 comment "Delay (in seconds) before autobooting"
617 define AUTOBOOT_CMDLINE
618 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
621 comment "Default command line when autobooting"
624 define USE_WATCHDOG_ON_BOOT
627 comment "Use the watchdog on booting"
630 ###############################################
631 # Plugin Device support options
632 ###############################################
634 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
637 comment "Enable support for plugin Hypertransport busses"
639 define CONFIG_AGP_PLUGIN_SUPPORT
642 comment "Enable support for plugin AGP busses"
644 define CONFIG_CARDBUS_PLUGIN_SUPPORT
647 comment "Enable support cardbus plugin cards"
649 define CONFIG_PCIX_PLUGIN_SUPPORT
652 comment "Enable support for plugin PCI-X busses"
654 define CONFIG_PCIEXP_PLUGIN_SUPPORT
657 comment "Enable support for plugin PCI-E busses"
660 ###############################################
662 ###############################################
664 define HAVE_PIRQ_TABLE
667 comment "Define if we have a PIRQ table"
669 define IRQ_SLOT_COUNT
672 comment "Number of IRQ slots"
674 define CONFIG_PCIBIOS_IRQ
677 comment "PCIBIOS IRQ support"
682 comment "IOAPIC support"
685 ###############################################
686 # IDE specific options
687 ###############################################
692 comment "Define to include IDE support"
694 define IDE_BOOT_DRIVE
697 comment "Disk number of boot drive"
702 comment "Swap bytes when reading from IDE device"
707 comment "Sector at which to start searching for boot image"
710 ###############################################
711 # Options for memory mapped I/O
712 ###############################################
718 comment "Address of PCI Configuration Address Register"
724 comment "Address of PCI Configuration Data Register"
730 comment "Base address of PCI/ISA I/O address range"
736 comment "Base address of PCI/ISA memory address range"
742 comment "PNP Configuration Address Register offset"
748 comment "PNP Configuration Data Register offset"
754 comment "Base address of memory mapped I/O operations"
757 ###############################################
758 # Options for embedded systems
759 ###############################################
761 define EMBEDDED_RAM_SIZE
764 comment "Embedded boards generally have fixed RAM size"
767 ###############################################
769 ###############################################
771 define CONFIG_CHIP_NAME
774 comment "Compile in the chip name"
777 define CONFIG_GDB_STUB
780 comment "Compile in gdb stub support?"
783 define HAVE_INIT_TIMER
786 comment "Have a init_timer function"
788 define HAVE_HARD_RESET
791 comment "Have hard reset"
796 comment "Set to deal with memory hole"
798 define MAX_REBOOT_CNT
801 comment "Set maximum reboots"
804 ###############################################
805 # Misc device options
806 ###############################################
808 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
811 comment "Use timer2 to callibrate the x86 time stamp counter"
813 define INTEL_PPRO_MTRR
818 define CONFIG_UDELAY_TSC
821 comment "Implement udelay with the x86 time stamp counter"
823 define CONFIG_UDELAY_IO
826 comment "Implement udelay with x86 io registers"
831 comment "Use this to fake spd rom values"
834 define HAVE_ACPI_TABLES
837 comment "Define to build ACPI tables"
840 define ACPI_SSDTX_NUM
843 comment "extra ssdt num for PCI Device"
846 define AGP_APERTURE_SIZE
850 comment "AGP graphics virtual memory aperture size"
853 define HT_CHAIN_UNITID_BASE
856 comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
859 define HT_CHAIN_END_UNITID_BASE
862 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
865 define SB_HT_CHAIN_UNITID_OFFSET_ONLY
868 comment "this will decided if only offset SB hypertransport chain"
871 define K8_SB_HT_CHAIN_ON_BUS0
874 comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
877 define K8_HW_MEM_HOLE_SIZEK
880 comment "Opteron E0 later memory hole size in K, 0 mean disable"
883 define K8_HW_MEM_HOLE_SIZE_AUTO_INC
886 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
889 define K8_HT_FREQ_1G_SUPPORT
892 comment "Optern E0 later could support 1G HT, but still depends MB design"
895 define CONFIG_PCI_ROM_RUN
898 comment "Init PCI device option rom"
901 define CONFIG_PCI_64BIT_PREF_MEM
904 comment "allow PCI device get 4G above Region as pref mem"
908 ###############################################
909 # Board specific options
910 ###############################################
912 ###############################################
913 # Options for motorola/sandpoint
914 ###############################################
915 define CONFIG_SANDPOINT_ALTIMUS
918 comment "Configure Sandpoint with Altimus PMC"
920 define CONFIG_SANDPOINT_TALUS
923 comment "Configure Sandpoint with Talus PMC"
925 define CONFIG_SANDPOINT_UNITY
928 comment "Configure Sandpoint with Unity PMC"
930 define CONFIG_SANDPOINT_VALIS
933 comment "Configure Sandpoint with Valis PMC"
935 define CONFIG_SANDPOINT_GYRUS
938 comment "Configure Sandpoint with Gyrus PMC"
941 ###############################################
942 # Options for totalimpact/briq
943 ###############################################
944 define CONFIG_BRIQ_750FX
947 comment "Configure briQ with PowerPC 750FX"
949 define CONFIG_BRIQ_7400
952 comment "Configure briQ with PowerPC G4"