1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
62 comment "Default architecture is i386, options are alpha and ppc"
67 comment "This cpu supports the MOVNTI directive"
70 ###############################################
72 ###############################################
77 comment "Cross compiler prefix"
80 default "$(CROSS_COMPILE)gcc"
82 comment "Target C Compiler"
87 comment "Host C Compiler"
92 comment "Additional per-cpu CFLAGS"
95 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
97 comment "Objcopy command"
99 define COREBOOT_VERSION
103 comment "coreboot version"
105 define COREBOOT_EXTRA_VERSION
109 comment "coreboot extra version"
111 define COREBOOT_BUILD
112 default "$(shell date)"
117 define COREBOOT_COMPILE_TIME
118 default "$(shell date +%T)"
123 define COREBOOT_COMPILE_BY
124 default "$(shell whoami)"
127 comment "Who build this image"
129 define COREBOOT_COMPILE_HOST
130 default "$(shell hostname)"
136 define COREBOOT_COMPILE_DOMAIN
137 default "$(shell dnsdomainname)"
140 comment "Build domain name"
142 define COREBOOT_COMPILER
143 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
146 comment "Build compiler"
148 define COREBOOT_LINKER
149 default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
152 comment "Build linker"
154 define COREBOOT_ASSEMBLER
155 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
158 comment "Build assembler"
160 define CONFIG_CHIP_CONFIGURE
163 comment "Use new chip_configure method for configuring (non-pci) devices"
165 define CONFIG_USE_INIT
168 comment "Use stage 1 initialization code"
171 ###############################################
173 ###############################################
175 define HAVE_FALLBACK_BOOT
179 comment "Set if fallback booting required"
181 define HAVE_FAILOVER_BOOT
185 comment "Set if failover booting required"
187 define USE_FALLBACK_IMAGE
191 comment "Set to build a fallback image"
193 define USE_FAILOVER_IMAGE
197 comment "Set to build a failover image"
203 comment "Default fallback image size"
209 comment "Default failover image size"
215 comment "Size of your ROM"
217 define ROM_IMAGE_SIZE
221 comment "Default image size"
223 define ROM_SECTION_SIZE
224 default {FALLBACK_SIZE}
227 comment "Default rom section size"
229 define ROM_SECTION_OFFSET
230 default {ROM_SIZE - FALLBACK_SIZE}
233 comment "Default rom section offset"
236 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
239 comment "Default payload size"
242 default {PAYLOAD_SIZE}
245 comment "Base address of coreboot in ROM"
251 comment "Start address of coreboot in ROM"
257 comment "Hardware reset vector address"
259 define _EXCEPTION_VECTORS
260 default {_ROMBASE+0x100}
263 comment "Address of exception vector table"
269 comment "Default stack size"
275 comment "Default heap size"
281 comment "Base address of coreboot in RAM"
287 comment "Start address of coreboot in RAM"
289 define USE_DCACHE_RAM
292 comment "Use data cache as temporary RAM if possible"
297 comment "AMD family 10 CAR requires additional setup"
299 define DCACHE_RAM_BASE
303 comment "Base address of data cache when using it for temporary RAM"
305 define DCACHE_RAM_SIZE
309 comment "Size of data cache when using it for temporary RAM"
311 define DCACHE_RAM_GLOBAL_VAR_SIZE
315 comment "Size of region that for global variable of cache as ram stage"
317 define CONFIG_AP_CODE_IN_CAR
320 comment "will copy coreboot_apc to AP cache ane execute in AP"
325 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
327 define WAIT_BEFORE_CPUS_INIT
330 comment "execute cpus_ready_for_init if it is set to 1"
336 comment "Start address of area to cache during coreboot execution directly from ROM"
342 comment "Size of area to cache during coreboot execution directly from ROM"
344 define CONFIG_COMPRESS
347 comment "Set for compressed image"
349 define CONFIG_UNCOMPRESSED
351 default {!CONFIG_COMPRESS}
353 comment "Set for uncompressed image"
355 define CONFIG_LB_MEM_TOPK
359 comment "Kilobytes of memory to initialized before executing code from RAM"
361 define HAVE_OPTION_TABLE
364 comment "Export CMOS option table"
366 define USE_OPTION_TABLE
368 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
370 comment "Use option table"
373 ###############################################
374 # CMOS variable options
375 ###############################################
376 define LB_CKS_RANGE_START
380 comment "First CMOS byte to use for coreboot options"
382 define LB_CKS_RANGE_END
386 comment "Last CMOS byte to use for coreboot options"
392 comment "Pair of bytes to use for CMOS checksum"
396 ###############################################
398 ###############################################
401 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
403 comment "Main initialization target"
406 ###############################################
407 # Debugging/Logging options
408 ###############################################
413 comment "Enable debugging code"
415 define CONFIG_CONSOLE_VGA
418 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
420 define CONFIG_CONSOLE_VGA_MULTI
423 comment "Multi VGA console"
425 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
428 comment "Use onboard VGA instead of add on VGA card"
430 define CONFIG_CONSOLE_BTEXT
433 comment "Log messages to btext fb console"
435 define CONFIG_CONSOLE_LOGBUF
438 comment "Log messages to buffer"
440 define CONFIG_CONSOLE_SROM
443 comment "Log messages to SROM console"
445 define CONFIG_CONSOLE_SERIAL8250
448 comment "Log messages to 8250 uart based serial console"
450 define CONFIG_USBDEBUG_DIRECT
453 comment "Log messages to ehci debug port console"
455 define DEFAULT_CONSOLE_LOGLEVEL
458 comment "Console will log at this level unless changed"
460 define MAXIMUM_CONSOLE_LOGLEVEL
463 comment "Error messages up to this level can be printed"
465 define CONFIG_SERIAL_POST
468 comment "Enable SERIAL POST codes"
473 comment "Disable POST codes"
479 comment "Base address for 8250 uart for the serial console"
484 comment "Default baud rate for serial console"
490 comment "Allow UART divisor to be set explicitly"
496 comment "Default flow control settings for the 8250 serial console uart"
499 define CONFIG_USE_PRINTK_IN_CAR
502 comment "use printk instead of print in CAR stage code"
504 define ASSEMBLER_DEBUG
507 comment "Create disassembly files for debugging"
510 ###############################################
512 ###############################################
515 default "Mainboard_not_set"
517 comment "Mainboard name"
519 define MAINBOARD_PART_NUMBER
520 default "Part_number_not_set"
523 comment "Part number of mainboard"
525 define MAINBOARD_VENDOR
526 default "Vendor_not_set"
529 comment "Vendor of mainboard"
531 define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
534 comment "PCI Vendor ID of mainboard manufacturer"
536 define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
540 comment "PCI susbsystem device id assigned my mainboard manufacturer"
542 define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
545 comment "Default power on after power fail setting"
547 define CONFIG_SYS_CLK_FREQ
550 comment "System clock frequency in MHz"
552 define CONFIG_MAX_PCI_BUSES
555 comment "Maximum number of PCI buses to search for devices"
557 ###############################################
559 ###############################################
564 comment "Define if we support SMP"
566 define CONFIG_MAX_CPUS
569 comment "Maximum CPU count for this machine"
571 define CONFIG_MAX_PHYSICAL_CPUS
574 comment "Maximum physical CPU count for this machine"
576 define CONFIG_LOGICAL_CPUS
579 comment "Should multiple cpus per die be enabled?"
581 define CONFIG_AP_IN_SIPI_WAIT
584 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
589 comment "Define to build an MP table"
591 define SERIAL_CPU_INIT
594 comment "Serialize CPU init"
596 define APIC_ID_OFFSET
599 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
601 define ENABLE_APIC_EXT_ID
604 comment "Enable APIC ext id mode 8 bit"
606 define LIFT_BSP_APIC_ID
609 comment "decide if we lift bsp apic id while ap apic id"
611 ###############################################
613 ###############################################
615 define CONFIG_MULTIBOOT
618 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
620 define CONFIG_IDE_PAYLOAD
623 comment "Boot from IDE device"
625 define CONFIG_ROM_PAYLOAD
628 comment "Boot image is located in ROM"
630 define CONFIG_ROM_PAYLOAD_START
631 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
634 comment "ROM stream start location"
636 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
639 comment "NRV2B compressed boot image is located in ROM"
641 define CONFIG_COMPRESSED_PAYLOAD_LZMA
644 comment "LZMA compressed boot image is located in ROM"
646 define CONFIG_PRECOMPRESSED_PAYLOAD
649 comment "boot image is already compressed"
651 define CONFIG_SERIAL_PAYLOAD
654 comment "Download boot image from serial port"
656 define CONFIG_FS_PAYLOAD
659 comment "Boot from a filesystem"
661 define CONFIG_FS_EXT2
664 comment "Enable ext2 filesystem support"
666 define CONFIG_FS_ISO9660
669 comment "Enable ISO9660 filesystem support"
674 comment "Enable FAT filesystem support"
676 define AUTOBOOT_DELAY
679 comment "Delay (in seconds) before autobooting"
681 define AUTOBOOT_CMDLINE
682 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
685 comment "Default command line when autobooting"
688 define USE_WATCHDOG_ON_BOOT
691 comment "Use the watchdog on booting"
694 ###############################################
695 # Plugin Device support options
696 ###############################################
698 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
701 comment "Enable support for plugin Hypertransport busses"
703 define CONFIG_AGP_PLUGIN_SUPPORT
706 comment "Enable support for plugin AGP busses"
708 define CONFIG_CARDBUS_PLUGIN_SUPPORT
711 comment "Enable support cardbus plugin cards"
713 define CONFIG_PCIX_PLUGIN_SUPPORT
716 comment "Enable support for plugin PCI-X busses"
718 define CONFIG_PCIEXP_PLUGIN_SUPPORT
721 comment "Enable support for plugin PCI-E busses"
724 ###############################################
726 ###############################################
728 define HAVE_PIRQ_TABLE
731 comment "Define if we have a PIRQ table"
736 comment "Define if we have a PIRQ table and want routing IRQs"
738 define IRQ_SLOT_COUNT
741 comment "Number of IRQ slots"
743 define CONFIG_PCIBIOS_IRQ
746 comment "PCIBIOS IRQ support"
751 comment "IOAPIC support"
754 ###############################################
755 # IDE specific options
756 ###############################################
761 comment "Define to include IDE support"
763 define IDE_BOOT_DRIVE
766 comment "Disk number of boot drive"
771 comment "Swap bytes when reading from IDE device"
776 comment "Sector at which to start searching for boot image"
779 ###############################################
780 # Options for memory mapped I/O
781 ###############################################
783 define PCI_IO_CFG_EXT
786 comment "allow 4K register space via io CFG port"
793 comment "Address of PCI Configuration Address Register"
799 comment "Address of PCI Configuration Data Register"
805 comment "Base address of PCI/ISA I/O address range"
811 comment "Base address of PCI/ISA memory address range"
817 comment "PNP Configuration Address Register offset"
823 comment "PNP Configuration Data Register offset"
829 comment "Base address of memory mapped I/O operations"
832 ###############################################
833 # Options for embedded systems
834 ###############################################
836 define EMBEDDED_RAM_SIZE
839 comment "Embedded boards generally have fixed RAM size"
842 ###############################################
844 ###############################################
846 define CONFIG_CHIP_NAME
849 comment "Compile in the chip name"
852 define CONFIG_GDB_STUB
855 comment "Compile in gdb stub support?"
858 define HAVE_INIT_TIMER
861 comment "Have a init_timer function"
863 define HAVE_HARD_RESET
866 comment "Have hard reset"
868 define HAVE_SMI_HANDLER
871 comment "Set, if the board needs an SMI handler"
876 comment "Set to deal with memory hole"
878 define MAX_REBOOT_CNT
881 comment "Set maximum reboots"
884 ###############################################
885 # Misc device options
886 ###############################################
891 comment "Include board specific FAN control initialization"
893 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
896 comment "Use timer2 to callibrate the x86 time stamp counter"
898 define INTEL_PPRO_MTRR
903 define CONFIG_UDELAY_TSC
906 comment "Implement udelay with the x86 time stamp counter"
908 define CONFIG_UDELAY_IO
911 comment "Implement udelay with x86 io registers"
916 comment "Use this to fake spd rom values"
919 define HAVE_ACPI_TABLES
922 comment "Define to build ACPI tables"
925 define ACPI_SSDTX_NUM
928 comment "extra ssdt num for PCI Device"
931 define AGP_APERTURE_SIZE
935 comment "AGP graphics virtual memory aperture size"
938 define HT_CHAIN_UNITID_BASE
941 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
944 define HT_CHAIN_END_UNITID_BASE
947 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
950 define SB_HT_CHAIN_UNITID_OFFSET_ONLY
953 comment "this will decided if only offset SB hypertransport chain"
956 define SB_HT_CHAIN_ON_BUS0
959 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
962 define PCI_BUS_SEGN_BITS
965 comment "It could be 0, 1, 2, 3 and 4 only"
968 define MMCONF_SUPPORT
971 comment "enable mmconfig for pci conf"
974 define MMCONF_SUPPORT_DEFAULT
977 comment "enable mmconfig for pci conf"
980 define HW_MEM_HOLE_SIZEK
983 comment "Opteron E0 later memory hole size in K, 0 mean disable"
986 define HW_MEM_HOLE_SIZE_AUTO_INC
989 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
992 define CONFIG_VAR_MTRR_HOLE
995 comment "using hole in MTRR instead of increasing method"
998 define K8_HT_FREQ_1G_SUPPORT
1001 comment "Optern E0 later could support 1G HT, but still depends MB design"
1004 define K8_REV_F_SUPPORT
1007 comment "Opteron Rev F (DDR2) support"
1013 comment "Opteron cpu bus num base"
1019 comment "Opteron cpu device num base"
1025 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1028 define EXT_RT_TBL_SUPPORT
1031 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1034 define EXT_CONF_SUPPORT
1037 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1044 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1047 define CPU_SOCKET_TYPE
1050 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1053 define CPU_ADDR_BITS
1056 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1059 define CONFIG_VGA_ROM_RUN
1062 comment "Init x86 ROMs on VGA-class PCI devices"
1065 define CONFIG_PCI_ROM_RUN
1068 comment "Init x86 ROMs on all PCI devices"
1071 define CONFIG_PCI_64BIT_PREF_MEM
1074 comment "allow PCI device get 4G above Region as pref mem"
1077 define CONFIG_AMDMCT
1080 comment "use AMD MCT to init RAM instead of native code"
1083 define AMD_UCODE_PATCH_FILE
1087 comment "name of the microcode patch file"
1090 define K8_MEM_BANK_B_ONLY
1093 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1096 define CONFIG_VIDEO_MB
1099 comment "Integrated graphics with UMA has dynamic setup"
1102 define CONFIG_GFXUMA
1108 define HAVE_MAINBOARD_RESOURCES
1111 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1114 define CONFIG_SPLASH_GRAPHIC
1117 comment "Paint a splash screen"
1120 define CONFIG_GX1_VIDEO
1123 comment "Build in GX1's graphic support"
1126 define CONFIG_GX1_VIDEOMODE
1129 comment "Define video mode after reset"
1138 define CONFIG_PCIE_CONFIGSPACE_HOLE
1141 comment "Leave a hole for PCIe config space in the device allocator"
1144 ###############################################
1145 # Board specific options
1146 ###############################################
1148 ###############################################
1149 # Options for motorola/sandpoint
1150 ###############################################
1151 define CONFIG_SANDPOINT_ALTIMUS
1154 comment "Configure Sandpoint with Altimus PMC"
1156 define CONFIG_SANDPOINT_TALUS
1159 comment "Configure Sandpoint with Talus PMC"
1161 define CONFIG_SANDPOINT_UNITY
1164 comment "Configure Sandpoint with Unity PMC"
1166 define CONFIG_SANDPOINT_VALIS
1169 comment "Configure Sandpoint with Valis PMC"
1171 define CONFIG_SANDPOINT_GYRUS
1174 comment "Configure Sandpoint with Gyrus PMC"
1177 ###############################################
1178 # Options for totalimpact/briq
1179 ###############################################
1180 define CONFIG_BRIQ_750FX
1183 comment "Configure briQ with PowerPC 750FX"
1185 define CONFIG_BRIQ_7400
1188 comment "Configure briQ with PowerPC G4"