1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
59 define CONFIG_ARCH_X86
62 comment "X86 is the default"
67 comment "Default architecture is i386, options are alpha and ppc"
69 define CONFIG_HAVE_MOVNTI
72 comment "This cpu supports the MOVNTI directive"
75 ###############################################
77 ###############################################
79 define CONFIG_CROSS_COMPILE
82 comment "Cross compiler prefix"
85 default "$(CONFIG_CROSS_COMPILE)gcc"
87 comment "Target C Compiler"
92 comment "Host C Compiler"
97 comment "Additional per-cpu CFLAGS"
100 default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
102 comment "Objcopy command"
105 # Try to determine svn revision first.
106 # If that fails, try last svn revision in git log.
107 define COREBOOT_VERSION
108 default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
111 comment "coreboot version"
113 define COREBOOT_EXTRA_VERSION
117 comment "coreboot extra version"
119 define COREBOOT_BUILD
120 default "$(shell date)"
125 define COREBOOT_COMPILE_TIME
126 default "$(shell date +%T)"
131 define COREBOOT_COMPILE_BY
132 default "$(shell whoami)"
135 comment "Who build this image"
137 define COREBOOT_COMPILE_HOST
138 default "$(shell hostname)"
144 define COREBOOT_COMPILE_DOMAIN
145 default "$(shell dnsdomainname)"
148 comment "Build domain name"
150 define COREBOOT_COMPILER
151 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)"
154 comment "Build compiler"
156 define COREBOOT_LINKER
157 default "$(shell $(CC) -Wl,--version 2>&1 | grep \" ld\")"
160 comment "Build linker"
162 define COREBOOT_ASSEMBLER
163 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
166 comment "Build assembler"
168 define CONFIG_CHIP_CONFIGURE
171 comment "Use new chip_configure method for configuring (non-pci) devices"
173 define CONFIG_USE_INIT
176 comment "Use stage 1 initialization code"
179 define CONFIG_COREBOOT_V2
182 comment "This is used by code to determine v2 vs v3"
185 ###############################################
187 ###############################################
189 define CONFIG_HAVE_FALLBACK_BOOT
193 comment "Set if fallback booting required"
195 define CONFIG_HAVE_FAILOVER_BOOT
199 comment "Set if failover booting required"
201 define CONFIG_USE_FALLBACK_IMAGE
205 comment "Set to build a fallback image"
207 define CONFIG_USE_FAILOVER_IMAGE
211 comment "Set to build a failover image"
213 define CONFIG_FALLBACK_SIZE
217 comment "Default fallback image size"
219 define CONFIG_FAILOVER_SIZE
223 comment "Default failover image size"
225 define CONFIG_ROM_SIZE
229 comment "Size of your ROM"
231 define CONFIG_ROM_IMAGE_SIZE
235 comment "Default image size"
237 define CONFIG_ROM_SECTION_SIZE
238 default {CONFIG_FALLBACK_SIZE}
241 comment "Default rom section size"
243 define CONFIG_ROM_SECTION_OFFSET
244 default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
247 comment "Default rom section offset"
249 define CONFIG_PAYLOAD_SIZE
250 default {CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE}
253 comment "Default payload size"
255 define CONFIG_ROMBASE
256 default {CONFIG_PAYLOAD_SIZE}
259 comment "Base address of coreboot in ROM"
261 define CONFIG_ROMSTART
265 comment "Start address of coreboot in ROM"
268 default {CONFIG_ROMBASE}
271 comment "Hardware reset vector address"
273 define CONFIG_EXCEPTION_VECTORS
274 default {CONFIG_ROMBASE+0x100}
277 comment "Address of exception vector table"
279 define CONFIG_STACK_SIZE
283 comment "Default stack size"
285 define CONFIG_HEAP_SIZE
289 comment "Default heap size"
291 define CONFIG_RAMBASE
295 comment "Base address of coreboot in RAM"
297 define CONFIG_RAMSTART
301 comment "Start address of coreboot in RAM"
303 define CONFIG_USE_DCACHE_RAM
306 comment "Use data cache as temporary RAM if possible"
308 define CONFIG_CAR_FAM10
311 comment "AMD family 10 CAR requires additional setup"
313 define CONFIG_DCACHE_RAM_BASE
317 comment "Base address of data cache when using it for temporary RAM"
319 define CONFIG_DCACHE_RAM_SIZE
323 comment "Size of data cache when using it for temporary RAM"
325 define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
329 comment "Size of region that for global variable of cache as ram stage"
331 define CONFIG_AP_CODE_IN_CAR
334 comment "will copy coreboot_apc to AP cache ane execute in AP"
336 define CONFIG_MEM_TRAIN_SEQ
339 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
341 define CONFIG_WAIT_BEFORE_CPUS_INIT
344 comment "execute cpus_ready_for_init if it is set to 1"
346 define CONFIG_XIP_ROM_BASE
350 comment "Start address of area to cache during coreboot execution directly from ROM"
352 define CONFIG_XIP_ROM_SIZE
356 comment "Size of area to cache during coreboot execution directly from ROM"
358 define CONFIG_COMPRESS
361 comment "Set for compressed image"
363 define CONFIG_UNCOMPRESSED
365 default {!CONFIG_COMPRESS}
367 comment "Set for uncompressed image"
369 define CONFIG_LB_MEM_TOPK
373 comment "Kilobytes of memory to initialized before executing code from RAM"
375 define CONFIG_HAVE_OPTION_TABLE
378 comment "Export CMOS option table"
380 define CONFIG_USE_OPTION_TABLE
382 default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
384 comment "Use option table"
387 ###############################################
388 # CMOS variable options
389 ###############################################
390 define CONFIG_LB_CKS_RANGE_START
394 comment "First CMOS byte to use for coreboot options"
396 define CONFIG_LB_CKS_RANGE_END
400 comment "Last CMOS byte to use for coreboot options"
402 define CONFIG_LB_CKS_LOC
406 comment "Pair of bytes to use for CMOS checksum"
410 ###############################################
412 ###############################################
415 default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
417 comment "Main initialization target"
420 ###############################################
421 # Debugging/Logging options
422 ###############################################
427 comment "Enable x86emu debugging code"
429 define CONFIG_VGA_BRIDGE_SETUP
432 comment "Set bridge bits to enable legacy VGA ranges"
434 define CONFIG_CONSOLE_VGA
437 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
439 define CONFIG_CONSOLE_VGA_MULTI
442 comment "Multi VGA console"
444 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
447 comment "Use onboard VGA instead of add on VGA card"
449 define CONFIG_CONSOLE_BTEXT
452 comment "Log messages to btext fb console"
454 define CONFIG_CONSOLE_LOGBUF
457 comment "Log messages to buffer"
459 define CONFIG_CONSOLE_SROM
462 comment "Log messages to SROM console"
464 define CONFIG_CONSOLE_SERIAL8250
467 comment "Log messages to 8250 uart based serial console"
469 define CONFIG_USBDEBUG_DIRECT
472 comment "Log messages to ehci debug port console"
474 define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
477 comment "Console will log at this level unless changed"
479 define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
482 comment "Error messages up to this level can be printed"
484 define CONFIG_SERIAL_POST
487 comment "Enable SERIAL POST codes"
489 define CONFIG_NO_POST
492 comment "Disable POST codes"
494 define CONFIG_TTYS0_BASE
498 comment "Base address for 8250 uart for the serial console"
500 define CONFIG_TTYS0_BAUD
503 comment "Default baud rate for serial console"
505 define CONFIG_TTYS0_DIV
509 comment "Allow UART divisor to be set explicitly"
511 define CONFIG_TTYS0_LCS
515 comment "Default flow control settings for the 8250 serial console uart"
518 define CONFIG_USE_PRINTK_IN_CAR
521 comment "use printk instead of print in CAR stage code"
523 define CONFIG_ASSEMBLER_DEBUG
526 comment "Create disassembly files for debugging"
529 ###############################################
531 ###############################################
533 define CONFIG_MAINBOARD
534 default "Mainboard_not_set"
536 comment "Mainboard name"
538 define CONFIG_MAINBOARD_PART_NUMBER
539 default "Part_number_not_set"
542 comment "Part number of mainboard"
544 define CONFIG_MAINBOARD_VENDOR
545 default "Vendor_not_set"
548 comment "Vendor of mainboard"
550 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
553 comment "PCI Vendor ID of mainboard manufacturer"
555 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
559 comment "PCI susbsystem device id assigned my mainboard manufacturer"
561 define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
564 comment "Default power on after power fail setting"
566 define CONFIG_SYS_CLK_FREQ
569 comment "System clock frequency in MHz"
571 define CONFIG_MAX_PCI_BUSES
574 comment "Maximum number of PCI buses to search for devices"
576 define CONFIG_EPIA_VT8237R_INIT
579 comment "Enable EPIA Specific Initialisation of VT8237R SB"
581 ###############################################
583 ###############################################
588 comment "Define if we support SMP"
590 define CONFIG_MAX_CPUS
593 comment "Maximum CPU count for this machine"
595 define CONFIG_MAX_PHYSICAL_CPUS
598 comment "Maximum physical CPU count for this machine"
600 define CONFIG_LOGICAL_CPUS
603 comment "Should multiple cpus per die be enabled?"
605 define CONFIG_AP_IN_SIPI_WAIT
608 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
610 define CONFIG_HAVE_MP_TABLE
613 comment "Define to build an MP table"
615 define CONFIG_SERIAL_CPU_INIT
618 comment "Serialize CPU init"
620 define CONFIG_APIC_ID_OFFSET
623 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
625 define CONFIG_ENABLE_APIC_EXT_ID
628 comment "Enable APIC ext id mode 8 bit"
630 define CONFIG_LIFT_BSP_APIC_ID
633 comment "decide if we lift bsp apic id while ap apic id"
635 ###############################################
637 ###############################################
639 define CONFIG_MULTIBOOT
642 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
644 define CONFIG_IDE_PAYLOAD
647 comment "Boot from IDE device"
649 define CONFIG_ROM_PAYLOAD
652 comment "Boot image is located in ROM"
654 define CONFIG_ROM_PAYLOAD_START
655 default {0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1}
658 comment "ROM stream start location"
660 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
663 comment "NRV2B compressed boot image is located in ROM"
665 define CONFIG_COMPRESSED_PAYLOAD_LZMA
668 comment "LZMA compressed boot image is located in ROM"
670 define CONFIG_PRECOMPRESSED_PAYLOAD
673 comment "boot image is already compressed"
675 define CONFIG_SERIAL_PAYLOAD
678 comment "Download boot image from serial port"
680 define CONFIG_FS_PAYLOAD
683 comment "Boot from a filesystem"
685 define CONFIG_FS_EXT2
688 comment "Enable ext2 filesystem support"
690 define CONFIG_FS_ISO9660
693 comment "Enable ISO9660 filesystem support"
698 comment "Enable FAT filesystem support"
703 comment "The new CBFS file system"
705 define CONFIG_AUTOBOOT_DELAY
708 comment "Delay (in seconds) before autobooting"
710 define CONFIG_AUTOBOOT_CMDLINE
711 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
714 comment "Default command line when autobooting"
717 define CONFIG_USE_WATCHDOG_ON_BOOT
720 comment "Use the watchdog on booting"
723 ###############################################
724 # Plugin Device support options
725 ###############################################
727 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
730 comment "Enable support for plugin Hypertransport busses"
732 define CONFIG_AGP_PLUGIN_SUPPORT
735 comment "Enable support for plugin AGP busses"
737 define CONFIG_CARDBUS_PLUGIN_SUPPORT
740 comment "Enable support cardbus plugin cards"
742 define CONFIG_PCIX_PLUGIN_SUPPORT
745 comment "Enable support for plugin PCI-X busses"
747 define CONFIG_PCIEXP_PLUGIN_SUPPORT
750 comment "Enable support for plugin PCI-E busses"
753 ###############################################
755 ###############################################
757 define CONFIG_HAVE_PIRQ_TABLE
760 comment "Define if we have a PIRQ table"
762 define CONFIG_PIRQ_ROUTE
765 comment "Define if we have a PIRQ table and want routing IRQs"
767 define CONFIG_IRQ_SLOT_COUNT
770 comment "Number of IRQ slots"
772 define CONFIG_PCIBIOS_IRQ
775 comment "PCIBIOS IRQ support"
780 comment "IOAPIC support"
783 ###############################################
784 # IDE specific options
785 ###############################################
790 comment "Define to include IDE support"
792 define CONFIG_IDE_BOOT_DRIVE
795 comment "Disk number of boot drive"
797 define CONFIG_IDE_SWAB
800 comment "Swap bytes when reading from IDE device"
802 define CONFIG_IDE_OFFSET
805 comment "Sector at which to start searching for boot image"
808 ###############################################
809 # Options for memory mapped I/O
810 ###############################################
812 define CONFIG_PCI_IO_CFG_EXT
815 comment "allow 4K register space via io CFG port"
818 define CONFIG_PCIC0_CFGADDR
822 comment "Address of PCI Configuration Address Register"
824 define CONFIG_PCIC0_CFGDATA
828 comment "Address of PCI Configuration Data Register"
830 define CONFIG_ISA_IO_BASE
834 comment "Base address of PCI/ISA I/O address range"
836 define CONFIG_ISA_MEM_BASE
840 comment "Base address of PCI/ISA memory address range"
842 define CONFIG_PNP_CFGADDR
846 comment "PNP Configuration Address Register offset"
848 define CONFIG_PNP_CFGDATA
852 comment "PNP Configuration Data Register offset"
854 define CONFIG_IO_BASE
858 comment "Base address of memory mapped I/O operations"
861 ###############################################
862 # Options for embedded systems
863 ###############################################
865 define CONFIG_EMBEDDED_RAM_SIZE
868 comment "Embedded boards generally have fixed RAM size"
871 ###############################################
873 ###############################################
875 define CONFIG_GDB_STUB
878 comment "Compile in gdb stub support?"
881 define CONFIG_HAVE_INIT_TIMER
884 comment "Have a init_timer function"
886 define CONFIG_HAVE_HARD_RESET
889 comment "Have hard reset"
891 define CONFIG_HAVE_SMI_HANDLER
894 comment "Set, if the board needs an SMI handler"
896 define CONFIG_MEMORY_HOLE
899 comment "Set to deal with memory hole"
901 define CONFIG_MAX_REBOOT_CNT
904 comment "Set maximum reboots"
907 ###############################################
908 # Misc device options
909 ###############################################
911 define CONFIG_HAVE_FANCTL
914 comment "Include board specific FAN control initialization"
916 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
919 comment "Use timer2 to callibrate the x86 time stamp counter"
921 define CONFIG_INTEL_PPRO_MTRR
926 define CONFIG_UDELAY_TSC
929 comment "Implement udelay with the x86 time stamp counter"
931 define CONFIG_UDELAY_IO
934 comment "Implement udelay with x86 io registers"
936 define CONFIG_UDELAY_LAPIC
939 comment "Implement udelay with the x86 Local APIC"
941 define CONFIG_FAKE_SPDROM
944 comment "Use this to fake spd rom values"
947 define CONFIG_HAVE_ACPI_TABLES
950 comment "Define to build ACPI tables"
953 define CONFIG_HAVE_ACPI_RESUME
956 comment "Define to build ACPI with resume support"
959 define CONFIG_ACPI_SSDTX_NUM
962 comment "extra ssdt num for PCI Device"
965 define CONFIG_AGP_APERTURE_SIZE
969 comment "AGP graphics virtual memory aperture size"
972 define CONFIG_HT_CHAIN_UNITID_BASE
975 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
978 define CONFIG_HT_CHAIN_END_UNITID_BASE
981 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
984 define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
987 comment "this will decided if only offset SB hypertransport chain"
990 define CONFIG_SB_HT_CHAIN_ON_BUS0
993 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
996 define CONFIG_PCI_BUS_SEGN_BITS
999 comment "It could be 0, 1, 2, 3 and 4 only"
1002 define CONFIG_MMCONF_SUPPORT
1005 comment "enable mmconfig for pci conf"
1008 define CONFIG_MMCONF_SUPPORT_DEFAULT
1011 comment "enable mmconfig for pci conf"
1014 define CONFIG_MMCONF_BASE_ADDRESS
1018 comment "enable mmconfig base address"
1021 define CONFIG_HW_MEM_HOLE_SIZEK
1024 comment "Opteron E0 later memory hole size in K, 0 mean disable"
1027 define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
1030 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
1033 define CONFIG_VAR_MTRR_HOLE
1036 comment "using hole in MTRR instead of increasing method"
1039 define CONFIG_K8_HT_FREQ_1G_SUPPORT
1042 comment "Optern E0 later could support 1G HT, but still depends MB design"
1045 define CONFIG_K8_REV_F_SUPPORT
1048 comment "Opteron Rev F (DDR2) support"
1054 comment "Opteron cpu bus num base"
1060 comment "Opteron cpu device num base"
1063 define CONFIG_HT3_SUPPORT
1066 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1069 define CONFIG_EXT_RT_TBL_SUPPORT
1072 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1075 define CONFIG_EXT_CONF_SUPPORT
1078 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1081 define CONFIG_DIMM_SUPPORT
1085 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1088 define CONFIG_CPU_SOCKET_TYPE
1091 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1094 define CONFIG_CPU_ADDR_BITS
1097 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1103 comment "Include VGA initialisation code"
1106 define CONFIG_VGA_ROM_RUN
1109 comment "Init x86 ROMs on VGA-class PCI devices"
1112 define CONFIG_PCI_ROM_RUN
1115 comment "Init x86 ROMs on all PCI devices"
1118 define CONFIG_PCI_OPTION_ROM_RUN_YABEL
1121 comment "Use Yabel instead of old bios emulator"
1124 define CONFIG_YABEL_DEBUG_FLAGS
1127 comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
1130 define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
1133 comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
1137 define CONFIG_PCI_OPTION_ROM_RUN_REALMODE
1140 comment "Use Yabel instead of old bios emulator"
1143 define CONFIG_PCI_64BIT_PREF_MEM
1146 comment "allow PCI device get 4G above Region as pref mem"
1149 define CONFIG_AMDMCT
1152 comment "use AMD MCT to init RAM instead of native code"
1155 define CONFIG_AMD_UCODE_PATCH_FILE
1159 comment "name of the microcode patch file"
1162 define CONFIG_K8_MEM_BANK_B_ONLY
1165 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1168 define CONFIG_VIDEO_MB
1171 comment "Integrated graphics with UMA has dynamic setup"
1174 define CONFIG_GFXUMA
1180 define CONFIG_HAVE_MAINBOARD_RESOURCES
1183 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1186 define CONFIG_HAVE_LOW_TABLES
1189 comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
1192 define CONFIG_HAVE_HIGH_TABLES
1195 comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
1198 define CONFIG_SPLASH_GRAPHIC
1201 comment "Paint a splash screen"
1204 define CONFIG_GX1_VIDEO
1207 comment "Build in GX1's graphic support"
1210 define CONFIG_GX1_VIDEOMODE
1213 comment "Define video mode after reset"
1222 define CONFIG_PCIE_CONFIGSPACE_HOLE
1225 comment "Leave a hole for PCIe config space in the device allocator"