1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
62 comment "Default architecture is i386, options are alpha and ppc"
67 comment "This cpu supports the MOVNTI directive"
70 ###############################################
72 ###############################################
77 comment "Cross compiler prefix"
80 default "$(CROSS_COMPILE)gcc"
82 comment "Target C Compiler"
87 comment "Host C Compiler"
92 comment "Additional per-cpu CFLAGS"
95 default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
97 comment "Objcopy command"
100 # Try to determine svn revision first.
101 # If that fails, try last svn revision in git log.
102 define COREBOOT_VERSION
103 default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
106 comment "coreboot version"
108 define COREBOOT_EXTRA_VERSION
112 comment "coreboot extra version"
114 define COREBOOT_BUILD
115 default "$(shell date)"
120 define COREBOOT_COMPILE_TIME
121 default "$(shell date +%T)"
126 define COREBOOT_COMPILE_BY
127 default "$(shell whoami)"
130 comment "Who build this image"
132 define COREBOOT_COMPILE_HOST
133 default "$(shell hostname)"
139 define COREBOOT_COMPILE_DOMAIN
140 default "$(shell dnsdomainname)"
143 comment "Build domain name"
145 define COREBOOT_COMPILER
146 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
149 comment "Build compiler"
151 define COREBOOT_LINKER
152 default "$(shell $(CC) -Wl,--version 2>&1 | grep \" ld\")"
155 comment "Build linker"
157 define COREBOOT_ASSEMBLER
158 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
161 comment "Build assembler"
163 define CONFIG_CHIP_CONFIGURE
166 comment "Use new chip_configure method for configuring (non-pci) devices"
168 define CONFIG_USE_INIT
171 comment "Use stage 1 initialization code"
177 comment "This is used by code to determine v2 vs v3"
180 ###############################################
182 ###############################################
184 define HAVE_FALLBACK_BOOT
188 comment "Set if fallback booting required"
190 define HAVE_FAILOVER_BOOT
194 comment "Set if failover booting required"
196 define USE_FALLBACK_IMAGE
200 comment "Set to build a fallback image"
202 define USE_FAILOVER_IMAGE
206 comment "Set to build a failover image"
212 comment "Default fallback image size"
218 comment "Default failover image size"
224 comment "Size of your ROM"
226 define ROM_IMAGE_SIZE
230 comment "Default image size"
232 define ROM_SECTION_SIZE
233 default {FALLBACK_SIZE}
236 comment "Default rom section size"
238 define ROM_SECTION_OFFSET
239 default {ROM_SIZE - FALLBACK_SIZE}
242 comment "Default rom section offset"
245 default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
248 comment "Default payload size"
251 default {PAYLOAD_SIZE}
254 comment "Base address of coreboot in ROM"
260 comment "Start address of coreboot in ROM"
266 comment "Hardware reset vector address"
268 define _EXCEPTION_VECTORS
269 default {_ROMBASE+0x100}
272 comment "Address of exception vector table"
278 comment "Default stack size"
284 comment "Default heap size"
290 comment "Base address of coreboot in RAM"
296 comment "Start address of coreboot in RAM"
298 define USE_DCACHE_RAM
301 comment "Use data cache as temporary RAM if possible"
306 comment "AMD family 10 CAR requires additional setup"
308 define DCACHE_RAM_BASE
312 comment "Base address of data cache when using it for temporary RAM"
314 define DCACHE_RAM_SIZE
318 comment "Size of data cache when using it for temporary RAM"
320 define DCACHE_RAM_GLOBAL_VAR_SIZE
324 comment "Size of region that for global variable of cache as ram stage"
326 define CONFIG_AP_CODE_IN_CAR
329 comment "will copy coreboot_apc to AP cache ane execute in AP"
334 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
336 define WAIT_BEFORE_CPUS_INIT
339 comment "execute cpus_ready_for_init if it is set to 1"
345 comment "Start address of area to cache during coreboot execution directly from ROM"
351 comment "Size of area to cache during coreboot execution directly from ROM"
353 define CONFIG_COMPRESS
356 comment "Set for compressed image"
358 define CONFIG_UNCOMPRESSED
360 default {!CONFIG_COMPRESS}
362 comment "Set for uncompressed image"
364 define CONFIG_LB_MEM_TOPK
368 comment "Kilobytes of memory to initialized before executing code from RAM"
370 define HAVE_OPTION_TABLE
373 comment "Export CMOS option table"
375 define USE_OPTION_TABLE
377 default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
379 comment "Use option table"
382 ###############################################
383 # CMOS variable options
384 ###############################################
385 define LB_CKS_RANGE_START
389 comment "First CMOS byte to use for coreboot options"
391 define LB_CKS_RANGE_END
395 comment "Last CMOS byte to use for coreboot options"
401 comment "Pair of bytes to use for CMOS checksum"
405 ###############################################
407 ###############################################
410 default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
412 comment "Main initialization target"
415 ###############################################
416 # Debugging/Logging options
417 ###############################################
422 comment "Enable x86emu debugging code"
424 define CONFIG_CONSOLE_VGA
427 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
429 define CONFIG_CONSOLE_VGA_MULTI
432 comment "Multi VGA console"
434 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
437 comment "Use onboard VGA instead of add on VGA card"
439 define CONFIG_CONSOLE_BTEXT
442 comment "Log messages to btext fb console"
444 define CONFIG_CONSOLE_LOGBUF
447 comment "Log messages to buffer"
449 define CONFIG_CONSOLE_SROM
452 comment "Log messages to SROM console"
454 define CONFIG_CONSOLE_SERIAL8250
457 comment "Log messages to 8250 uart based serial console"
459 define CONFIG_USBDEBUG_DIRECT
462 comment "Log messages to ehci debug port console"
464 define DEFAULT_CONSOLE_LOGLEVEL
467 comment "Console will log at this level unless changed"
469 define MAXIMUM_CONSOLE_LOGLEVEL
472 comment "Error messages up to this level can be printed"
474 define CONFIG_SERIAL_POST
477 comment "Enable SERIAL POST codes"
482 comment "Disable POST codes"
488 comment "Base address for 8250 uart for the serial console"
493 comment "Default baud rate for serial console"
499 comment "Allow UART divisor to be set explicitly"
505 comment "Default flow control settings for the 8250 serial console uart"
508 define CONFIG_USE_PRINTK_IN_CAR
511 comment "use printk instead of print in CAR stage code"
513 define ASSEMBLER_DEBUG
516 comment "Create disassembly files for debugging"
519 ###############################################
521 ###############################################
524 default "Mainboard_not_set"
526 comment "Mainboard name"
528 define MAINBOARD_PART_NUMBER
529 default "Part_number_not_set"
532 comment "Part number of mainboard"
534 define MAINBOARD_VENDOR
535 default "Vendor_not_set"
538 comment "Vendor of mainboard"
540 define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
543 comment "PCI Vendor ID of mainboard manufacturer"
545 define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
549 comment "PCI susbsystem device id assigned my mainboard manufacturer"
551 define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
554 comment "Default power on after power fail setting"
556 define CONFIG_SYS_CLK_FREQ
559 comment "System clock frequency in MHz"
561 define CONFIG_MAX_PCI_BUSES
564 comment "Maximum number of PCI buses to search for devices"
566 ###############################################
568 ###############################################
573 comment "Define if we support SMP"
575 define CONFIG_MAX_CPUS
578 comment "Maximum CPU count for this machine"
580 define CONFIG_MAX_PHYSICAL_CPUS
583 comment "Maximum physical CPU count for this machine"
585 define CONFIG_LOGICAL_CPUS
588 comment "Should multiple cpus per die be enabled?"
590 define CONFIG_AP_IN_SIPI_WAIT
593 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
598 comment "Define to build an MP table"
600 define SERIAL_CPU_INIT
603 comment "Serialize CPU init"
605 define APIC_ID_OFFSET
608 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
610 define ENABLE_APIC_EXT_ID
613 comment "Enable APIC ext id mode 8 bit"
615 define LIFT_BSP_APIC_ID
618 comment "decide if we lift bsp apic id while ap apic id"
620 ###############################################
622 ###############################################
624 define CONFIG_MULTIBOOT
627 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
629 define CONFIG_IDE_PAYLOAD
632 comment "Boot from IDE device"
634 define CONFIG_ROM_PAYLOAD
637 comment "Boot image is located in ROM"
639 define CONFIG_ROM_PAYLOAD_START
640 default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
643 comment "ROM stream start location"
645 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
648 comment "NRV2B compressed boot image is located in ROM"
650 define CONFIG_COMPRESSED_PAYLOAD_LZMA
653 comment "LZMA compressed boot image is located in ROM"
655 define CONFIG_PRECOMPRESSED_PAYLOAD
658 comment "boot image is already compressed"
660 define CONFIG_SERIAL_PAYLOAD
663 comment "Download boot image from serial port"
665 define CONFIG_FS_PAYLOAD
668 comment "Boot from a filesystem"
670 define CONFIG_FS_EXT2
673 comment "Enable ext2 filesystem support"
675 define CONFIG_FS_ISO9660
678 comment "Enable ISO9660 filesystem support"
683 comment "Enable FAT filesystem support"
688 comment "The new CBFS file system"
690 define AUTOBOOT_DELAY
693 comment "Delay (in seconds) before autobooting"
695 define AUTOBOOT_CMDLINE
696 default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
699 comment "Default command line when autobooting"
702 define USE_WATCHDOG_ON_BOOT
705 comment "Use the watchdog on booting"
708 ###############################################
709 # Plugin Device support options
710 ###############################################
712 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
715 comment "Enable support for plugin Hypertransport busses"
717 define CONFIG_AGP_PLUGIN_SUPPORT
720 comment "Enable support for plugin AGP busses"
722 define CONFIG_CARDBUS_PLUGIN_SUPPORT
725 comment "Enable support cardbus plugin cards"
727 define CONFIG_PCIX_PLUGIN_SUPPORT
730 comment "Enable support for plugin PCI-X busses"
732 define CONFIG_PCIEXP_PLUGIN_SUPPORT
735 comment "Enable support for plugin PCI-E busses"
738 ###############################################
740 ###############################################
742 define HAVE_PIRQ_TABLE
745 comment "Define if we have a PIRQ table"
750 comment "Define if we have a PIRQ table and want routing IRQs"
752 define IRQ_SLOT_COUNT
755 comment "Number of IRQ slots"
757 define CONFIG_PCIBIOS_IRQ
760 comment "PCIBIOS IRQ support"
765 comment "IOAPIC support"
768 ###############################################
769 # IDE specific options
770 ###############################################
775 comment "Define to include IDE support"
777 define IDE_BOOT_DRIVE
780 comment "Disk number of boot drive"
785 comment "Swap bytes when reading from IDE device"
790 comment "Sector at which to start searching for boot image"
793 ###############################################
794 # Options for memory mapped I/O
795 ###############################################
797 define PCI_IO_CFG_EXT
800 comment "allow 4K register space via io CFG port"
807 comment "Address of PCI Configuration Address Register"
813 comment "Address of PCI Configuration Data Register"
819 comment "Base address of PCI/ISA I/O address range"
825 comment "Base address of PCI/ISA memory address range"
831 comment "PNP Configuration Address Register offset"
837 comment "PNP Configuration Data Register offset"
843 comment "Base address of memory mapped I/O operations"
846 ###############################################
847 # Options for embedded systems
848 ###############################################
850 define EMBEDDED_RAM_SIZE
853 comment "Embedded boards generally have fixed RAM size"
856 ###############################################
858 ###############################################
860 define CONFIG_GDB_STUB
863 comment "Compile in gdb stub support?"
866 define HAVE_INIT_TIMER
869 comment "Have a init_timer function"
871 define HAVE_HARD_RESET
874 comment "Have hard reset"
876 define HAVE_SMI_HANDLER
879 comment "Set, if the board needs an SMI handler"
884 comment "Set to deal with memory hole"
886 define MAX_REBOOT_CNT
889 comment "Set maximum reboots"
892 ###############################################
893 # Misc device options
894 ###############################################
899 comment "Include board specific FAN control initialization"
901 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
904 comment "Use timer2 to callibrate the x86 time stamp counter"
906 define INTEL_PPRO_MTRR
911 define CONFIG_UDELAY_TSC
914 comment "Implement udelay with the x86 time stamp counter"
916 define CONFIG_UDELAY_IO
919 comment "Implement udelay with x86 io registers"
924 comment "Use this to fake spd rom values"
927 define HAVE_ACPI_TABLES
930 comment "Define to build ACPI tables"
933 define HAVE_ACPI_RESUME
936 comment "Define to build ACPI with resume support"
939 define ACPI_SSDTX_NUM
942 comment "extra ssdt num for PCI Device"
945 define AGP_APERTURE_SIZE
949 comment "AGP graphics virtual memory aperture size"
952 define HT_CHAIN_UNITID_BASE
955 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
958 define HT_CHAIN_END_UNITID_BASE
961 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
964 define SB_HT_CHAIN_UNITID_OFFSET_ONLY
967 comment "this will decided if only offset SB hypertransport chain"
970 define SB_HT_CHAIN_ON_BUS0
973 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
976 define PCI_BUS_SEGN_BITS
979 comment "It could be 0, 1, 2, 3 and 4 only"
982 define MMCONF_SUPPORT
985 comment "enable mmconfig for pci conf"
988 define MMCONF_SUPPORT_DEFAULT
991 comment "enable mmconfig for pci conf"
994 define MMCONF_BASE_ADDRESS
998 comment "enable mmconfig base address"
1001 define HW_MEM_HOLE_SIZEK
1004 comment "Opteron E0 later memory hole size in K, 0 mean disable"
1007 define HW_MEM_HOLE_SIZE_AUTO_INC
1010 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
1013 define CONFIG_VAR_MTRR_HOLE
1016 comment "using hole in MTRR instead of increasing method"
1019 define K8_HT_FREQ_1G_SUPPORT
1022 comment "Optern E0 later could support 1G HT, but still depends MB design"
1025 define K8_REV_F_SUPPORT
1028 comment "Opteron Rev F (DDR2) support"
1034 comment "Opteron cpu bus num base"
1040 comment "Opteron cpu device num base"
1046 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
1049 define EXT_RT_TBL_SUPPORT
1052 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
1055 define EXT_CONF_SUPPORT
1058 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
1065 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
1068 define CPU_SOCKET_TYPE
1071 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1074 define CPU_ADDR_BITS
1077 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1080 define CONFIG_VGA_ROM_RUN
1083 comment "Init x86 ROMs on VGA-class PCI devices"
1086 define CONFIG_PCI_ROM_RUN
1089 comment "Init x86 ROMs on all PCI devices"
1092 define CONFIG_PCI_OPTION_ROM_RUN_YABEL
1095 comment "Use Yabel instead of old bios emulator"
1098 define CONFIG_YABEL_DEBUG_FLAGS
1101 comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
1104 define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
1107 comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
1111 define CONFIG_PCI_OPTION_ROM_RUN_VM86
1114 comment "Use Yabel instead of old bios emulator"
1117 define CONFIG_PCI_64BIT_PREF_MEM
1120 comment "allow PCI device get 4G above Region as pref mem"
1123 define CONFIG_AMDMCT
1126 comment "use AMD MCT to init RAM instead of native code"
1129 define AMD_UCODE_PATCH_FILE
1133 comment "name of the microcode patch file"
1136 define K8_MEM_BANK_B_ONLY
1139 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1142 define CONFIG_VIDEO_MB
1145 comment "Integrated graphics with UMA has dynamic setup"
1148 define CONFIG_GFXUMA
1154 define HAVE_MAINBOARD_RESOURCES
1157 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1160 define HAVE_LOW_TABLES
1163 comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
1166 define HAVE_HIGH_TABLES
1169 comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
1172 define CONFIG_SPLASH_GRAPHIC
1175 comment "Paint a splash screen"
1178 define CONFIG_GX1_VIDEO
1181 comment "Build in GX1's graphic support"
1184 define CONFIG_GX1_VIDEOMODE
1187 comment "Define video mode after reset"
1196 define CONFIG_PCIE_CONFIGSPACE_HOLE
1199 comment "Leave a hole for PCIe config space in the device allocator"
1202 ###############################################
1203 # Board specific options
1204 ###############################################
1206 ###############################################
1207 # Options for motorola/sandpoint
1208 ###############################################
1209 define CONFIG_SANDPOINT_ALTIMUS
1212 comment "Configure Sandpoint with Altimus PMC"
1214 define CONFIG_SANDPOINT_TALUS
1217 comment "Configure Sandpoint with Talus PMC"
1219 define CONFIG_SANDPOINT_UNITY
1222 comment "Configure Sandpoint with Unity PMC"
1224 define CONFIG_SANDPOINT_VALIS
1227 comment "Configure Sandpoint with Valis PMC"
1229 define CONFIG_SANDPOINT_GYRUS
1232 comment "Configure Sandpoint with Gyrus PMC"
1235 ###############################################
1236 # Options for totalimpact/briq
1237 ###############################################
1238 define CONFIG_BRIQ_750FX
1241 comment "Configure briQ with PowerPC 750FX"
1243 define CONFIG_BRIQ_7400
1246 comment "Configure briQ with PowerPC G4"