1 #######################################################
3 # Main options file for coreboot
5 # Each option used by a part must be defined in
6 # this file. The format for options is:
9 # default <expr> | {<expr>} | "<string>" | none
11 # export always | used | never
17 # <name> is the name of the option
18 # <expr> is a numeric expression
19 # <string> is a string
21 # Either a default value or 'default none' must
22 # be specified for every option. An option
23 # specified as 'default none' will not be exported
24 # (i.e. will remain undefined) unless it has
25 # been assigned a value.
27 # Option values can be an immediate expression that
28 # evaluates to a numeric value, a delayed expression
29 # (surrounded by curley braces), or a string
30 # (surrounded by double quotes.)
32 # Immediate expressions are evaluated at the time an
33 # option is defined or set and the numeric result
34 # becomes the value of the option.
36 # Delayed expression are evaluated at the time the
37 # option is used, either in another expression or
38 # when being exported.
40 # String values will have the double quotes removed
43 # Format strings determine the print format that is
44 # used when exporting options. The default format
45 # is "%s" for strings and "%d" for numbers.
47 # Exported options generate entries in the
48 # Makefile.settings file. Options can be always
49 # exported, exported only if used, or never exported.
51 # A comment string must be supplied for every option.
53 #######################################################
55 ###############################################
56 # Architecture options
57 ###############################################
59 define CONFIG_ARCH_X86
62 comment "X86 is the default"
67 comment "Default architecture is i386, options are alpha and ppc"
69 define CONFIG_HAVE_MOVNTI
72 comment "This cpu supports the MOVNTI directive"
75 ###############################################
77 ###############################################
79 define CONFIG_CROSS_COMPILE
82 comment "Cross compiler prefix"
85 default "$(CONFIG_CROSS_COMPILE)gcc"
87 comment "Target C Compiler"
92 comment "Host C Compiler"
97 comment "Additional per-cpu CFLAGS"
100 default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
102 comment "Objcopy command"
105 # Try to determine svn revision first.
106 # If that fails, try last svn revision in git log.
107 define COREBOOT_VERSION
108 default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
111 comment "coreboot version"
113 define COREBOOT_EXTRA_VERSION
117 comment "coreboot extra version"
119 define COREBOOT_BUILD
120 default "$(shell date)"
125 define COREBOOT_COMPILE_TIME
126 default "$(shell date +%T)"
131 define COREBOOT_COMPILE_BY
132 default "$(shell whoami)"
135 comment "Who build this image"
137 define COREBOOT_COMPILE_HOST
138 default "$(shell hostname)"
144 define COREBOOT_COMPILE_DOMAIN
145 default "$(shell dnsdomainname)"
148 comment "Build domain name"
150 define COREBOOT_COMPILER
151 default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)"
154 comment "Build compiler"
156 define COREBOOT_LINKER
157 default "$(shell $(CC) -Wl,--version 2>&1 | grep \" ld\")"
160 comment "Build linker"
162 define COREBOOT_ASSEMBLER
163 default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
166 comment "Build assembler"
168 define CONFIG_CHIP_CONFIGURE
171 comment "Use new chip_configure method for configuring (non-pci) devices"
173 define CONFIG_USE_INIT
176 comment "Use stage 1 initialization code"
179 define CONFIG_COREBOOT_V2
182 comment "This is used by code to determine v2 vs v3"
185 ###############################################
187 ###############################################
189 define CONFIG_HAVE_FALLBACK_BOOT
193 comment "Set if fallback booting required"
195 define CONFIG_HAVE_FAILOVER_BOOT
199 comment "Set if failover booting required"
201 define CONFIG_USE_FALLBACK_IMAGE
205 comment "Set to build a fallback image"
207 define CONFIG_USE_FAILOVER_IMAGE
211 comment "Set to build a failover image"
213 define CONFIG_FALLBACK_SIZE
217 comment "Default fallback image size"
219 define CONFIG_FAILOVER_SIZE
223 comment "Default failover image size"
225 define CONFIG_ROM_SIZE
229 comment "Size of your ROM"
231 define CONFIG_ROM_IMAGE_SIZE
235 comment "Default image size"
237 define CONFIG_ROM_SECTION_SIZE
238 default {CONFIG_FALLBACK_SIZE}
241 comment "Default rom section size"
243 define CONFIG_ROM_SECTION_OFFSET
244 default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
247 comment "Default rom section offset"
249 define CONFIG_ROMBASE
250 default {0xffffffff - CONFIG_ROM_SIZE + 1}
253 comment "Base address of coreboot in ROM"
255 define CONFIG_ROMSTART
259 comment "Start address of coreboot in ROM"
262 default {CONFIG_ROMBASE}
265 comment "Hardware reset vector address"
267 define CONFIG_EXCEPTION_VECTORS
268 default {CONFIG_ROMBASE+0x100}
271 comment "Address of exception vector table"
273 define CONFIG_STACK_SIZE
277 comment "Default stack size"
279 define CONFIG_HEAP_SIZE
283 comment "Default heap size"
285 define CONFIG_RAMBASE
289 comment "Base address of coreboot in RAM"
291 define CONFIG_RAMSTART
295 comment "Start address of coreboot in RAM"
297 define CONFIG_USE_DCACHE_RAM
300 comment "Use data cache as temporary RAM if possible"
302 define CONFIG_DCACHE_RAM_BASE
306 comment "Base address of data cache when using it for temporary RAM"
308 define CONFIG_DCACHE_RAM_SIZE
312 comment "Size of data cache when using it for temporary RAM"
314 define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
318 comment "Size of region that for global variable of cache as ram stage"
320 define CONFIG_AP_CODE_IN_CAR
323 comment "will copy coreboot_apc to AP cache ane execute in AP"
325 define CONFIG_MEM_TRAIN_SEQ
328 comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
330 define CONFIG_WAIT_BEFORE_CPUS_INIT
333 comment "execute cpus_ready_for_init if it is set to 1"
335 define CONFIG_XIP_ROM_BASE
339 comment "Start address of area to cache during coreboot execution directly from ROM"
341 define CONFIG_XIP_ROM_SIZE
345 comment "Size of area to cache during coreboot execution directly from ROM"
347 define CONFIG_COMPRESS
350 comment "Set for compressed image"
352 define CONFIG_UNCOMPRESSED
354 default {!CONFIG_COMPRESS}
356 comment "Set for uncompressed image"
362 comment "Highest RAM that coreboot_ram will use"
364 define CONFIG_HAVE_OPTION_TABLE
367 comment "Export CMOS option table"
369 define CONFIG_USE_OPTION_TABLE
371 default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
373 comment "Use option table"
376 ###############################################
377 # CMOS variable options
378 ###############################################
379 define CONFIG_LB_CKS_RANGE_START
383 comment "First CMOS byte to use for coreboot options"
385 define CONFIG_LB_CKS_RANGE_END
389 comment "Last CMOS byte to use for coreboot options"
391 define CONFIG_LB_CKS_LOC
395 comment "Pair of bytes to use for CMOS checksum"
399 ###############################################
401 ###############################################
404 default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
406 comment "Main initialization target"
409 ###############################################
410 # Debugging/Logging options
411 ###############################################
416 comment "Enable x86emu debugging code"
418 define CONFIG_VGA_BRIDGE_SETUP
421 comment "Set bridge bits to enable legacy VGA ranges"
423 define CONFIG_CONSOLE_VGA
426 comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
428 define CONFIG_CONSOLE_VGA_MULTI
431 comment "Multi VGA console"
433 define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
436 comment "Use onboard VGA instead of add on VGA card"
438 define CONFIG_CONSOLE_BTEXT
441 comment "Log messages to btext fb console"
443 define CONFIG_CONSOLE_LOGBUF
446 comment "Log messages to buffer"
448 define CONFIG_CONSOLE_SROM
451 comment "Log messages to SROM console"
453 define CONFIG_CONSOLE_SERIAL8250
456 comment "Log messages to 8250 uart based serial console"
458 define CONFIG_USBDEBUG_DIRECT
461 comment "Log messages to ehci debug port console"
463 define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
466 comment "Console will log at this level unless changed"
468 define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
471 comment "Error messages up to this level can be printed"
473 define CONFIG_SERIAL_POST
476 comment "Enable SERIAL POST codes"
478 define CONFIG_NO_POST
481 comment "Disable POST codes"
483 define CONFIG_TTYS0_BASE
487 comment "Base address for 8250 uart for the serial console"
489 define CONFIG_TTYS0_BAUD
492 comment "Default baud rate for serial console"
494 define CONFIG_TTYS0_DIV
498 comment "Allow UART divisor to be set explicitly"
500 define CONFIG_TTYS0_LCS
504 comment "Default flow control settings for the 8250 serial console uart"
507 define CONFIG_USE_PRINTK_IN_CAR
510 comment "use printk instead of print in CAR stage code"
512 define CONFIG_ASSEMBLER_DEBUG
515 comment "Create disassembly files for debugging"
518 ###############################################
520 ###############################################
522 define CONFIG_MAINBOARD
523 default "Mainboard_not_set"
525 comment "Mainboard name"
527 define CONFIG_MAINBOARD_PART_NUMBER
528 default "Part_number_not_set"
531 comment "Part number of mainboard"
533 define CONFIG_MAINBOARD_VENDOR
534 default "Vendor_not_set"
537 comment "Vendor of mainboard"
539 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
542 comment "PCI Vendor ID of mainboard manufacturer"
544 define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
548 comment "PCI susbsystem device id assigned my mainboard manufacturer"
550 define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
553 comment "Default power on after power fail setting"
555 define CONFIG_SYS_CLK_FREQ
558 comment "System clock frequency in MHz"
560 define CONFIG_EPIA_VT8237R_INIT
563 comment "Enable EPIA Specific Initialisation of VT8237R SB"
565 ###############################################
567 ###############################################
572 comment "Define if we support SMP"
574 define CONFIG_MAX_CPUS
577 comment "Maximum CPU count for this machine"
579 define CONFIG_MAX_PHYSICAL_CPUS
582 comment "Maximum physical CPU count for this machine"
584 define CONFIG_LOGICAL_CPUS
587 comment "Should multiple cpus per die be enabled?"
589 define CONFIG_AP_IN_SIPI_WAIT
592 comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
594 define CONFIG_GENERATE_MP_TABLE
597 comment "Define to build an MP table"
599 define CONFIG_SERIAL_CPU_INIT
602 comment "Serialize CPU init"
604 define CONFIG_APIC_ID_OFFSET
607 comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
609 define CONFIG_ENABLE_APIC_EXT_ID
612 comment "Enable APIC ext id mode 8 bit"
614 define CONFIG_LIFT_BSP_APIC_ID
617 comment "decide if we lift bsp apic id while ap apic id"
619 ###############################################
621 ###############################################
623 define CONFIG_MULTIBOOT
626 comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
628 define CONFIG_ROM_PAYLOAD
631 comment "Boot image is located in ROM"
633 define CONFIG_COMPRESSED_PAYLOAD_NRV2B
636 comment "NRV2B compressed boot image is located in ROM"
638 define CONFIG_COMPRESSED_PAYLOAD_LZMA
641 comment "LZMA compressed boot image is located in ROM"
643 define CONFIG_PRECOMPRESSED_PAYLOAD
646 comment "boot image is already compressed"
649 define CONFIG_USE_WATCHDOG_ON_BOOT
652 comment "Use the watchdog on booting"
655 ###############################################
656 # Plugin Device support options
657 ###############################################
659 define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
662 comment "Enable support for plugin Hypertransport busses"
664 define CONFIG_AGP_PLUGIN_SUPPORT
667 comment "Enable support for plugin AGP busses"
669 define CONFIG_CARDBUS_PLUGIN_SUPPORT
672 comment "Enable support cardbus plugin cards"
674 define CONFIG_PCIX_PLUGIN_SUPPORT
677 comment "Enable support for plugin PCI-X busses"
679 define CONFIG_PCIEXP_PLUGIN_SUPPORT
682 comment "Enable support for plugin PCI-E busses"
685 ###############################################
687 ###############################################
689 define CONFIG_GENERATE_PIRQ_TABLE
692 comment "Define if we have a PIRQ table"
694 define CONFIG_PIRQ_ROUTE
697 comment "Define if we have a PIRQ table and want routing IRQs"
699 define CONFIG_IRQ_SLOT_COUNT
702 comment "Number of IRQ slots"
704 define CONFIG_PCIBIOS_IRQ
707 comment "PCIBIOS IRQ support"
712 comment "IOAPIC support"
715 ###############################################
716 # Options for memory mapped I/O
717 ###############################################
719 define CONFIG_PCI_IO_CFG_EXT
722 comment "allow 4K register space via io CFG port"
725 define CONFIG_PCIC0_CFGADDR
729 comment "Address of PCI Configuration Address Register"
731 define CONFIG_PCIC0_CFGDATA
735 comment "Address of PCI Configuration Data Register"
737 define CONFIG_ISA_IO_BASE
741 comment "Base address of PCI/ISA I/O address range"
743 define CONFIG_ISA_MEM_BASE
747 comment "Base address of PCI/ISA memory address range"
749 define CONFIG_PNP_CFGADDR
753 comment "PNP Configuration Address Register offset"
755 define CONFIG_PNP_CFGDATA
759 comment "PNP Configuration Data Register offset"
761 define CONFIG_IO_BASE
765 comment "Base address of memory mapped I/O operations"
768 ###############################################
769 # Options for embedded systems
770 ###############################################
772 define CONFIG_EMBEDDED_RAM_SIZE
775 comment "Embedded boards generally have fixed RAM size"
778 ###############################################
780 ###############################################
782 define CONFIG_GDB_STUB
785 comment "Compile in gdb stub support?"
788 define CONFIG_HAVE_INIT_TIMER
791 comment "Have a init_timer function"
793 define CONFIG_HAVE_HARD_RESET
796 comment "Have hard reset"
798 define CONFIG_HAVE_SMI_HANDLER
801 comment "Set, if the board needs an SMI handler"
803 define CONFIG_MEMORY_HOLE
806 comment "Set to deal with memory hole"
808 define CONFIG_MAX_REBOOT_CNT
811 comment "Set maximum reboots"
814 ###############################################
815 # Misc device options
816 ###############################################
818 define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
821 comment "Include board specific FAN control initialization"
823 define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
826 comment "Use timer2 to callibrate the x86 time stamp counter"
828 define CONFIG_INTEL_PPRO_MTRR
833 define CONFIG_UDELAY_TSC
836 comment "Implement udelay with the x86 time stamp counter"
838 define CONFIG_UDELAY_IO
841 comment "Implement udelay with x86 io registers"
843 define CONFIG_UDELAY_LAPIC
846 comment "Implement udelay with the x86 Local APIC"
848 define CONFIG_FAKE_SPDROM
851 comment "Use this to fake spd rom values"
854 define CONFIG_GENERATE_ACPI_TABLES
857 comment "Define to build ACPI tables"
860 define CONFIG_HAVE_ACPI_RESUME
863 comment "Define to build ACPI with resume support"
866 define CONFIG_ACPI_SSDTX_NUM
869 comment "extra ssdt num for PCI Device"
872 define CONFIG_AGP_APERTURE_SIZE
876 comment "AGP graphics virtual memory aperture size"
879 define CONFIG_HT_CHAIN_UNITID_BASE
882 comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
885 define CONFIG_HT_CHAIN_END_UNITID_BASE
888 comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
891 define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
894 comment "this will decided if only offset SB hypertransport chain"
897 define CONFIG_SB_HT_CHAIN_ON_BUS0
900 comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
903 define CONFIG_PCI_BUS_SEGN_BITS
906 comment "It could be 0, 1, 2, 3 and 4 only"
909 define CONFIG_MMCONF_SUPPORT
912 comment "enable mmconfig for pci conf"
915 define CONFIG_MMCONF_SUPPORT_DEFAULT
918 comment "enable mmconfig for pci conf"
921 define CONFIG_MMCONF_BASE_ADDRESS
925 comment "enable mmconfig base address"
928 define CONFIG_HW_MEM_HOLE_SIZEK
931 comment "Opteron E0 later memory hole size in K, 0 mean disable"
934 define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
937 comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
940 define CONFIG_VAR_MTRR_HOLE
943 comment "using hole in MTRR instead of increasing method"
946 define CONFIG_K8_HT_FREQ_1G_SUPPORT
949 comment "Optern E0 later could support 1G HT, but still depends MB design"
952 define CONFIG_K8_REV_F_SUPPORT
955 comment "Opteron Rev F (DDR2) support"
961 comment "Opteron cpu bus num base"
967 comment "Opteron cpu device num base"
970 define CONFIG_HT3_SUPPORT
973 comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
976 define CONFIG_EXT_RT_TBL_SUPPORT
979 comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
982 define CONFIG_EXT_CONF_SUPPORT
985 comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
988 define CONFIG_DIMM_SUPPORT
992 comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
995 define CONFIG_CPU_SOCKET_TYPE
998 comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
1001 define CONFIG_CPU_ADDR_BITS
1004 comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
1010 comment "Include VGA initialisation code"
1013 define CONFIG_VGA_ROM_RUN
1016 comment "Init x86 ROMs on VGA-class PCI devices"
1019 define CONFIG_PCI_ROM_RUN
1022 comment "Init x86 ROMs on all PCI devices"
1025 define CONFIG_PCI_OPTION_ROM_RUN_YABEL
1028 comment "Use Yabel instead of old bios emulator"
1031 define CONFIG_YABEL_DEBUG_FLAGS
1034 comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
1037 define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
1040 comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
1044 define CONFIG_PCI_OPTION_ROM_RUN_REALMODE
1047 comment "Use Yabel instead of old bios emulator"
1050 define CONFIG_PCI_64BIT_PREF_MEM
1053 comment "allow PCI device get 4G above Region as pref mem"
1056 define CONFIG_AMDMCT
1059 comment "use AMD MCT to init RAM instead of native code"
1062 define CONFIG_AMD_UCODE_PATCH_FILE
1066 comment "name of the microcode patch file"
1069 define CONFIG_K8_MEM_BANK_B_ONLY
1072 comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
1075 define CONFIG_VIDEO_MB
1078 comment "Integrated graphics with UMA has dynamic setup"
1081 define CONFIG_GFXUMA
1087 define CONFIG_HAVE_MAINBOARD_RESOURCES
1090 comment "Enable if the mainboard/chipset requires extra entries in the memory map"
1093 define CONFIG_HAVE_LOW_TABLES
1096 comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
1099 define CONFIG_WRITE_HIGH_TABLES
1102 comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
1105 define CONFIG_SPLASH_GRAPHIC
1108 comment "Paint a splash screen"
1111 define CONFIG_GX1_VIDEO
1114 comment "Build in GX1's graphic support"
1117 define CONFIG_GX1_VIDEOMODE
1120 comment "Define video mode after reset"
1129 define CONFIG_PCIE_CONFIGSPACE_HOLE
1132 comment "Leave a hole for PCIe config space in the device allocator"