1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "util.h" // debug_enter
10 #include "disk.h" // floppy_tick
11 #include "cmos.h" // inb_cmos
12 #include "pic.h" // eoi_pic1
13 #include "bregs.h" // struct bregs
14 #include "biosvar.h" // GET_GLOBAL
17 #define RTC_A_UIP 0x80
19 #define RTC_B_SET 0x80
20 #define RTC_B_PIE 0x40
21 #define RTC_B_AIE 0x20
22 #define RTC_B_UIE 0x10
23 #define RTC_B_BIN 0x04
24 #define RTC_B_24HR 0x02
25 #define RTC_B_DSE 0x01
28 // Bits for PORT_PS2_CTRLB
29 #define PPCB_T2GATE (1<<0)
30 #define PPCB_SPKR (1<<1)
31 #define PPCB_T2OUT (1<<5)
33 // Bits for PORT_PIT_MODE
34 #define PM_SEL_TIMER0 (0<<6)
35 #define PM_SEL_TIMER1 (1<<6)
36 #define PM_SEL_TIMER2 (2<<6)
37 #define PM_SEL_READBACK (3<<6)
38 #define PM_ACCESS_LATCH (0<<4)
39 #define PM_ACCESS_LOBYTE (1<<4)
40 #define PM_ACCESS_HIBYTE (2<<4)
41 #define PM_ACCESS_WORD (3<<4)
42 #define PM_MODE0 (0<<1)
43 #define PM_MODE1 (1<<1)
44 #define PM_MODE2 (2<<1)
45 #define PM_MODE3 (3<<1)
46 #define PM_MODE4 (4<<1)
47 #define PM_MODE5 (5<<1)
48 #define PM_CNT_BINARY (0<<0)
49 #define PM_CNT_BCD (1<<0)
52 /****************************************************************
54 ****************************************************************/
56 #define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
57 #define CALIBRATE_COUNT 0x800 // Approx 1.7ms
65 u8 orig = inb(PORT_PS2_CTRLB);
66 outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
67 /* binary, mode 0, LSB/MSB, Ch 2 */
68 outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
70 outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
72 outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
74 u64 start = rdtscll();
75 while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
79 // Restore PORT_PS2_CTRLB
80 outb(orig, PORT_PS2_CTRLB);
82 // Store calibrated cpu khz.
83 u64 diff = end - start;
84 dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
85 , (u32)start, (u32)end, (u32)diff);
86 u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
87 SET_GLOBAL(cpu_khz, hz / 1000);
89 dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
95 u64 start = rdtscll();
96 u64 end = start + diff;
97 while (rdtscll() <= end)
104 u32 khz = GET_GLOBAL(cpu_khz);
105 tscsleep(count * khz / 1000000);
110 u32 khz = GET_GLOBAL(cpu_khz);
111 tscsleep(count * khz / 1000);
116 u32 khz = GET_GLOBAL(cpu_khz);
117 tscsleep(count * khz);
120 // Return the TSC value that is 'msecs' time in the future.
122 calc_future_tsc(u32 msecs)
124 u32 khz = GET_GLOBAL(cpu_khz);
125 return rdtscll() + ((u64)khz * msecs);
129 /****************************************************************
131 ****************************************************************/
136 // This function checks to see if the update-in-progress bit
137 // is set in CMOS Status Register A. If not, it returns 0.
138 // If it is set, it tries to wait until there is a transition
139 // to 0, and will return 0 if such a transition occurs. A -1
140 // is returned only after timing out. The maximum period
141 // that this bit should be set is constrained to 244useconds, so
142 // we wait for 1 msec max.
144 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
146 u64 end = calc_future_tsc(1);
148 if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
150 } while (rdtscll() <= end);
152 // update-in-progress never transitioned to 0
159 // timer0: binary count, 16bit count, mode 2
160 outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
161 // maximum count of 0000H = 18.2Hz
162 outb(0x0, PORT_PIT_COUNTER0);
163 outb(0x0, PORT_PIT_COUNTER0);
169 outb_cmos(0x26, CMOS_STATUS_A); // 976.5625us updates
170 u8 regB = inb_cmos(CMOS_STATUS_B);
171 outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
172 inb_cmos(CMOS_STATUS_C);
173 inb_cmos(CMOS_STATUS_D);
179 return (val & 0xf) + ((val >> 4) * 10);
185 dprintf(3, "init timer\n");
191 u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
192 u32 ticks = (seconds * 18206507) / 1000000;
193 u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
194 ticks += (minutes * 10923904) / 10000;
195 u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
196 ticks += (hours * 65543427) / 1000;
197 SET_BDA(timer_counter, ticks);
198 SET_BDA(timer_rollover, 0);
200 enable_hwirq(0, entry_08);
201 enable_hwirq(8, entry_70);
205 /****************************************************************
206 * Standard clock functions
207 ****************************************************************/
209 // get current clock count
211 handle_1a00(struct bregs *regs)
213 u32 ticks = GET_BDA(timer_counter);
214 regs->cx = ticks >> 16;
216 regs->al = GET_BDA(timer_rollover);
217 SET_BDA(timer_rollover, 0); // reset flag
221 // Set Current Clock Count
223 handle_1a01(struct bregs *regs)
225 u32 ticks = (regs->cx << 16) | regs->dx;
226 SET_BDA(timer_counter, ticks);
227 SET_BDA(timer_rollover, 0); // reset flag
228 // XXX - should use set_code_success()?
235 handle_1a02(struct bregs *regs)
237 if (rtc_updating()) {
242 regs->dh = inb_cmos(CMOS_RTC_SECONDS);
243 regs->cl = inb_cmos(CMOS_RTC_MINUTES);
244 regs->ch = inb_cmos(CMOS_RTC_HOURS);
245 regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
253 handle_1a03(struct bregs *regs)
255 // Using a debugger, I notice the following masking/setting
256 // of bits in Status Register B, by setting Reg B to
257 // a few values and getting its value after INT 1A was called.
260 // before 1111 1101 0111 1101 0000 0000
261 // after 0110 0010 0110 0010 0000 0010
263 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
264 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
265 if (rtc_updating()) {
267 // fall through as if an update were not in progress
269 outb_cmos(regs->dh, CMOS_RTC_SECONDS);
270 outb_cmos(regs->cl, CMOS_RTC_MINUTES);
271 outb_cmos(regs->ch, CMOS_RTC_HOURS);
272 // Set Daylight Savings time enabled bit to requested value
273 u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
274 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
275 outb_cmos(val8, CMOS_STATUS_B);
277 regs->al = val8; // val last written to Reg B
283 handle_1a04(struct bregs *regs)
286 if (rtc_updating()) {
290 regs->cl = inb_cmos(CMOS_RTC_YEAR);
291 regs->dh = inb_cmos(CMOS_RTC_MONTH);
292 regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
293 if (CONFIG_COREBOOT) {
299 regs->ch = inb_cmos(CMOS_CENTURY);
307 handle_1a05(struct bregs *regs)
309 // Using a debugger, I notice the following masking/setting
310 // of bits in Status Register B, by setting Reg B to
311 // a few values and getting its value after INT 1A was called.
313 // try#1 try#2 try#3 try#4
314 // before 1111 1101 0111 1101 0000 0010 0000 0000
315 // after 0110 1101 0111 1101 0000 0010 0000 0000
317 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
318 // My assumption: RegB = (RegB & 01111111b)
319 if (rtc_updating()) {
324 outb_cmos(regs->cl, CMOS_RTC_YEAR);
325 outb_cmos(regs->dh, CMOS_RTC_MONTH);
326 outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
327 if (!CONFIG_COREBOOT)
328 outb_cmos(regs->ch, CMOS_CENTURY);
329 // clear halt-clock bit
330 u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
331 outb_cmos(val8, CMOS_STATUS_B);
333 regs->al = val8; // AL = val last written to Reg B
337 // Set Alarm Time in CMOS
339 handle_1a06(struct bregs *regs)
341 // Using a debugger, I notice the following masking/setting
342 // of bits in Status Register B, by setting Reg B to
343 // a few values and getting its value after INT 1A was called.
346 // before 1101 1111 0101 1111 0000 0000
347 // after 0110 1111 0111 1111 0010 0000
349 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
350 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
351 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
353 if (val8 & RTC_B_AIE) {
354 // Alarm interrupt enabled already
358 if (rtc_updating()) {
360 // fall through as if an update were not in progress
362 outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
363 outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
364 outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
365 // enable Status Reg B alarm bit, clear halt clock bit
366 outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
372 handle_1a07(struct bregs *regs)
374 // Using a debugger, I notice the following masking/setting
375 // of bits in Status Register B, by setting Reg B to
376 // a few values and getting its value after INT 1A was called.
378 // try#1 try#2 try#3 try#4
379 // before 1111 1101 0111 1101 0010 0000 0010 0010
380 // after 0100 0101 0101 0101 0000 0000 0000 0010
382 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
383 // My assumption: RegB = (RegB & 01010111b)
384 u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
385 // clear clock-halt bit, disable alarm bit
386 outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
388 regs->al = val8; // val last written to Reg B
394 handle_1aXX(struct bregs *regs)
399 // INT 1Ah Time-of-day Service Entry Point
401 handle_1a(struct bregs *regs)
403 debug_enter(regs, DEBUG_HDL_1a);
405 case 0x00: handle_1a00(regs); break;
406 case 0x01: handle_1a01(regs); break;
407 case 0x02: handle_1a02(regs); break;
408 case 0x03: handle_1a03(regs); break;
409 case 0x04: handle_1a04(regs); break;
410 case 0x05: handle_1a05(regs); break;
411 case 0x06: handle_1a06(regs); break;
412 case 0x07: handle_1a07(regs); break;
413 case 0xb1: handle_1ab1(regs); break;
414 default: handle_1aXX(regs); break;
418 // INT 08h System Timer ISR Entry Point
422 debug_isr(DEBUG_ISR_08);
426 u32 counter = GET_BDA(timer_counter);
428 // compare to one days worth of timer ticks at 18.2 hz
429 if (counter >= 0x001800B0) {
430 // there has been a midnight rollover at this point
432 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
435 SET_BDA(timer_counter, counter);
437 // chain to user timer tick INT #0x1c
439 call16_simpint(0x1c, &eax, &flags);
445 /****************************************************************
447 ****************************************************************/
450 set_usertimer(u32 usecs, u16 seg, u16 offset)
452 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
455 // Interval not already set.
456 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
457 SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
458 SET_BDA(user_wait_timeout, usecs);
460 // Turn on the Periodic Interrupt timer
461 u8 bRegister = inb_cmos(CMOS_STATUS_B);
462 outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
470 // Turn off status byte.
471 SET_BDA(rtc_wait_flag, 0);
472 // Clear the Periodic Interrupt.
473 u8 bRegister = inb_cmos(CMOS_STATUS_B);
474 outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
477 #define RET_ECLOCKINUSE 0x83
479 // Wait for CX:DX microseconds
481 handle_1586(struct bregs *regs)
483 // Use the rtc to wait for the specified time.
485 u32 count = (regs->cx << 16) | regs->dx;
486 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
488 set_code_fail(regs, RET_ECLOCKINUSE);
498 // Set Interval requested.
500 handle_158300(struct bregs *regs)
502 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
504 // Interval already set.
505 set_code_fail(regs, RET_EUNSUPPORTED);
510 // Clear interval requested
512 handle_158301(struct bregs *regs)
519 handle_1583XX(struct bregs *regs)
521 set_code_fail(regs, RET_EUNSUPPORTED);
526 handle_1583(struct bregs *regs)
529 case 0x00: handle_158300(regs); break;
530 case 0x01: handle_158301(regs); break;
531 default: handle_1583XX(regs); break;
535 // int70h: IRQ8 - CMOS RTC
539 debug_isr(DEBUG_ISR_70);
541 // Check which modes are enabled and have occurred.
542 u8 registerB = inb_cmos(CMOS_STATUS_B);
543 u8 registerC = inb_cmos(CMOS_STATUS_C);
545 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
547 if (registerC & RTC_B_AIE) {
548 // Handle Alarm Interrupt.
550 call16_simpint(0x4a, &eax, &flags);
552 if (!(registerC & RTC_B_PIE))
555 // Handle Periodic Interrupt.
557 if (!GET_BDA(rtc_wait_flag))
560 // Wait Interval (Int 15, AH=83) active.
561 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
563 // Done waiting - write to specified flag byte.
564 u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
565 u16 segment = segoff >> 16;
566 u16 offset = segoff & 0xffff;
567 u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
568 SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
574 SET_BDA(user_wait_timeout, time);