2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity beh_uart_tx_tb is
7 end entity beh_uart_tx_tb;
9 architecture sim of beh_uart_tx_tb is
10 constant CLK_FREQ : integer := 33000000;
11 constant BAUDRATE : integer := 115200;
12 constant BAUD : integer := CLK_FREQ/BAUDRATE;
14 signal sys_clk, sys_res_n, txd, tx_new, tx_done : std_logic;
15 signal tx_data : std_logic_vector (7 downto 0);
16 signal stop : boolean := false;
18 inst : entity work.uart_tx(beh)
25 sys_res_n => sys_res_n,
44 procedure exec_tc(testnr : integer;
45 constant expectedresult : std_logic_vector(9 downto 0);
46 constant testvector : std_logic_vector(7 downto 0)) is
47 variable success : boolean := true;
50 tx_data <= testvector;
53 -- ein BAUD-cycle auf high warten
54 icwait(sys_clk, BAUD);
56 -- in der mitte abtasten
57 icwait(sys_clk, BAUD/2);
59 if txd /= expectedresult(9-i) then
63 icwait(sys_clk, BAUD);
67 wait until tx_done = '1';
69 wait until tx_done = '0';
71 report "testfall " & integer'image(testnr) & " war erfolgreich";
73 report "testfall " & integer'image(testnr) & " schlug fehl";
80 tx_data <= (others => '0');
85 -- 1. parameter: testfallnummer
86 -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
87 -- 3. parameter: byte das gesendet werden soll
88 exec_tc(1, b"0000011111", b"00001111");
89 exec_tc(2, b"0101010101", b"10101010");
90 exec_tc(3, b"0110011001", b"11001100");
91 exec_tc(4, b"0001100111", b"00110011");
92 exec_tc(5, b"0010101011", b"01010101");
93 exec_tc(6, b"0100110111", b"10011011");