2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 entity beh_uart_rx_tb is
7 end entity beh_uart_rx_tb;
9 architecture sim of beh_uart_rx_tb is
10 constant CLK_FREQ : integer := 33000000;
11 constant BAUDRATE : integer := 115200;
12 constant BAUD : integer := CLK_FREQ/BAUDRATE;
14 signal sys_clk, sys_res_n, rxd, rx_new : std_logic;
15 signal rx_data : std_logic_vector (7 downto 0);
16 signal stop : boolean := false;
18 inst : entity work.uart_rx(beh)
25 sys_res_n => sys_res_n,
43 procedure exec_tc(testnr : integer;
44 constant testvector : std_logic_vector(9 downto 0);
45 constant expectedresult : std_logic_vector(7 downto 0)) is
47 -- vorher auf high setzen um falling edge simulieren zu koennen
52 rxd <= testvector(9-i);
54 icwait(sys_clk, BAUD);
58 wait until rx_new = '1';
59 if expectedresult = rx_data then
60 report "testfall " & integer'image(testnr) & " war erfolgreich";
62 report "testfall " & integer'image(testnr) & " schlug fehl";
67 variable testvector : std_logic_vector(9 downto 0);
68 variable expectedresult : std_logic_vector(7 downto 0);
76 -- 1. parameter: testfallnummer
77 -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
78 -- 3. parameter: byte das rauskommen soll (umgekehrte reihenfolge)
79 exec_tc(1, b"0000011111", b"11110000");
80 exec_tc(2, b"0101010101", b"01010101");
81 exec_tc(3, b"0110011001", b"00110011");
82 exec_tc(4, b"0001100111", b"11001100");
83 exec_tc(5, b"0010101011", b"10101010");
84 exec_tc(6, b"0100110111", b"11011001");