4 #include "types.h" // u8
5 #include "config.h" // CONFIG_MAX_ATA_INTERFACES
16 extern struct ata_channel_s ATA_channels[CONFIG_MAX_ATA_INTERFACES];
17 int cdrom_read(struct disk_op_s *op);
18 int ata_cmd_packet(struct drive_s *drive_g, u8 *cmdbuf, u8 cmdlen
19 , u32 length, void *buf_fl);
21 int process_ata_op(struct disk_op_s *op);
22 int process_atapi_op(struct disk_op_s *op);
23 void describe_ata(struct drive_s *drive_g);
24 void describe_atapi(struct drive_s *drive_g);
26 // Global defines -- ATA register and register bits.
27 // command block & control block regs
28 #define ATA_CB_DATA 0 // data reg in/out pio_base_addr1+0
29 #define ATA_CB_ERR 1 // error in pio_base_addr1+1
30 #define ATA_CB_FR 1 // feature reg out pio_base_addr1+1
31 #define ATA_CB_SC 2 // sector count in/out pio_base_addr1+2
32 #define ATA_CB_SN 3 // sector number in/out pio_base_addr1+3
33 #define ATA_CB_CL 4 // cylinder low in/out pio_base_addr1+4
34 #define ATA_CB_CH 5 // cylinder high in/out pio_base_addr1+5
35 #define ATA_CB_DH 6 // device head in/out pio_base_addr1+6
36 #define ATA_CB_STAT 7 // primary status in pio_base_addr1+7
37 #define ATA_CB_CMD 7 // command out pio_base_addr1+7
39 #define ATA_CB_ASTAT 2 // alternate status in pio_base_addr2+2
40 #define ATA_CB_DC 2 // device control out pio_base_addr2+2
41 #define ATA_CB_DA 3 // device address in pio_base_addr2+3
43 #define ATA_CB_ER_ICRC 0x80 // ATA Ultra DMA bad CRC
44 #define ATA_CB_ER_BBK 0x80 // ATA bad block
45 #define ATA_CB_ER_UNC 0x40 // ATA uncorrected error
46 #define ATA_CB_ER_MC 0x20 // ATA media change
47 #define ATA_CB_ER_IDNF 0x10 // ATA id not found
48 #define ATA_CB_ER_MCR 0x08 // ATA media change request
49 #define ATA_CB_ER_ABRT 0x04 // ATA command aborted
50 #define ATA_CB_ER_NTK0 0x02 // ATA track 0 not found
51 #define ATA_CB_ER_NDAM 0x01 // ATA address mark not found
53 #define ATA_CB_ER_P_SNSKEY 0xf0 // ATAPI sense key (mask)
54 #define ATA_CB_ER_P_MCR 0x08 // ATAPI Media Change Request
55 #define ATA_CB_ER_P_ABRT 0x04 // ATAPI command abort
56 #define ATA_CB_ER_P_EOM 0x02 // ATAPI End of Media
57 #define ATA_CB_ER_P_ILI 0x01 // ATAPI Illegal Length Indication
59 // ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC)
60 #define ATA_CB_SC_P_TAG 0xf8 // ATAPI tag (mask)
61 #define ATA_CB_SC_P_REL 0x04 // ATAPI release
62 #define ATA_CB_SC_P_IO 0x02 // ATAPI I/O
63 #define ATA_CB_SC_P_CD 0x01 // ATAPI C/D
65 // bits 7-4 of the device/head (CB_DH) reg
66 #define ATA_CB_DH_DEV0 0xa0 // select device 0
67 #define ATA_CB_DH_DEV1 0xb0 // select device 1
68 #define ATA_CB_DH_LBA 0x40 // use LBA
70 // status reg (CB_STAT and CB_ASTAT) bits
71 #define ATA_CB_STAT_BSY 0x80 // busy
72 #define ATA_CB_STAT_RDY 0x40 // ready
73 #define ATA_CB_STAT_DF 0x20 // device fault
74 #define ATA_CB_STAT_WFT 0x20 // write fault (old name)
75 #define ATA_CB_STAT_SKC 0x10 // seek complete
76 #define ATA_CB_STAT_SERV 0x10 // service
77 #define ATA_CB_STAT_DRQ 0x08 // data request
78 #define ATA_CB_STAT_CORR 0x04 // corrected
79 #define ATA_CB_STAT_IDX 0x02 // index
80 #define ATA_CB_STAT_ERR 0x01 // error (ATA)
81 #define ATA_CB_STAT_CHK 0x01 // check (ATAPI)
83 // device control reg (CB_DC) bits
84 #define ATA_CB_DC_HD15 0x08 // bit should always be set to one
85 #define ATA_CB_DC_SRST 0x04 // soft reset
86 #define ATA_CB_DC_NIEN 0x02 // disable interrupts
88 // Most mandtory and optional ATA commands (from ATA-3),
89 #define ATA_CMD_CFA_ERASE_SECTORS 0xC0
90 #define ATA_CMD_CFA_REQUEST_EXT_ERR_CODE 0x03
91 #define ATA_CMD_CFA_TRANSLATE_SECTOR 0x87
92 #define ATA_CMD_CFA_WRITE_MULTIPLE_WO_ERASE 0xCD
93 #define ATA_CMD_CFA_WRITE_SECTORS_WO_ERASE 0x38
94 #define ATA_CMD_CHECK_POWER_MODE1 0xE5
95 #define ATA_CMD_CHECK_POWER_MODE2 0x98
96 #define ATA_CMD_DEVICE_RESET 0x08
97 #define ATA_CMD_EXECUTE_DEVICE_DIAGNOSTIC 0x90
98 #define ATA_CMD_FLUSH_CACHE 0xE7
99 #define ATA_CMD_FORMAT_TRACK 0x50
100 #define ATA_CMD_IDENTIFY_DEVICE 0xEC
101 #define ATA_CMD_IDENTIFY_PACKET_DEVICE 0xA1
102 #define ATA_CMD_IDLE1 0xE3
103 #define ATA_CMD_IDLE2 0x97
104 #define ATA_CMD_IDLE_IMMEDIATE1 0xE1
105 #define ATA_CMD_IDLE_IMMEDIATE2 0x95
106 #define ATA_CMD_INITIALIZE_DRIVE_PARAMETERS 0x91
107 #define ATA_CMD_INITIALIZE_DEVICE_PARAMETERS 0x91
108 #define ATA_CMD_NOP 0x00
109 #define ATA_CMD_PACKET 0xA0
110 #define ATA_CMD_READ_BUFFER 0xE4
111 #define ATA_CMD_READ_DMA 0xC8
112 #define ATA_CMD_READ_DMA_EXT 0x25
113 #define ATA_CMD_READ_DMA_QUEUED 0xC7
114 #define ATA_CMD_READ_DMA_QUEUED_EXT 0x26
115 #define ATA_CMD_READ_LOG_EXT 0x2F
116 #define ATA_CMD_READ_MULTIPLE 0xC4
117 #define ATA_CMD_READ_MULTIPLE_EXT 0x29
118 #define ATA_CMD_READ_NATIVE_MAX_ADDRESS 0xF8
119 #define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT 0x27
120 #define ATA_CMD_READ_SECTORS 0x20
121 #define ATA_CMD_READ_SECTORS_EXT 0x24
122 #define ATA_CMD_READ_VERIFY_SECTORS 0x40
123 #define ATA_CMD_READ_VERIFY_SECTORS_EXT 0x42
124 #define ATA_CMD_RECALIBRATE 0x10
125 #define ATA_CMD_REQUEST_SENSE 0x03
126 #define ATA_CMD_SEEK 0x70
127 #define ATA_CMD_SET_FEATURES 0xEF
128 #define ATA_CMD_SET_MAX 0xF9
129 #define ATA_CMD_SET_MAX_ADDRESS_EXT 0x37
130 #define ATA_CMD_SET_MULTIPLE_MODE 0xC6
131 #define ATA_CMD_SLEEP1 0xE6
132 #define ATA_CMD_SLEEP2 0x99
133 #define ATA_CMD_STANDBY1 0xE2
134 #define ATA_CMD_STANDBY2 0x96
135 #define ATA_CMD_STANDBY_IMMEDIATE1 0xE0
136 #define ATA_CMD_STANDBY_IMMEDIATE2 0x94
137 #define ATA_CMD_WRITE_BUFFER 0xE8
138 #define ATA_CMD_WRITE_DMA 0xCA
139 #define ATA_CMD_WRITE_DMA_EXT 0x35
140 #define ATA_CMD_WRITE_DMA_QUEUED 0xCC
141 #define ATA_CMD_WRITE_DMA_QUEUED_EXT 0x36
142 #define ATA_CMD_WRITE_LOG_EXT 0x3F
143 #define ATA_CMD_WRITE_MULTIPLE 0xC5
144 #define ATA_CMD_WRITE_MULTIPLE_EXT 0x39
145 #define ATA_CMD_WRITE_SECTORS 0x30
146 #define ATA_CMD_WRITE_SECTORS_EXT 0x34
147 #define ATA_CMD_WRITE_VERIFY 0x3C