1 /* Copyright 2000 AG Electronics Ltd. */
2 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
4 /* In the MSR, not all bits are interesting to us
5 13 - POW - Power management
6 14 - TGPR - temporary registers for page table routines
7 15 - ILE - Exception little endian
8 16 - EE - External interrupts
9 17 - PR - Privilege level
10 18 - FP - Floating Point available
11 19 - ME - Machine check exception enable
12 20 - FE0 - Floating exception mode 0
13 21 - SE - Single step trace mode
14 22 - BE - Branch trace enable
15 23 - FE1 - Floating exception mode 1
16 25 - IP - Exception prefix
17 26 - IR - Instruction address translation
18 27 - DR - Data address translation
19 30 - RI - Recoverable exception
20 31 - LE - Little endian mode
21 MSR_MASK is the bits we do not change.
24 #define MSR_MASK 0xfff8008c
25 #define MSR_POW 0x00040000
26 #define MSR_TGPR 0x00020000
27 #define MSR_ILE 0x00010000
28 #define MSR_EE 0x00008000
29 #define MSR_PR 0x00004000
30 #define MSR_FP 0x00002000
31 #define MSR_ME 0x00001000
32 #define MSR_FE0 0x00000800
33 #define MSR_SE 0x00000400
34 #define MSR_BE 0x00000200
35 #define MSR_FE1 0x00000100
36 #define MSR_IP 0x00000040
37 #define MSR_IR 0x00000020
38 #define MSR_DR 0x00000010
39 #define MSR_RI 0x00000002
40 #define MSR_LE 0x00000001
42 #define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
44 /* We are interested in the following hid0 bits:
45 6 - ECLK - Enable external test clock (603 only)
46 11 - DPM - Turn on dynamic power management (603 only)
47 15 - NHR - Not hard reset
48 16 - ICE - Instruction cache enable
49 17 - DCE - Data cache enable
50 18 - ILOCK - Instruction cache lock
51 19 - DLOCK - Data cache lock
52 20 - ICFI - Instruction cache invalidate
53 21 - DCFI - Data cache invalidate
54 24 - NOSER - Serial execution disable (604 only - turbo mode)
55 24 - SGE - Store gathering enable (7410 only)
56 29 - BHT - Branch history table (604 only)
58 I made up the tags for the 604 specific bits, as they aren't
59 named in the 604 book. The 603 book calls the invalidate bits
60 ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
61 one, and Motorola named the other. */
63 #define HID0_ECLK 0x02000000
64 #define HID0_DPM 0x00100000
65 #define HID0_NHR 0x00010000
66 #define HID0_ICE 0x00008000
67 #define HID0_DCE 0x00004000
68 #define HID0_ILOCK 0x00002000
69 #define HID0_DLOCK 0x00001000
70 #define HID0_ICFI 0x00000800
71 #define HID0_DCFI 0x00000400
72 #define HID0_NOSER 0x00000080
73 #define HID0_SGE 0x00000080
74 #define HID0_BTIC 0x00000020
75 #define HID0_BHT 0x00000004
82 * BL field in upper BAT register
84 #define BAT_BL_128K 0x00000000
85 #define BAT_BL_256K 0x00000004
86 #define BAT_BL_512K 0x0000000C
87 #define BAT_BL_1M 0x0000001C
88 #define BAT_BL_2M 0x0000003C
89 #define BAT_BL_4M 0x0000007C
90 #define BAT_BL_8M 0x000000FC
91 #define BAT_BL_16M 0x000001FC
92 #define BAT_BL_32M 0x000003FC
93 #define BAT_BL_64M 0x000007FC
94 #define BAT_BL_128M 0x00000FFC
95 #define BAT_BL_256M 0x00001FFC
98 * Supervisor/user valid mode in upper BAT register
100 #define BAT_VALID_SUPERVISOR 0x00000002
101 #define BAT_VALID_USER 0x00000001
102 #define BAT_INVALID 0x00000000
105 * WIMG bit setting in lower BAT register
107 #define BAT_WRITE_THROUGH 0x00000040
108 #define BAT_CACHE_INHIBITED 0x00000020
109 #define BAT_COHERENT 0x00000010
110 #define BAT_GUARDED 0x00000008
113 * Protection bits in lower BAT register
115 #define BAT_NO_ACCESS 0x00000000
116 #define BAT_READ_ONLY 0x00000001
117 #define BAT_READ_WRITE 0x00000002
120 unsigned __getmsr(void);
121 void __setmsr(unsigned value);
122 unsigned __gethid0(void);
123 unsigned __gethid1(void);
124 void __sethid0(unsigned value);
125 unsigned __getpvr(void);