7 * Structure definitions for SMP machines following the
8 * Intel Multiprocessing Specification 1.1 and 1.4.
12 * This tag identifies where the SMP configuration
16 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
19 * a maximum of 16 APICs with the current APIC ID architecture.
24 #define SMP_FLOATING_TABLE_LEN sizeof(struct intel_mp_floating)
26 struct intel_mp_floating
28 char mpf_signature[4]; /* "_MP_" */
29 unsigned long mpf_physptr; /* Configuration table address */
30 unsigned char mpf_length; /* Our length (paragraphs) */
31 unsigned char mpf_specification;/* Specification version */
32 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
33 unsigned char mpf_feature1; /* Standard or configuration ? */
34 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
35 unsigned char mpf_feature3; /* Unused (0) */
36 unsigned char mpf_feature4; /* Unused (0) */
37 unsigned char mpf_feature5; /* Unused (0) */
40 struct mp_config_table
42 char mpc_signature[4];
43 #define MPC_SIGNATURE "PCMP"
44 unsigned short mpc_length; /* Size of table */
45 char mpc_spec; /* 0x01 */
48 char mpc_productid[12];
49 unsigned long mpc_oemptr; /* 0 if not present */
50 unsigned short mpc_oemsize; /* 0 if not present */
51 unsigned short mpc_entry_count;
52 unsigned long mpc_lapic; /* APIC address */
53 unsigned short mpe_length; /* Extended Table size */
54 unsigned char mpe_checksum; /* Extended Table checksum */
55 unsigned char reserved;
58 /* Followed by entries */
60 #define MP_PROCESSOR 0
66 struct mpc_config_processor
68 unsigned char mpc_type;
69 unsigned char mpc_apicid; /* Local APIC number */
70 unsigned char mpc_apicver; /* Its versions */
71 unsigned char mpc_cpuflag;
72 #define MPC_CPU_ENABLED 1 /* Processor is available */
73 #define MPC_CPU_BOOTPROCESSOR 2 /* Processor is the BP */
74 unsigned long mpc_cpufeature;
75 #define MPC_CPU_STEPPING_MASK 0x0F
76 #define MPC_CPU_MODEL_MASK 0xF0
77 #define MPC_CPU_FAMILY_MASK 0xF00
78 unsigned long mpc_featureflag; /* CPUID feature value */
79 unsigned long mpc_reserved[2];
84 unsigned char mpc_type;
85 unsigned char mpc_busid;
86 unsigned char mpc_bustype[6] __attribute((packed));
89 #define BUSTYPE_EISA "EISA"
90 #define BUSTYPE_ISA "ISA"
91 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
92 #define BUSTYPE_MCA "MCA"
93 #define BUSTYPE_VL "VL" /* Local bus */
94 #define BUSTYPE_PCI "PCI"
95 #define BUSTYPE_PCMCIA "PCMCIA"
97 struct mpc_config_ioapic
99 unsigned char mpc_type;
100 unsigned char mpc_apicid;
101 unsigned char mpc_apicver;
102 unsigned char mpc_flags;
103 #define MPC_APIC_USABLE 0x01
104 unsigned long mpc_apicaddr;
107 struct mpc_config_intsrc
109 unsigned char mpc_type;
110 unsigned char mpc_irqtype;
111 unsigned short mpc_irqflag;
112 unsigned char mpc_srcbus;
113 unsigned char mpc_srcbusirq;
114 unsigned char mpc_dstapic;
115 unsigned char mpc_dstirq;
118 enum mp_irq_source_types {
125 #define MP_IRQ_POLARITY_DEFAULT 0x0
126 #define MP_IRQ_POLARITY_HIGH 0x1
127 #define MP_IRQ_POLARITY_LOW 0x3
128 #define MP_IRQ_POLARITY_MASK 0x3
129 #define MP_IRQ_TRIGGER_DEFAULT 0x0
130 #define MP_IRQ_TRIGGER_EDGE 0x4
131 #define MP_IRQ_TRIGGER_LEVEL 0xc
132 #define MP_IRQ_TRIGGER_MASK 0xc
135 struct mpc_config_lintsrc
137 unsigned char mpc_type;
138 unsigned char mpc_irqtype;
139 unsigned short mpc_irqflag;
140 unsigned char mpc_srcbusid;
141 unsigned char mpc_srcbusirq;
142 unsigned char mpc_destapic;
143 #define MP_APIC_ALL 0xFF
144 unsigned char mpc_destapiclint;
148 * Default configurations
150 * 1 2 CPU ISA 82489DX
151 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
152 * 3 2 CPU EISA 82489DX
153 * 4 2 CPU MCA 82489DX
159 #define MAX_IRQ_SOURCES 128
160 #define MAX_MP_BUSSES 32
168 /* Followed by entries */
170 #define MPE_SYSTEM_ADDRESS_SPACE 0x80
171 #define MPE_BUS_HIERARCHY 0x81
172 #define MPE_COMPATIBILITY_ADDRESS_SPACE 0x82
174 struct mp_exten_config {
175 unsigned char mpe_type;
176 unsigned char mpe_length;
179 typedef struct mp_exten_config *mpe_t;
181 struct mp_exten_system_address_space {
182 unsigned char mpe_type;
183 unsigned char mpe_length;
184 unsigned char mpe_busid;
185 unsigned char mpe_address_type;
186 #define ADDRESS_TYPE_IO 0
187 #define ADDRESS_TYPE_MEM 1
188 #define ADDRESS_TYPE_PREFETCH 2
189 unsigned int mpe_address_base_low;
190 unsigned int mpe_address_base_high;
191 unsigned int mpe_address_length_low;
192 unsigned int mpe_address_length_high;
195 struct mp_exten_bus_hierarchy {
196 unsigned char mpe_type;
197 unsigned char mpe_length;
198 unsigned char mpe_busid;
199 unsigned char mpe_bus_info;
200 #define BUS_SUBTRACTIVE_DECODE 1
201 unsigned char mpe_parent_busid;
202 unsigned char reserved[3];
205 struct mp_exten_compatibility_address_space {
206 unsigned char mpe_type;
207 unsigned char mpe_length;
208 unsigned char mpe_busid;
209 unsigned char mpe_address_modifier;
210 #define ADDRESS_RANGE_SUBTRACT 1
211 #define ADDRESS_RANGE_ADD 0
212 unsigned int mpe_range_list;
213 #define RANGE_LIST_IO_ISA 0
219 #define RANGE_LIST_IO_VGA 1
231 /* Default local apic addr */
232 #define LAPIC_ADDR 0xFEE00000
234 void *smp_next_mpc_entry(struct mp_config_table *mc);
235 void *smp_next_mpe_entry(struct mp_config_table *mc);
237 void smp_write_processor(struct mp_config_table *mc,
238 unsigned char apicid, unsigned char apicver,
239 unsigned char cpuflag, unsigned int cpufeature,
240 unsigned int featureflag);
241 void smp_write_processors(struct mp_config_table *mc,
242 unsigned long *processor_map);
243 void smp_write_bus(struct mp_config_table *mc,
244 unsigned char id, unsigned char *bustype);
245 void smp_write_ioapic(struct mp_config_table *mc,
246 unsigned char id, unsigned char ver,
247 unsigned long apicaddr);
248 void smp_write_intsrc(struct mp_config_table *mc,
249 unsigned char irqtype, unsigned short irqflag,
250 unsigned char srcbus, unsigned char srcbusirq,
251 unsigned char dstapic, unsigned char dstirq);
252 void smp_write_lintsrc(struct mp_config_table *mc,
253 unsigned char irqtype, unsigned short irqflag,
254 unsigned char srcbusid, unsigned char srcbusirq,
255 unsigned char destapic, unsigned char destapiclint);
256 void smp_write_address_space(struct mp_config_table *mc,
257 unsigned char busid, unsigned char address_type,
258 unsigned int address_base_low, unsigned int address_base_high,
259 unsigned int address_length_low, unsigned int address_length_high);
260 void smp_write_bus_hierarchy(struct mp_config_table *mc,
261 unsigned char busid, unsigned char bus_info,
262 unsigned char parent_busid);
263 void smp_write_compatibility_address_space(struct mp_config_table *mc,
264 unsigned char busid, unsigned char address_modifier,
265 unsigned int range_list);
266 unsigned char smp_compute_checksum(void *v, int len);
267 void *smp_write_floating_table(unsigned long addr);
268 unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map);
270 /* A table (per mainboard) listing the initial apicid of each cpu. */
271 extern unsigned long initial_apicid[MAX_CPUS];
273 #else /* HAVE_MP_TABLE */
275 unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
279 #endif /* HAVE_MP_TABLE */