2 This software and ancillary information (herein called SOFTWARE )
3 called LinuxBIOS is made available under the terms described
4 here. The SOFTWARE has been approved for release with associated
5 LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
6 been authored by an employee or employees of the University of
7 California, operator of the Los Alamos National Laboratory under
8 Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
9 U.S. Government has rights to use, reproduce, and distribute this
10 SOFTWARE. The public may copy, distribute, prepare derivative works
11 and publicly display this SOFTWARE without charge, provided that this
12 Notice and any statement of authorship are reproduced on all copies.
13 Neither the Government nor the University makes any warranty, express
14 or implied, or assumes any liability or responsibility for the use of
15 this SOFTWARE. If SOFTWARE is modified to produce derivative works,
16 such modified SOFTWARE should be clearly marked, so as not to confuse
17 it with the version available from LANL.
19 /* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
28 * Bootstrap code for the Intel
37 /* yeah, yeah, I know these are macros, which is bad. Don't forget:
38 * we have almost no assembly, so I am not worrying just yet about this.
39 * we'll fix it someday if we care. My guess is we won't.
42 /* well we want functions. But first we want to see it work at all. */
47 #define RET_LABEL(label) \
50 #define CALL_LABEL(label) \
54 #define CALLSP(func) \
63 #define DELAY(x) mov x, %ecx ;\
68 * Macro: PCI_WRITE_CONFIG_BYTE
69 * Arguments: %eax address to write to (includes bus, device, function, &offset)
75 * Effects: writes a single byte to pci config space
77 * Notes: This routine is optimized for minimal register usage.
78 * And the tricks it does cannot scale beyond writing a single byte.
80 * What it does is almost simple.
81 * It preserves %eax (baring special bits) until it is written
82 * out to the appropriate port. And hides the data byte
83 * in the high half of edx.
85 * In %edx[3] it stores the byte to write.
86 * In %edx[2] it stores the lower three bits of the address.
90 #define PCI_WRITE_CONFIG_BYTE \
96 orl $0x80000000, %eax ; \
97 andl $0xfffffffc, %eax ; \
104 addl $0xcfc, %edx ; \
109 * Macro: PCI_WRITE_CONFIG_WORD
110 * Arguments: %eax address to write to (includes bus, device, function, &offset)
115 * Trashed: %eax, %edx
117 * Effects: writes a single byte to pci config space
119 * Notes: This routine is optimized for minimal register usage.
121 * What it does is almost simple.
122 * It preserves %eax (baring special bits) until it is written
123 * out to the appropriate port. And hides the least significant
124 * bits of the address in the high half of edx.
126 * In %edx[2] it stores the lower three bits of the address.
130 #define PCI_WRITE_CONFIG_WORD \
135 orl $0x80000000, %eax ; \
136 andl $0xfffffffc, %eax ; \
142 addl $0xcfc, %edx ; \
148 * Macro: PCI_WRITE_CONFIG_DWORD
149 * Arguments: %eax address to write to (includes bus, device, function, &offset)
150 * %ecx dword to write
154 * Trashed: %eax, %edx
156 * Effects: writes a single byte to pci config space
158 * Notes: This routine is optimized for minimal register usage.
160 * What it does is almost simple.
161 * It preserves %eax (baring special bits) until it is written
162 * out to the appropriate port. And hides the least significant
163 * bits of the address in the high half of edx.
165 * In %edx[2] it stores the lower three bits of the address.
169 #define PCI_WRITE_CONFIG_DWORD \
174 orl $0x80000000, %eax ; \
175 andl $0xfffffffc, %eax ; \
181 addl $0xcfc, %edx ; \
188 * Macro: PCI_READ_CONFIG_BYTE
189 * Arguments: %eax address to read from (includes bus, device, function, &offset)
191 * Results: %al Byte read
193 * Trashed: %eax, %edx
194 * Effects: reads a single byte from pci config space
196 * Notes: This routine is optimized for minimal register usage.
198 * What it does is almost simple.
199 * It preserves %eax (baring special bits) until it is written
200 * out to the appropriate port. And hides the least significant
201 * bits of the address in the high half of edx.
203 * In %edx[2] it stores the lower three bits of the address.
207 #define PCI_READ_CONFIG_BYTE \
212 orl $0x80000000, %eax ; \
213 andl $0xfffffffc, %eax ; \
218 addl $0xcfc, %edx ; \
224 * Macro: PCI_READ_CONFIG_WORD
225 * Arguments: %eax address to read from (includes bus, device, function, &offset)
227 * Results: %ax word read
229 * Trashed: %eax, %edx
230 * Effects: reads a 2 bytes from pci config space
232 * Notes: This routine is optimized for minimal register usage.
234 * What it does is almost simple.
235 * It preserves %eax (baring special bits) until it is written
236 * out to the appropriate port. And hides the least significant
237 * bits of the address in the high half of edx.
239 * In %edx[2] it stores the lower three bits of the address.
243 #define PCI_READ_CONFIG_WORD \
248 orl $0x80000000, %eax ; \
249 andl $0xfffffffc, %eax ; \
254 addl $0xcfc, %edx ; \
260 * Macro: PCI_READ_CONFIG_DWORD
261 * Arguments: %eax address to read from (includes bus, device, function, &offset)
266 * Effects: reads 4 bytes from pci config space
268 * Notes: This routine is optimized for minimal register usage.
270 * What it does is almost simple.
271 * It preserves %eax (baring special bits) until it is written
272 * out to the appropriate port. And hides the least significant
273 * bits of the address in the high half of edx.
275 * In %edx[2] it stores the lower three bits of the address.
279 #define PCI_READ_CONFIG_DWORD \
284 orl $0x80000000, %eax ; \
285 andl $0xfffffffc, %eax ; \
290 addl $0xcfc, %edx ; \
296 #define CS_READ(which) \
297 mov $0x80000000,%eax ; \
299 and $0xfc,%al /* clear bits 1-0 */ ; \
300 mov $0xcf8,%dx /* port 0xcf8 ?*/ ; \
301 outl %eax,%dx /* open up CS config */ ; \
302 add $0x4,%dl /* 0xcfc data port 0 */ ; \
304 and $0x3,%al /* only bits 1-0 */ ; \
306 inb %dx,%al /* read */ ; \
309 #define CS_WRITE(which, data) \
310 mov $0x80000000,%eax /* 32bit word with bit 31 set */ ; \
311 mov which,%ax /* put the reg# in the low part */ ; \
312 and $0xfc,%al /* dword align the reg# */ ; \
313 mov $0xcf8,%dx /* enable port */ ; \
315 add $0x4,%dl /* 1st data port */ ; \
316 mov which,%ax /* register# */ ; \
320 outb %al,%dx /* write to reg */
322 #define REGBIS(which, bis) \
328 #define REGBIC(which, bic) \
336 /* macro to BIC and BIS a reg. calls read a reg,
337 * does a BIC and then a BIS on it.
338 * to clear no bits, make BIC 0.
339 * to set no bits, make BIS 0
341 #define REGBICBIS(which, bic, bis) \
356 /* originally this macro was from STPC BIOS */
357 #define intel_chip_post_macro(value) \
361 #define INTEL_PDATA_MAGIC 0xdeadbeef
363 /* SLOW_DOWN_IO is a delay we can use that is roughly cpu neutral,
364 * and can be used before memory or timer chips come up.
365 * Since this hits the isa bus it's roughly
367 #define SLOW_DOWN_IO inb $0x80, %al
369 #endif /* ROM_INTEL_H */