Remove fallback/normal handling in mainboards'
[coreboot.git] / src / arch / i386 / Makefile.inc
1 #######################################################################
2 # Take care of subdirectories
3 subdirs-y += boot
4 # subdirs-y += init
5 subdirs-y += lib
6 subdirs-y += smp
7
8 obj-$(CONFIG_HAVE_OPTION_TABLE) += ../../option_table.o
9
10 ifdef POST_EVALUATION
11
12 #######################################################################
13 # Build the final rom image
14 COREBOOT_ROM_DEPENDENCIES:=
15 ifneq ($(CONFIG_PAYLOAD_NONE),y)
16 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_FALLBACK_PAYLOAD_FILE)
17 endif
18 ifeq ($(CONFIG_VGA_BIOS),y)
19 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_FALLBACK_VGA_BIOS_FILE)
20 endif
21 ifeq ($(CONFIG_INTEL_MBI),y)
22 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_FALLBACK_MBI_FILE)
23 endif
24 ifeq ($(CONFIG_BOOTSPLASH),y)
25 COREBOOT_ROM_DEPENDENCIES+=$(CONFIG_FALLBACK_BOOTSPLASH_FILE)
26 endif
27 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES))
28         cp $(obj)/coreboot.pre $@.tmp
29         if [ -f fallback/coreboot_apc ]; \
30         then \
31                 $(CBFSTOOL) $@.tmp add-stage fallback/coreboot_apc $(CONFIG_CBFS_PREFIX)/coreboot_apc $(CBFS_COMPRESS_FLAG); \
32         fi
33         $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG)
34 ifeq ($(CONFIG_PAYLOAD_NONE),y)
35         printf "    PAYLOAD    none (as specified by user)\n"
36 else
37         printf "    PAYLOAD    $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n"
38         $(CBFSTOOL) $@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
39 endif
40 ifeq ($(CONFIG_VGA_BIOS),y)
41         printf "    VGABIOS    $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n"
42         $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_VGA_BIOS_FILE) "pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom" optionrom
43 endif
44 ifeq ($(CONFIG_INTEL_MBI),y)
45         printf "    MBI        $(CONFIG_FALLBACK_MBI_FILE)\n"
46         $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_MBI_FILE) mbi.bin mbi
47 endif
48 ifeq ($(CONFIG_BOOTSPLASH),y)
49         printf "    BOOTSPLASH $(CONFIG_FALLBACK_BOOTSPLASH_FILE)\n"
50         $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_BOOTSPLASH_FILE) bootsplash.jpg bootsplash
51 endif
52         mv $@.tmp $@
53         printf "    CBFSPRINT  $(subst $(obj)/,,$(@))\n\n"
54         $(CBFSTOOL) $@ print
55
56 #######################################################################
57 # i386 specific tools
58
59 $(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
60         @printf "    OPTION     $(subst $(obj)/,,$(@))\n"
61         $(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
62
63 $(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h $(obj)/config.h
64         @printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
65         $(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
66
67 #######################################################################
68 # Build the coreboot_ram (stage 2)
69
70 $(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/i386/coreboot_ram.ld #ldoptions
71         @printf "    CC         $(subst $(obj)/,,$(@))\n"
72         $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o
73         $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
74
75 $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
76         @printf "    CC         $(subst $(obj)/,,$(@))\n"
77         $(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,--start-group $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,--end-group
78
79 $(obj)/coreboot.a: $(objs)
80         @printf "    AR         $(subst $(obj)/,,$(@))\n"
81         rm -f $(obj)/coreboot.a
82         $(AR) cr $(obj)/coreboot.a $(objs)
83
84 #######################################################################
85 # done
86
87 crt0s :=
88 ldscripts :=
89 ldscripts += $(src)/arch/i386/init/ldscript_fallback_cbfs.lb
90 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
91 crt0s += $(src)/cpu/x86/16bit/entry16.inc
92 ldscripts += $(src)/cpu/x86/16bit/entry16.lds
93 endif
94 crt0s += $(src)/cpu/x86/32bit/entry32.inc
95 ldscripts += $(src)/cpu/x86/32bit/entry32.lds
96 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
97 crt0s += $(src)/cpu/x86/16bit/reset16.inc
98 ldscripts += $(src)/cpu/x86/16bit/reset16.lds
99 ifeq ($(CONFIG_ROMCC),y)
100 crt0s += $(src)/arch/i386/lib/cpu_reset.inc
101 endif
102 crt0s += $(src)/arch/i386/lib/id.inc
103 ldscripts += $(src)/arch/i386/lib/id.lds
104 endif
105
106 crt0s += $(src)/cpu/x86/fpu_enable.inc
107 ifeq ($(CONFIG_CPU_AMD_GX1),y)
108 crt0s += $(src)/cpu/amd/model_gx1/cpu_setup.inc
109 crt0s += $(src)/cpu/amd/model_gx1/gx_setup.inc
110 endif
111 ifeq ($(CONFIG_SSE),y)
112 crt0s += $(src)/cpu/x86/sse_enable.inc
113 endif
114
115 ifeq ($(CONFIG_CPU_AMD_LX),y)
116 crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
117 endif
118 ifeq ($(CONFIG_CPU_AMD_SOCKET_F),y)
119 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
120 endif
121 ifeq ($(CONFIG_CPU_AMD_SOCKET_F_1207),y)
122 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
123 endif
124 ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2R2),y)
125 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
126 endif
127 ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2),y)
128 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
129 endif
130 ifeq ($(CONFIG_CPU_AMD_SOCKET_S1G1),y)
131 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
132 endif
133 ifeq ($(CONFIG_CPU_AMD_SOCKET_754),y)
134 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
135 endif
136 ifeq ($(CONFIG_CPU_AMD_SOCKET_939),y)
137 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
138 endif
139 ifeq ($(CONFIG_CPU_AMD_SOCKET_940),y)
140 crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
141 endif
142 ifeq ($(CONFIG_CPU_INTEL_CORE),y)
143 crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
144 endif
145 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
146 ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y)
147 crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
148 endif
149 # should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet
150 ifeq ($(CONFIG_BOARD_VIA_VT8454C),y)
151 crt0s += $(src)/cpu/via/car/cache_as_ram.inc
152 endif
153 ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y)
154 crt0s += $(src)/cpu/via/car/cache_as_ram.inc
155 endif
156 # who else could use this?
157 ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
158 crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
159 ldscripts += $(src)/cpu/x86/car/cache_as_ram.lds
160 endif
161
162 ifeq ($(CONFIG_LLSHELL),y)
163 crt0s += $(src)/arch/i386/llshell/llshell.inc
164 endif
165
166 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
167
168 ifeq ($(CONFIG_SSE),y)
169 crt0s += $(src)/cpu/x86/sse_disable.inc
170 endif
171 ifeq ($(CONFIG_MMX),y)
172 crt0s += $(src)/cpu/x86/mmx_disable.inc
173 endif
174
175 ifeq ($(CONFIG_AP_CODE_IN_CAR),y)
176 ldscripts += $(src)/arch/i386/init/ldscript_apc.lb
177 endif
178
179 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
180 crt0s += $(chipset_bootblock_inc)
181 ldscripts += $(chipset_bootblock_lds)
182 endif
183
184 OPTION_TABLE_H:=
185 ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
186 OPTION_TABLE_H:=$(obj)/option_table.h
187 endif
188
189 ifeq ($(CONFIG_ROMCC),y)
190 ROMCCFLAGS ?= -mcpu=p2 -O2
191
192 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
193         printf "    ROMCC      romstage.inc\n"
194         $(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@
195
196 else
197
198 $(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
199         $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
200
201 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
202         printf "    GEN        romstage.inc\n"
203         $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -include $(obj)/build.h -I$(src) -I. -c -S $< -o $@.tmp1
204         sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $@.tmp1 > $@.tmp
205         mv $@.tmp $@
206         rm -f $@.tmp1
207 endif
208
209 else
210 # Only in first pass
211
212 # Things that appear in every board
213 initobjs += $(obj)/mainboard/$(MAINBOARDDIR)/crt0.o
214 objs += $(obj)/mainboard/$(MAINBOARDDIR)/mainboard.o
215 ifeq ($(CONFIG_GENERATE_MP_TABLE),y)
216 objs += $(obj)/mainboard/$(MAINBOARDDIR)/mptable.o
217 endif
218 ifeq ($(CONFIG_GENERATE_PIRQ_TABLE),y)
219 objs += $(obj)/mainboard/$(MAINBOARDDIR)/irq_tables.o
220 endif
221 ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y)
222 objs += $(obj)/mainboard/$(MAINBOARDDIR)/reset.o
223 endif
224 ifeq ($(CONFIG_GENERATE_ACPI_TABLES),y)
225 objs += $(obj)/mainboard/$(MAINBOARDDIR)/acpi_tables.o
226 objs += $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o
227 # make doesn't have arithmetic operators or greater-than comparisons
228 ifeq ($(subst 5,4,$(CONFIG_ACPI_SSDTX_NUM)),4)
229 objs += $(obj)/mainboard/$(MAINBOARDDIR)/ssdt2.o
230 objs += $(obj)/mainboard/$(MAINBOARDDIR)/ssdt3.o
231 objs += $(obj)/mainboard/$(MAINBOARDDIR)/ssdt4.o
232 endif
233 ifeq ($(CONFIG_ACPI_SSDTX_NUM),5)
234 objs += $(obj)/mainboard/$(MAINBOARDDIR)/ssdt5.o
235 endif
236 ifeq ($(CONFIG_BOARD_HAS_FADT),y)
237 objs += $(obj)/mainboard/$(MAINBOARDDIR)/fadt.o
238 endif
239 endif
240
241 ifeq ($(CONFIG_HAVE_BUS_CONFIG),y)
242 objs += $(obj)/mainboard/$(MAINBOARDDIR)/get_bus_conf.o
243 endif
244
245 endif
246
247 ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
248 include $(src)/arch/i386/Makefile.bootblock.inc
249 else
250 include $(src)/arch/i386/Makefile.bigbootblock.inc
251 endif