2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
15 do_calc : in std_logic;
16 calc_done : out std_logic
17 -- TODO: hier debug ports hinzufuegen ;)
21 architecture beh of alu is
22 type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE, SDONE);
23 signal state_int, state_next : ALU_STATE;
24 signal done_intern, div_calc_done, div_go_calc : std_logic;
25 signal op3_int, op3_next : csigned;
26 signal calc_done_int, calc_done_next : std_logic;
27 -- signale fuer division
28 signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : natural;
29 signal quo_int, quo_next, aktdiv, aktdiv_next, op1_int, op1_next, op2_int, op2_next : csigned;
30 signal sign_int, sign_next : std_logic;
33 calc_done <= calc_done_int;
36 process(sys_clk, sys_res_n)
38 if sys_res_n = '0' then
40 op3_int <= (others => '0');
43 dividend_msb_int <= 0;
45 quo_int <= (others => '0');
46 aktdiv <= (others => '0');
47 op1_int <= (others => '0');
48 op2_int <= (others => '0');
50 elsif rising_edge(sys_clk) then
51 state_int <= state_next;
53 calc_done_int <= calc_done_next;
55 dividend_msb_int <= dividend_msb_next;
56 laengediv_int <= laengediv_next;
58 aktdiv <= aktdiv_next;
61 sign_int <= sign_next;
66 process(state_int, opcode, done_intern, do_calc, div_calc_done, div_go_calc)
68 -- set a default value for next state
69 state_next <= state_int;
70 -- next state berechnen
88 if done_intern = '1' then
92 if done_intern = '1' then
96 if done_intern = '1' then
100 if div_go_calc = '1' then
101 state_next <= SDIV_CALC;
104 if div_calc_done = '1' then
105 state_next <= SDIV_DONE;
108 if done_intern = '1' then
112 if do_calc = '0' then
119 process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int, aktdiv, sign_int, op1_int, op2_int)
120 variable tmperg : csigned;
121 variable multmp : signed(((2*CBITS)-1) downto 0);
123 variable laengediv_var, dividend_msb_var : natural;
124 variable aktdiv_var, quo_var, op1_var, op2_var : csigned;
126 op3_next <= (others => '0');
127 calc_done_next <= '0';
128 div_calc_done <= '0';
132 dividend_msb_next <= 0;
134 quo_next <= (others => '0');
135 aktdiv_next <= (others => '0');
136 op1_next <= (others => '0');
137 op2_next <= (others => '0');
142 tmperg := (others => '0');
151 tmperg(CBITS-1) := multmp((2*CBITS)-1);
152 tmperg((CBITS-2) downto 0) := multmp((CBITS-2) downto 0);
155 -- division implementiert nach ~hwmod/doc/division.pdf
156 tmperg := (others => '0');
157 if op2 = to_signed(0,CBITS) then
158 -- TODO: err out signal
164 if op1(CBITS-1) = '1' then
165 op1_var := not (op1_var + 1);
167 if op2(CBITS-1) = '1' then
168 op2_var := not (op2_var + 1);
171 dividend_msb_var := find_msb(op1_var)-1;
172 laengediv_var := find_msb(op2_var)-1;
174 aktdiv_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
177 dividend_msb_next <= dividend_msb_var;
178 laengediv_next <= laengediv_var;
179 quo_next <= (others => '0');
182 sign_next <= op1(CBITS-1) xor op2(CBITS-1);
185 tmperg := (others => '0');
187 if (dividend_msb_int - laengediv_int + 1) > 0 then
188 aktdiv_var := aktdiv sll 1;
189 aktdiv_var(0) := op1_int(dividend_msb_int - laengediv_int);
191 quo_var := quo_int sll 1;
192 if aktdiv_var >= op2_int then
194 aktdiv_var := aktdiv_var - op2_int;
198 aktdiv_next <= aktdiv_var;
199 dividend_msb_next <= dividend_msb_int;
200 laengediv_next <= laengediv_int + 1;
203 sign_next <= sign_int;
205 if sign_int = '1' then
206 quo_next <= (not quo_int) + 1;
210 div_calc_done <= '1';
217 calc_done_next <= '1';
219 tmperg := (others => '0');
222 end architecture beh;