2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
15 do_calc : in std_logic;
16 calc_done : out std_logic
20 architecture beh of alu is
21 type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDONE);
22 signal state, state_next : ALU_STATE;
23 signal done_intern : std_logic;
26 process(sys_clk, sys_res_n)
28 if sys_res_n = '0' then
30 elsif rising_edge(sys_clk) then
36 process(state, opcode, done_intern, do_calc)
38 -- set a default value for next state
40 -- next state berechnen
58 if done_intern = '1' then
62 if done_intern = '1' then
66 if done_intern = '1' then
70 if done_intern = '1' then
82 variable tmperg : csigned;
83 variable multmp : signed(((2*CBITS)-1) downto 0);
85 op3 <= (others => '0');
99 tmperg(CBITS-1) := multmp((2*CBITS)-1);
100 tmperg((CBITS-2) downto 0) := multmp((CBITS-2) downto 0);
111 end architecture beh;