2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 sys_clk : in std_logic;
10 sys_res_n : in std_logic;
16 do_calc : in std_logic;
17 calc_done : out std_logic;
18 calc_error : out std_logic
22 architecture beh of alu is
23 type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE,
25 signal state_int, state_next : ALU_STATE;
26 signal done_intern, error_intern : std_logic;
27 signal div_calc_done_int : std_logic;
28 signal div_calc_done2_int : std_logic;
29 signal div_go_calc_int : std_logic;
30 signal op3_int, op3_next, opM_int, opM_next : csigned;
31 signal calc_done_int, calc_done_next : std_logic;
32 signal calc_error_int, calc_error_next : std_logic;
33 -- signale fuer division
34 signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : divinteger;
35 signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
36 signal sign_int, sign_next : std_logic;
40 calc_done <= calc_done_int;
41 calc_error <= calc_error_int;
44 process(sys_clk, sys_res_n)
46 if sys_res_n = '0' then
48 op3_int <= (others => '0');
49 opM_int <= (others => '0');
51 calc_error_int <= '0';
53 dividend_msb_int <= 0;
55 quo_int <= (others => '0');
56 aktdiv_int <= (others => '0');
57 op1_int <= (others => '0');
58 op2_int <= (others => '0');
60 elsif rising_edge(sys_clk) then
61 state_int <= state_next;
64 calc_done_int <= calc_done_next;
65 calc_error_int <= calc_error_next;
67 dividend_msb_int <= dividend_msb_next;
68 laengediv_int <= laengediv_next;
70 aktdiv_int <= aktdiv_int_next;
73 sign_int <= sign_next;
78 process(state_int, opcode, done_intern, error_intern, do_calc,
79 div_calc_done_int, div_calc_done2_int, div_go_calc_int)
81 -- set a default value for next state
82 state_next <= state_int;
83 -- next state berechnen
100 when SADD | SSUB | SMUL | SDIV_DONE =>
101 if done_intern = '1' then
104 if error_intern = '1' then
105 state_next <= SERROR;
108 if div_go_calc_int = '1' then
109 state_next <= SDIV_CALC;
111 if div_calc_done2_int = '1' then
112 state_next <= SDIV_DONE;
114 if error_intern = '1' then
115 state_next <= SERROR;
118 if div_calc_done_int = '1' then
119 state_next <= SDIV_DONE;
121 when SDONE | SERROR =>
122 if do_calc = '0' then
129 process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int,
130 aktdiv_int, sign_int, op1_int, op2_int, op3_int, opM_int)
131 variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
132 variable mulsign : std_logic;
133 variable tmp : csigned;
135 variable laengediv_var, dividend_msb_var, divtmp : divinteger;
136 variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
138 calc_done_next <= '0';
139 calc_error_next <= '0';
140 div_calc_done_int <= '0';
141 div_calc_done2_int <= '0';
142 div_go_calc_int <= '0';
146 dividend_msb_next <= 0;
148 quo_next <= (others => '0');
149 aktdiv_int_next <= aktdiv_int;
150 op1_next <= (others => '0');
151 op2_next <= (others => '0');
158 opM_next <= (others => '0');
159 aktdiv_int_next <= (others => '0');
164 -- over- bzw. underflow?
165 if (op1(CBITS-1) = op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
174 -- over- bzw. underflow?
175 if (op1(CBITS-1) /= op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
181 mulsign := op1(CBITS-1) xor op2(CBITS-1);
183 op3_next((CBITS-2) downto 0) <= multmp((CBITS-2) downto 0);
184 op3_next(CBITS-1) <= mulsign;
186 if mulsign = '1' then
187 multmp2 := (not multmp) + 1;
192 if(multmp2((2*CBITS)-2 downto (CBITS-1)) > 0) then
199 -- division implementiert nach ~hwmod/doc/division.pdf
200 if ((op1 = x"80000000" and op2 = to_signed(-1, CBITS)) or op2 = to_signed(0, CBITS)) then
206 if op1(CBITS-1) = '1' then
207 op1_var := (not op1_var) + 1;
209 if op2(CBITS-1) = '1' then
210 op2_var := (not op2_var) + 1;
213 dividend_msb_var := find_msb(op1_var)-1;
214 laengediv_var := find_msb(op2_var)-1;
216 aktdiv_int_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
218 if op1_var < op2_var then
219 div_calc_done2_int <= '1';
220 quo_next <= to_signed(0,CBITS);
221 aktdiv_int_next <= op1_var;
223 div_go_calc_int <= '1';
224 dividend_msb_next <= dividend_msb_var;
225 laengediv_next <= laengediv_var;
226 quo_next <= (others => '0');
229 sign_next <= op1(CBITS-1) xor op2(CBITS-1);
233 divtmp := dividend_msb_int - laengediv_int + 1;
236 aktdiv_int_var := aktdiv_int sll 1;
237 aktdiv_int_var(0) := op1_int(divtmp - 1);
239 quo_var := quo_int sll 1;
240 if aktdiv_int_var >= op2_int then
242 aktdiv_int_var := aktdiv_int_var - op2_int;
246 aktdiv_int_next <= aktdiv_int_var;
247 dividend_msb_next <= dividend_msb_int;
248 laengediv_next <= laengediv_int + 1;
251 sign_next <= sign_int;
253 if sign_int = '1' then
254 quo_next <= (not quo_int) + 1;
258 div_calc_done_int <= '1';
262 opM_next <= aktdiv_int;
264 when SDONE | SERROR =>
265 calc_done_next <= '1';
266 if (state_int = SERROR) then
267 calc_error_next <= '1';
271 end architecture beh;