1 // Low level AHCI disk access
3 // Copyright (C) 2010 Gerd Hoffmann <kraxel@redhat.com>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "types.h" // u8
8 #include "ioport.h" // inb
9 #include "util.h" // dprintf
10 #include "biosvar.h" // GET_EBDA
11 #include "pci.h" // foreachpci
12 #include "pci_ids.h" // PCI_CLASS_STORAGE_OTHER
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
14 #include "boot.h" // add_bcv_hd
15 #include "disk.h" // struct ata_s
16 #include "ata.h" // ATA_CB_STAT
17 #include "ahci.h" // CDB_CMD_READ_10
18 #include "blockcmd.h" // CDB_CMD_READ_10
20 #define AHCI_MAX_RETRIES 5
22 /****************************************************************
23 * these bits must run in both 16bit and 32bit modes
24 ****************************************************************/
26 // prepare sata command fis
27 static void sata_prep_simple(struct sata_cmd_fis *fis, u8 command)
29 memset_fl(fis, 0, sizeof(*fis));
30 SET_FLATPTR(fis->command, command);
33 static void sata_prep_readwrite(struct sata_cmd_fis *fis,
34 struct disk_op_s *op, int iswrite)
39 memset_fl(fis, 0, sizeof(*fis));
41 if (op->count >= (1<<8) || lba + op->count >= (1<<28)) {
42 SET_FLATPTR(fis->sector_count2, op->count >> 8);
43 SET_FLATPTR(fis->lba_low2, lba >> 24);
44 SET_FLATPTR(fis->lba_mid2, lba >> 32);
45 SET_FLATPTR(fis->lba_high2, lba >> 40);
47 command = (iswrite ? ATA_CMD_WRITE_DMA_EXT
48 : ATA_CMD_READ_DMA_EXT);
50 command = (iswrite ? ATA_CMD_WRITE_DMA
53 SET_FLATPTR(fis->feature, 1); /* dma */
54 SET_FLATPTR(fis->command, command);
55 SET_FLATPTR(fis->sector_count, op->count);
56 SET_FLATPTR(fis->lba_low, lba);
57 SET_FLATPTR(fis->lba_mid, lba >> 8);
58 SET_FLATPTR(fis->lba_high, lba >> 16);
59 SET_FLATPTR(fis->device, ((lba >> 24) & 0xf) | ATA_CB_DH_LBA);
62 static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
64 memset_fl(fis, 0, sizeof(*fis));
65 SET_FLATPTR(fis->command, ATA_CMD_PACKET);
66 SET_FLATPTR(fis->feature, 1); /* dma */
67 SET_FLATPTR(fis->lba_mid, blocksize);
68 SET_FLATPTR(fis->lba_high, blocksize >> 8);
71 // ahci register access helpers
72 static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
74 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
75 return pci_readl(addr);
78 static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
80 u32 addr = GET_GLOBALFLAT(ctrl->iobase) + reg;
81 pci_writel(addr, val);
84 static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
87 ctrl_reg += pnr * 0x80;
92 static u32 ahci_port_readl(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg)
94 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
95 return ahci_ctrl_readl(ctrl, ctrl_reg);
98 static void ahci_port_writel(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg, u32 val)
100 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
101 ahci_ctrl_writel(ctrl, ctrl_reg, val);
104 // submit ahci command + wait for result
105 static int ahci_command(struct ahci_port_s *port, int iswrite, int isatapi,
106 void *buffer, u32 bsize)
108 u32 val, status, success, flags;
109 struct ahci_ctrl_s *ctrl = GET_GLOBAL(port->ctrl);
110 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
111 struct ahci_fis_s *fis = GET_GLOBAL(port->fis);
112 struct ahci_list_s *list = GET_GLOBAL(port->list);
113 u32 pnr = GET_GLOBAL(port->pnr);
115 SET_FLATPTR(cmd->fis.reg, 0x27);
116 SET_FLATPTR(cmd->fis.pmp_type, (1 << 7)); /* cmd fis */
117 SET_FLATPTR(cmd->prdt[0].base, ((u32)buffer));
118 SET_FLATPTR(cmd->prdt[0].baseu, 0);
119 SET_FLATPTR(cmd->prdt[0].flags, bsize-1);
121 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
122 ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_START);
124 if (ahci_port_readl(ctrl, pnr, PORT_CMD_ISSUE))
127 flags = ((1 << 16) | /* one prd entry */
128 (1 << 10) | /* clear busy on ok */
129 (iswrite ? (1 << 6) : 0) |
130 (isatapi ? (1 << 5) : 0) |
131 (4 << 0)); /* fis length (dwords) */
132 SET_FLATPTR(list[0].flags, flags);
133 SET_FLATPTR(list[0].bytes, bsize);
134 SET_FLATPTR(list[0].base, ((u32)(cmd)));
135 SET_FLATPTR(list[0].baseu, 0);
137 dprintf(2, "AHCI/%d: send cmd ...\n", pnr);
138 SET_FLATPTR(fis->rfis[2], 0);
139 ahci_port_writel(ctrl, pnr, PORT_SCR_ACT, 1);
140 ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1);
141 while (ahci_port_readl(ctrl, pnr, PORT_CMD_ISSUE)) {
144 while ((status = GET_FLATPTR(fis->rfis[2])) == 0) {
148 success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
149 ATA_CB_STAT_DRQ | ATA_CB_STAT_ERR)) &&
150 ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
151 dprintf(2, "AHCI/%d: ... finished, status 0x%x, %s\n", pnr,
152 status, success ? "OK" : "ERROR");
153 return success ? 0 : -1;
156 #define CDROM_CDB_SIZE 12
158 int ahci_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize)
163 struct ahci_port_s *port = container_of(
164 op->drive_g, struct ahci_port_s, drive);
165 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
169 sata_prep_atapi(&cmd->fis, blocksize);
170 for (i = 0; i < CDROM_CDB_SIZE; i++) {
171 SET_FLATPTR(cmd->atapi[i], atapi[i]);
173 rc = ahci_command(port, 0, 1, op->buf_fl,
174 op->count * blocksize);
176 return DISK_RET_EBADTRACK;
177 return DISK_RET_SUCCESS;
180 // read/write count blocks from a harddrive.
182 ahci_disk_readwrite(struct disk_op_s *op, int iswrite)
184 struct ahci_port_s *port = container_of(
185 op->drive_g, struct ahci_port_s, drive);
186 struct ahci_cmd_s *cmd = GET_GLOBAL(port->cmd);
189 sata_prep_readwrite(&cmd->fis, op, iswrite);
190 rc = ahci_command(port, iswrite, 0, op->buf_fl,
191 op->count * DISK_SECTOR_SIZE);
192 dprintf(2, "ahci disk %s, lba %6x, count %3x, buf %p, rc %d\n",
193 iswrite ? "write" : "read", (u32)op->lba, op->count, op->buf_fl, rc);
195 return DISK_RET_EBADTRACK;
196 return DISK_RET_SUCCESS;
200 int process_ahci_op(struct disk_op_s *op)
202 struct ahci_port_s *port;
208 port = container_of(op->drive_g, struct ahci_port_s, drive);
209 atapi = GET_GLOBAL(port->atapi);
212 switch (op->command) {
217 return DISK_RET_EWRITEPROTECT;
219 /* FIXME: what should we do here? */
222 return DISK_RET_SUCCESS;
224 dprintf(1, "AHCI: unknown cdrom command %d\n", op->command);
226 return DISK_RET_EPARAM;
229 switch (op->command) {
231 return ahci_disk_readwrite(op, 0);
233 return ahci_disk_readwrite(op, 1);
235 /* FIXME: what should we do here? */
239 return DISK_RET_SUCCESS;
241 dprintf(1, "AHCI: unknown disk command %d\n", op->command);
243 return DISK_RET_EPARAM;
248 /****************************************************************
249 * everything below is pure 32bit code
250 ****************************************************************/
253 ahci_port_reset(struct ahci_ctrl_s *ctrl, u32 pnr)
257 /* disable FIS + CMD */
258 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
259 while (val & (PORT_CMD_FIS_RX | PORT_CMD_START |
260 PORT_CMD_FIS_ON | PORT_CMD_LIST_ON) &&
261 count < AHCI_MAX_RETRIES) {
262 val &= ~(PORT_CMD_FIS_RX | PORT_CMD_START);
263 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
265 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
270 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
272 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
274 /* disable + clear IRQs */
275 ahci_port_writel(ctrl, pnr, PORT_IRQ_MASK, val);
276 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
278 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
282 ahci_port_probe(struct ahci_ctrl_s *ctrl, u32 pnr)
286 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
287 while (val & ((1 << 7) /* BSY */ |
288 (1 << 3) /* DRQ */)) {
290 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
292 if (count >= AHCI_MAX_RETRIES)
296 val = ahci_port_readl(ctrl, pnr, PORT_SCR_STAT);
297 if ((val & 0x07) != 0x03)
304 static struct ahci_port_s*
305 ahci_port_init(struct ahci_ctrl_s *ctrl, u32 pnr)
307 struct ahci_port_s *port = malloc_fseg(sizeof(*port));
308 char model[MAXMODEL+1];
319 port->list = memalign_low(1024, 1024);
320 port->fis = memalign_low(256, 256);
321 port->cmd = memalign_low(256, 256);
322 if (port->list == NULL || port->fis == NULL || port->cmd == NULL) {
326 memset(port->list, 0, 1024);
327 memset(port->fis, 0, 256);
328 memset(port->cmd, 0, 256);
330 ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list);
331 ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis);
332 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
333 ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_FIS_RX);
335 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE);
336 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
341 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE);
342 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
347 port->drive.type = DTYPE_AHCI;
348 port->drive.removable = (buffer[0] & 0x80) ? 1 : 0;
349 port->drive.desc = malloc_tmp(MAXDESCSIZE);
350 if (!port->drive.desc) {
357 port->drive.blksize = DISK_SECTOR_SIZE;
358 port->drive.pchs.cylinders = buffer[1];
359 port->drive.pchs.heads = buffer[3];
360 port->drive.pchs.spt = buffer[6];
363 if (buffer[83] & (1 << 10)) // word 83 - lba48 support
364 sectors = *(u64*)&buffer[100]; // word 100-103
366 sectors = *(u32*)&buffer[60]; // word 60 and word 61
367 port->drive.sectors = sectors;
368 u64 adjsize = sectors >> 11;
369 char adjprefix = 'M';
370 if (adjsize >= (1 << 16)) {
374 snprintf(port->drive.desc, MAXDESCSIZE
375 , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)"
377 , ata_extract_model(model, MAXMODEL, buffer)
378 , ata_extract_version(buffer)
379 , (u32)adjsize, adjprefix);
381 // Setup disk geometry translation.
382 setup_translation(&port->drive);
383 // Register with bcv system.
384 add_bcv_internal(&port->drive);
386 // found cdrom (atapi)
387 port->drive.blksize = CDROM_SECTOR_SIZE;
388 port->drive.sectors = (u64)-1;
389 u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05;
390 snprintf(port->drive.desc, MAXDESCSIZE, "AHCI/%d: %s ATAPI-%d %s"
392 , ata_extract_model(model, MAXMODEL, buffer)
393 , ata_extract_version(buffer)
394 , (iscd ? "DVD/CD" : "Device"));
398 map_cd_drive(&port->drive);
400 dprintf(1, "%s\n", port->drive.desc);
405 dprintf(1, "AHCI/%d: init failure, reset\n", port->pnr);
406 ahci_port_reset(ctrl, pnr);
410 // Detect any drives attached to a given controller.
412 ahci_detect(void *data)
414 struct ahci_ctrl_s *ctrl = data;
415 struct ahci_port_s *port;
419 max = ctrl->caps & 0x1f;
420 for (pnr = 0; pnr < max; pnr++) {
421 if (!(ctrl->ports & (1 << pnr)))
423 dprintf(2, "AHCI/%d: probing\n", pnr);
424 ahci_port_reset(ctrl, pnr);
425 rc = ahci_port_probe(ctrl, pnr);
426 dprintf(1, "AHCI/%d: link %s\n", pnr, rc == 0 ? "up" : "down");
429 port = ahci_port_init(ctrl, pnr);
433 // Initialize an ata controller and detect its drives.
435 ahci_init_controller(int bdf)
437 struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
445 ctrl->iobase = pci_config_readl(bdf, PCI_BASE_ADDRESS_5);
446 ctrl->irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
447 dprintf(1, "AHCI controller at %02x.%x, iobase %x, irq %d\n",
448 bdf >> 3, bdf & 7, ctrl->iobase, ctrl->irq);
450 val = ahci_ctrl_readl(ctrl, HOST_CTL);
451 ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
453 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
454 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
455 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
456 ctrl->caps, ctrl->ports);
458 run_thread(ahci_detect, ctrl);
461 // Locate and init ahci controllers.
465 // Scan PCI bus for ATA adapters
467 foreachpci(bdf, max) {
468 if (pci_config_readw(bdf, PCI_CLASS_DEVICE) != PCI_CLASS_STORAGE_SATA)
470 if (pci_config_readb(bdf, PCI_CLASS_PROG) != 1 /* AHCI rev 1 */)
472 ahci_init_controller(bdf);
483 dprintf(3, "init ahci\n");