1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "memmap.h" // malloc_fseg
11 #include "pci.h" // pci_find_device
12 #include "biosvar.h" // GET_EBDA
13 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
14 #include "pci_regs.h" // PCI_INTERRUPT_LINE
17 /****************************************************/
18 /* ACPI tables init */
20 /* Table structure from Linux kernel (the ACPI tables are under the
23 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
24 u32 signature; /* ACPI signature (4 ASCII characters) */ \
25 u32 length; /* Length of table, in bytes, including header */ \
26 u8 revision; /* ACPI Specification minor version # */ \
27 u8 checksum; /* To make sum of entire table == 0 */ \
28 u8 oem_id [6]; /* OEM identification */ \
29 u8 oem_table_id [8]; /* OEM table identification */ \
30 u32 oem_revision; /* OEM revision number */ \
31 u8 asl_compiler_id [4]; /* ASL compiler vendor ID */ \
32 u32 asl_compiler_revision; /* ASL compiler revision number */
35 struct acpi_table_header /* ACPI common table header */
41 * ACPI 1.0 Root System Description Table (RSDT)
43 #define RSDT_SIGNATURE 0x54445352 // RSDT
44 struct rsdt_descriptor_rev1
46 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
47 u32 table_offset_entry[3]; /* Array of pointers to other */
52 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
54 #define FACS_SIGNATURE 0x53434146 // FACS
55 struct facs_descriptor_rev1
57 u32 signature; /* ACPI Signature */
58 u32 length; /* Length of structure, in bytes */
59 u32 hardware_signature; /* Hardware configuration signature */
60 u32 firmware_waking_vector; /* ACPI OS waking vector */
61 u32 global_lock; /* Global Lock */
62 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
63 u32 reserved1 : 31; /* Must be 0 */
64 u8 resverved3 [40]; /* Reserved - must be zero */
69 * ACPI 1.0 Fixed ACPI Description Table (FADT)
71 #define FACP_SIGNATURE 0x50434146 // FACP
72 struct fadt_descriptor_rev1
74 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
75 u32 firmware_ctrl; /* Physical address of FACS */
76 u32 dsdt; /* Physical address of DSDT */
77 u8 model; /* System Interrupt Model */
78 u8 reserved1; /* Reserved */
79 u16 sci_int; /* System vector of SCI interrupt */
80 u32 smi_cmd; /* Port address of SMI command port */
81 u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
82 u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
83 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
84 u8 reserved2; /* Reserved - must be zero */
85 u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
86 u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
87 u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
88 u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
89 u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
90 u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
91 u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
92 u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
93 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
94 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
95 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
96 u8 pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
97 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
98 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
99 u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
100 u8 reserved3; /* Reserved */
101 u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
102 u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
103 u16 flush_size; /* Size of area read to flush caches */
104 u16 flush_stride; /* Stride used in flushing caches */
105 u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
106 u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
107 u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
108 u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
109 u8 century; /* Index to century in RTC CMOS RAM */
110 u8 reserved4; /* Reserved */
111 u8 reserved4a; /* Reserved */
112 u8 reserved4b; /* Reserved */
114 u32 wb_invd : 1; /* The wbinvd instruction works properly */
115 u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
116 u32 proc_c1 : 1; /* All processors support C1 state */
117 u32 plvl2_up : 1; /* C2 state works on MP system */
118 u32 pwr_button : 1; /* Power button is handled as a generic feature */
119 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
120 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
121 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
122 u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
123 u32 reserved5 : 23; /* Reserved - must be zero */
130 * MADT values and structures
133 /* Values for MADT PCATCompat */
136 #define MULTIPLE_APIC 1
141 #define APIC_SIGNATURE 0x43495041 // APIC
142 struct multiple_apic_table
144 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
145 u32 local_apic_address; /* Physical address of local APIC */
147 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
155 /* Values for Type in APIC_HEADER_DEF */
157 #define APIC_PROCESSOR 0
159 #define APIC_XRUPT_OVERRIDE 2
161 #define APIC_LOCAL_NMI 4
162 #define APIC_ADDRESS_OVERRIDE 5
163 #define APIC_IO_SAPIC 6
164 #define APIC_LOCAL_SAPIC 7
165 #define APIC_XRUPT_SOURCE 8
166 #define APIC_RESERVED 9 /* 9 and greater are reserved */
169 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
171 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
175 /* Sub-structures for MADT */
177 struct madt_processor_apic
180 u8 processor_id; /* ACPI processor id */
181 u8 local_apic_id; /* Processor's local APIC id */
183 u32 processor_enabled: 1; /* Processor is usable if set */
184 u32 reserved2 : 31; /* Reserved, must be zero */
193 u8 io_apic_id; /* I/O APIC ID */
194 u8 reserved; /* Reserved - must be zero */
195 u32 address; /* APIC physical address */
196 u32 interrupt; /* Global system interrupt where INTI
202 #define PCI_ISA_IRQ_MASK 0x0e20
204 #define PCI_ISA_IRQ_MASK 0x0000
207 struct madt_intsrcovr {
215 #include "acpi-dsdt.hex"
217 static inline u16 cpu_to_le16(u16 x)
222 static inline u32 cpu_to_le32(u32 x)
228 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev
229 , struct rsdt_descriptor_rev1 *rsdt)
232 h->length = cpu_to_le32(len);
234 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
235 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
236 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
237 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
238 h->oem_revision = cpu_to_le32(1);
239 h->asl_compiler_revision = cpu_to_le32(1);
240 h->checksum -= checksum(h, len);
245 if (rsdt->length >= sizeof(*rsdt)) {
246 dprintf(1, "No more room for rsdt entry!\n");
249 u32 *p = (void*)rsdt + rsdt->length;
251 rsdt->length += sizeof(*p);
255 build_fadt(struct rsdt_descriptor_rev1 *rsdt, int bdf)
257 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
258 struct facs_descriptor_rev1 *facs = malloc_high(sizeof(*facs) + 63);
259 void *dsdt = malloc_high(sizeof(AmlCode));
261 if (!fadt || !facs || !dsdt) {
262 dprintf(1, "Not enough memory for fadt!\n");
267 facs = (void*)ALIGN((u32)facs, 64);
268 memset(facs, 0, sizeof(*facs));
269 facs->signature = FACS_SIGNATURE;
270 facs->length = cpu_to_le32(sizeof(*facs));
273 memcpy(dsdt, AmlCode, sizeof(AmlCode));
276 memset(fadt, 0, sizeof(*fadt));
277 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
278 fadt->dsdt = cpu_to_le32((u32)dsdt);
281 int pm_sci_int = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
282 fadt->sci_int = cpu_to_le16(pm_sci_int);
283 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
284 fadt->acpi_enable = 0xf1;
285 fadt->acpi_disable = 0xf0;
286 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
287 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
288 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
289 fadt->pm1_evt_len = 4;
290 fadt->pm1_cnt_len = 2;
291 fadt->pm_tmr_len = 4;
292 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
293 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
294 /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
295 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
297 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1, rsdt);
301 build_madt(struct rsdt_descriptor_rev1 *rsdt)
303 int smp_cpus = CountCPUs;
304 int madt_size = (sizeof(struct multiple_apic_table)
305 + sizeof(struct madt_processor_apic) * smp_cpus
306 + sizeof(struct madt_io_apic)
307 + sizeof(struct madt_intsrcovr) * 16);
308 struct multiple_apic_table *madt = malloc_high(madt_size);
310 dprintf(1, "Not enough memory for madt!\n");
313 memset(madt, 0, madt_size);
314 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
315 madt->flags = cpu_to_le32(1);
316 struct madt_processor_apic *apic = (void*)&madt[1];
318 for (i=0; i<smp_cpus; i++) {
319 apic->type = APIC_PROCESSOR;
320 apic->length = sizeof(*apic);
321 apic->processor_id = i;
322 apic->local_apic_id = i;
323 apic->flags = cpu_to_le32(1);
326 struct madt_io_apic *io_apic = (void*)apic;
327 io_apic->type = APIC_IO;
328 io_apic->length = sizeof(*io_apic);
329 io_apic->io_apic_id = smp_cpus;
330 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
331 io_apic->interrupt = cpu_to_le32(0);
333 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
335 memset(intsrcovr, 0, sizeof(*intsrcovr));
336 intsrcovr->type = APIC_XRUPT_OVERRIDE;
337 intsrcovr->length = sizeof(*intsrcovr);
338 intsrcovr->source = 0;
340 intsrcovr->flags = 0; /* conforms to bus specifications */
343 for (i = 1; i < 16; i++) {
344 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
345 /* No need for a INT source override structure. */
347 memset(intsrcovr, 0, sizeof(*intsrcovr));
348 intsrcovr->type = APIC_XRUPT_OVERRIDE;
349 intsrcovr->length = sizeof(*intsrcovr);
350 intsrcovr->source = i;
352 intsrcovr->flags = 0xd; /* active high, level triggered */
356 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt
360 #define SSDT_SIGNATURE 0x54445353 // SSDT
362 build_ssdt(struct rsdt_descriptor_rev1 *rsdt)
364 int smp_cpus = CountCPUs;
365 int acpi_cpus = smp_cpus > 0xff ? 0xff : smp_cpus;
366 // calculate the length of processor block and scope block
367 // excluding PkgLength
368 int cpu_length = 13 * acpi_cpus + 4;
370 int length = sizeof(struct acpi_table_header) + 3 + cpu_length;
371 u8 *ssdt = malloc_high(length);
373 dprintf(1, "No space for ssdt!\n");
378 ssdt_ptr[9] = 0; // checksum;
379 ssdt_ptr += sizeof(struct acpi_table_header);
381 // build processor scope header
382 *(ssdt_ptr++) = 0x10; // ScopeOp
383 if (cpu_length <= 0x3e) {
384 *(ssdt_ptr++) = cpu_length + 1;
386 *(ssdt_ptr++) = 0x7F;
387 *(ssdt_ptr++) = (cpu_length + 2) >> 6;
389 *(ssdt_ptr++) = '_'; // Name
394 // build object for each processor
396 for (i=0; i<acpi_cpus; i++) {
397 *(ssdt_ptr++) = 0x5B; // ProcessorOp
398 *(ssdt_ptr++) = 0x83;
399 *(ssdt_ptr++) = 0x0B; // Length
400 *(ssdt_ptr++) = 'C'; // Name (CPUxx)
403 *(ssdt_ptr++) = (i >> 4) < 0xa ? (i >> 4) + '0' : (i >> 4) + 'A' - 0xa;
406 *(ssdt_ptr++) = (i & 0xf) < 0xa ? (i & 0xf) + '0' : (i & 0xf) + 'A' - 0xa;
408 *(ssdt_ptr++) = 0x10; // Processor block address
409 *(ssdt_ptr++) = 0xb0;
412 *(ssdt_ptr++) = 6; // Processor block length
415 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1, rsdt);
418 struct rsdp_descriptor *RsdpAddr;
426 dprintf(3, "init ACPI tables\n");
428 // This code is hardcoded for PIIX4 Power Management device.
429 int bdf = pci_find_device(PCI_VENDOR_ID_INTEL
430 , PCI_DEVICE_ID_INTEL_82371AB_3);
435 // Create initial rsdt table
436 struct rsdt_descriptor_rev1 *rsdt = malloc_high(sizeof(*rsdt));
438 dprintf(1, "Not enough memory for acpi rsdt table!\n");
441 memset(rsdt, 0, sizeof(*rsdt));
442 rsdt->length = offsetof(struct rsdt_descriptor_rev1, table_offset_entry[0]);
445 build_fadt(rsdt, bdf);
449 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt->length, 1, NULL);
451 // Build rsdp pointer table
452 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
454 dprintf(1, "Not enough memory for acpi rsdp!\n");
457 memset(rsdp, 0, sizeof(*rsdp));
458 rsdp->signature = RSDP_SIGNATURE;
459 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
460 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
461 rsdp->checksum -= checksum(rsdp, 20);
463 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
469 dprintf(4, "rsdp=%p\n", RsdpAddr);
470 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
472 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
473 dprintf(4, "rsdt=%p\n", rsdt);
474 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
476 void *end = (void*)rsdt + rsdt->length;
478 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
479 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
480 if (!fadt || fadt->signature != FACP_SIGNATURE)
482 dprintf(4, "fadt=%p\n", fadt);
483 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
484 dprintf(4, "facs=%p\n", facs);
485 if (! facs || facs->signature != FACS_SIGNATURE)
488 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
489 return facs->firmware_waking_vector;