1 // Support for generating ACPI tables (on emulators)
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "acpi.h" // struct rsdp_descriptor
9 #include "util.h" // memcpy
10 #include "pci.h" // pci_find_init_device
11 #include "biosvar.h" // GET_EBDA
12 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 /****************************************************/
17 /* ACPI tables init */
19 /* Table structure from Linux kernel (the ACPI tables are under the
22 struct acpi_table_header /* ACPI common table header */
28 * ACPI 1.0 Root System Description Table (RSDT)
30 #define RSDT_SIGNATURE 0x54445352 // RSDT
31 struct rsdt_descriptor_rev1
33 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
34 u32 table_offset_entry[0]; /* Array of pointers to other */
39 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
41 #define FACS_SIGNATURE 0x53434146 // FACS
42 struct facs_descriptor_rev1
44 u32 signature; /* ACPI Signature */
45 u32 length; /* Length of structure, in bytes */
46 u32 hardware_signature; /* Hardware configuration signature */
47 u32 firmware_waking_vector; /* ACPI OS waking vector */
48 u32 global_lock; /* Global Lock */
49 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
50 u32 reserved1 : 31; /* Must be 0 */
51 u8 resverved3 [40]; /* Reserved - must be zero */
56 * MADT values and structures
59 /* Values for MADT PCATCompat */
62 #define MULTIPLE_APIC 1
67 #define APIC_SIGNATURE 0x43495041 // APIC
68 struct multiple_apic_table
70 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
71 u32 local_apic_address; /* Physical address of local APIC */
73 u32 PCATcompat : 1; /* A one indicates system also has dual 8259s */
81 /* Values for Type in APIC sub-headers */
83 #define APIC_PROCESSOR 0
85 #define APIC_XRUPT_OVERRIDE 2
87 #define APIC_LOCAL_NMI 4
88 #define APIC_ADDRESS_OVERRIDE 5
89 #define APIC_IO_SAPIC 6
90 #define APIC_LOCAL_SAPIC 7
91 #define APIC_XRUPT_SOURCE 8
92 #define APIC_RESERVED 9 /* 9 and greater are reserved */
95 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
97 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
101 /* Sub-structures for MADT */
103 struct madt_processor_apic
106 u8 processor_id; /* ACPI processor id */
107 u8 local_apic_id; /* Processor's local APIC id */
109 u32 processor_enabled: 1; /* Processor is usable if set */
110 u32 reserved2 : 31; /* Reserved, must be zero */
119 u8 io_apic_id; /* I/O APIC ID */
120 u8 reserved; /* Reserved - must be zero */
121 u32 address; /* APIC physical address */
122 u32 interrupt; /* Global system interrupt where INTI
127 #define PCI_ISA_IRQ_MASK 0x0e20
129 struct madt_intsrcovr {
138 * ACPI 2.0 Generic Address Space definition.
140 struct acpi_20_generic_address {
142 u8 register_bit_width;
143 u8 register_bit_offset;
149 * HPET Description Table
151 struct acpi_20_hpet {
152 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
154 struct acpi_20_generic_address addr;
160 #define HPET_ID 0x000
161 #define HPET_PERIOD 0x004
164 * SRAT (NUMA topology description) table
167 #define SRAT_PROCESSOR 0
168 #define SRAT_MEMORY 1
170 struct system_resource_affinity_table
172 ACPI_TABLE_HEADER_DEF
177 struct srat_processor_affinity
188 struct srat_memory_affinity
193 u32 base_addr_low,base_addr_high;
194 u32 length_low,length_high;
200 #include "acpi-dsdt.hex"
203 build_header(struct acpi_table_header *h, u32 sig, int len, u8 rev)
206 h->length = cpu_to_le32(len);
208 memcpy(h->oem_id, CONFIG_APPNAME6, 6);
209 memcpy(h->oem_table_id, CONFIG_APPNAME4, 4);
210 memcpy(h->oem_table_id + 4, (void*)&sig, 4);
211 h->oem_revision = cpu_to_le32(1);
212 memcpy(h->asl_compiler_id, CONFIG_APPNAME4, 4);
213 h->asl_compiler_revision = cpu_to_le32(1);
214 h->checksum -= checksum(h, len);
217 #define PIIX4_ACPI_ENABLE 0xf1
218 #define PIIX4_ACPI_DISABLE 0xf0
219 #define PIIX4_GPE0_BLK 0xafe0
220 #define PIIX4_GPE0_BLK_LEN 4
222 static void piix4_fadt_init(struct pci_device *pci, void *arg)
224 struct fadt_descriptor_rev1 *fadt = arg;
225 fadt->acpi_enable = PIIX4_ACPI_ENABLE;
226 fadt->acpi_disable = PIIX4_ACPI_DISABLE;
227 fadt->gpe0_blk = cpu_to_le32(PIIX4_GPE0_BLK);
228 fadt->gpe0_blk_len = PIIX4_GPE0_BLK_LEN;
231 static const struct pci_device_id fadt_init_tbl[] = {
232 /* PIIX4 Power Management device (for ACPI) */
233 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
240 build_fadt(struct pci_device *pci)
242 struct fadt_descriptor_rev1 *fadt = malloc_high(sizeof(*fadt));
243 struct facs_descriptor_rev1 *facs = memalign_high(64, sizeof(*facs));
244 void *dsdt = malloc_high(sizeof(AmlCode));
246 if (!fadt || !facs || !dsdt) {
252 memset(facs, 0, sizeof(*facs));
253 facs->signature = FACS_SIGNATURE;
254 facs->length = cpu_to_le32(sizeof(*facs));
257 memcpy(dsdt, AmlCode, sizeof(AmlCode));
260 memset(fadt, 0, sizeof(*fadt));
261 fadt->firmware_ctrl = cpu_to_le32((u32)facs);
262 fadt->dsdt = cpu_to_le32((u32)dsdt);
265 int pm_sci_int = pci_config_readb(pci->bdf, PCI_INTERRUPT_LINE);
266 fadt->sci_int = cpu_to_le16(pm_sci_int);
267 fadt->smi_cmd = cpu_to_le32(PORT_SMI_CMD);
268 fadt->pm1a_evt_blk = cpu_to_le32(PORT_ACPI_PM_BASE);
269 fadt->pm1a_cnt_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x04);
270 fadt->pm_tmr_blk = cpu_to_le32(PORT_ACPI_PM_BASE + 0x08);
271 fadt->pm1_evt_len = 4;
272 fadt->pm1_cnt_len = 2;
273 fadt->pm_tmr_len = 4;
274 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
275 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
276 pci_init_device(fadt_init_tbl, pci, fadt);
277 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
278 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) | (1 << 7));
280 build_header((void*)fadt, FACP_SIGNATURE, sizeof(*fadt), 1);
288 int madt_size = (sizeof(struct multiple_apic_table)
289 + sizeof(struct madt_processor_apic) * MaxCountCPUs
290 + sizeof(struct madt_io_apic)
291 + sizeof(struct madt_intsrcovr) * 16);
292 struct multiple_apic_table *madt = malloc_high(madt_size);
297 memset(madt, 0, madt_size);
298 madt->local_apic_address = cpu_to_le32(BUILD_APIC_ADDR);
299 madt->flags = cpu_to_le32(1);
300 struct madt_processor_apic *apic = (void*)&madt[1];
302 for (i=0; i<MaxCountCPUs; i++) {
303 apic->type = APIC_PROCESSOR;
304 apic->length = sizeof(*apic);
305 apic->processor_id = i;
306 apic->local_apic_id = i;
308 apic->flags = cpu_to_le32(1);
310 apic->flags = cpu_to_le32(0);
313 struct madt_io_apic *io_apic = (void*)apic;
314 io_apic->type = APIC_IO;
315 io_apic->length = sizeof(*io_apic);
316 io_apic->io_apic_id = CountCPUs;
317 io_apic->address = cpu_to_le32(BUILD_IOAPIC_ADDR);
318 io_apic->interrupt = cpu_to_le32(0);
320 struct madt_intsrcovr *intsrcovr = (void*)&io_apic[1];
321 if (qemu_cfg_irq0_override()) {
322 memset(intsrcovr, 0, sizeof(*intsrcovr));
323 intsrcovr->type = APIC_XRUPT_OVERRIDE;
324 intsrcovr->length = sizeof(*intsrcovr);
325 intsrcovr->source = 0;
327 intsrcovr->flags = 0; /* conforms to bus specifications */
330 for (i = 1; i < 16; i++) {
331 if (!(PCI_ISA_IRQ_MASK & (1 << i)))
332 /* No need for a INT source override structure. */
334 memset(intsrcovr, 0, sizeof(*intsrcovr));
335 intsrcovr->type = APIC_XRUPT_OVERRIDE;
336 intsrcovr->length = sizeof(*intsrcovr);
337 intsrcovr->source = i;
339 intsrcovr->flags = 0xd; /* active high, level triggered */
343 build_header((void*)madt, APIC_SIGNATURE, (void*)intsrcovr - (void*)madt, 1);
347 // Encode a hex value
348 static inline char getHex(u32 val) {
350 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
353 // Encode a length in an SSDT.
355 encodeLen(u8 *ssdt_ptr, int length, int bytes)
359 case 4: ssdt_ptr[3] = ((length >> 20) & 0xff);
360 case 3: ssdt_ptr[2] = ((length >> 12) & 0xff);
361 case 2: ssdt_ptr[1] = ((length >> 4) & 0xff);
362 ssdt_ptr[0] = (((bytes-1) & 0x3) << 6) | (length & 0x0f);
364 case 1: ssdt_ptr[0] = length & 0x3f;
366 return ssdt_ptr + bytes;
369 // AML Processor() object. See src/ssdt-proc.dsl for info.
370 static unsigned char ssdt_proc[] = {
371 0x5b,0x83,0x42,0x05,0x43,0x50,0x41,0x41,
372 0xaa,0x10,0xb0,0x00,0x00,0x06,0x08,0x49,
373 0x44,0x5f,0x5f,0x0a,0xaa,0x08,0x5f,0x48,
374 0x49,0x44,0x0d,0x41,0x43,0x50,0x49,0x30,
375 0x30,0x30,0x37,0x00,0x14,0x0f,0x5f,0x4d,
376 0x41,0x54,0x00,0xa4,0x43,0x50,0x4d,0x41,
377 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x53,
378 0x54,0x41,0x00,0xa4,0x43,0x50,0x53,0x54,
379 0x49,0x44,0x5f,0x5f,0x14,0x0f,0x5f,0x45,
380 0x4a,0x30,0x01,0x43,0x50,0x45,0x4a,0x49,
383 #define SD_OFFSET_CPUHEX 6
384 #define SD_OFFSET_CPUID1 8
385 #define SD_OFFSET_CPUID2 20
387 #define SSDT_SIGNATURE 0x54445353 // SSDT
391 int acpi_cpus = MaxCountCPUs > 0xff ? 0xff : MaxCountCPUs;
392 // length = ScopeOp + procs + NTYF method + CPON package
393 int length = ((1+3+4)
394 + (acpi_cpus * sizeof(ssdt_proc))
395 + (1+2+5+(12*acpi_cpus))
396 + (6+2+1+(1*acpi_cpus)));
397 u8 *ssdt = malloc_high(sizeof(struct acpi_table_header) + length);
402 u8 *ssdt_ptr = ssdt + sizeof(struct acpi_table_header);
404 // build Scope(_SB_) header
405 *(ssdt_ptr++) = 0x10; // ScopeOp
406 ssdt_ptr = encodeLen(ssdt_ptr, length-1, 3);
412 // build Processor object for each processor
414 for (i=0; i<acpi_cpus; i++) {
415 memcpy(ssdt_ptr, ssdt_proc, sizeof(ssdt_proc));
416 ssdt_ptr[SD_OFFSET_CPUHEX] = getHex(i >> 4);
417 ssdt_ptr[SD_OFFSET_CPUHEX+1] = getHex(i);
418 ssdt_ptr[SD_OFFSET_CPUID1] = i;
419 ssdt_ptr[SD_OFFSET_CPUID2] = i;
420 ssdt_ptr += sizeof(ssdt_proc);
423 // build "Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}"
424 *(ssdt_ptr++) = 0x14; // MethodOp
425 ssdt_ptr = encodeLen(ssdt_ptr, 2+5+(12*acpi_cpus), 2);
430 *(ssdt_ptr++) = 0x02;
431 for (i=0; i<acpi_cpus; i++) {
432 *(ssdt_ptr++) = 0xA0; // IfOp
433 ssdt_ptr = encodeLen(ssdt_ptr, 11, 1);
434 *(ssdt_ptr++) = 0x93; // LEqualOp
435 *(ssdt_ptr++) = 0x68; // Arg0Op
436 *(ssdt_ptr++) = 0x0A; // BytePrefix
438 *(ssdt_ptr++) = 0x86; // NotifyOp
441 *(ssdt_ptr++) = getHex(i >> 4);
442 *(ssdt_ptr++) = getHex(i);
443 *(ssdt_ptr++) = 0x69; // Arg1Op
446 // build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
447 *(ssdt_ptr++) = 0x08; // NameOp
452 *(ssdt_ptr++) = 0x12; // PackageOp
453 ssdt_ptr = encodeLen(ssdt_ptr, 2+1+(1*acpi_cpus), 2);
454 *(ssdt_ptr++) = acpi_cpus;
455 for (i=0; i<acpi_cpus; i++)
456 *(ssdt_ptr++) = (i < CountCPUs) ? 0x01 : 0x00;
458 build_header((void*)ssdt, SSDT_SIGNATURE, ssdt_ptr - ssdt, 1);
460 //hexdump(ssdt, ssdt_ptr - ssdt);
465 #define HPET_SIGNATURE 0x54455048 // HPET
469 struct acpi_20_hpet *hpet;
470 const void *hpet_base = (void *)BUILD_HPET_ADDRESS;
471 u32 hpet_vendor = readl(hpet_base + HPET_ID) >> 16;
472 u32 hpet_period = readl(hpet_base + HPET_PERIOD);
474 if (hpet_vendor == 0 || hpet_vendor == 0xffff ||
475 hpet_period == 0 || hpet_period > 100000000)
478 hpet = malloc_high(sizeof(*hpet));
484 memset(hpet, 0, sizeof(*hpet));
485 /* Note timer_block_id value must be kept in sync with value advertised by
488 hpet->timer_block_id = cpu_to_le32(0x8086a201);
489 hpet->addr.address = cpu_to_le32(BUILD_HPET_ADDRESS);
490 build_header((void*)hpet, HPET_SIGNATURE, sizeof(*hpet), 1);
496 acpi_build_srat_memory(struct srat_memory_affinity *numamem,
497 u64 base, u64 len, int node, int enabled)
499 numamem->type = SRAT_MEMORY;
500 numamem->length = sizeof(*numamem);
501 memset(numamem->proximity, 0 ,4);
502 numamem->proximity[0] = node;
503 numamem->flags = cpu_to_le32(!!enabled);
504 numamem->base_addr_low = base & 0xFFFFFFFF;
505 numamem->base_addr_high = base >> 32;
506 numamem->length_low = len & 0xFFFFFFFF;
507 numamem->length_high = len >> 32;
510 #define SRAT_SIGNATURE 0x54415253 // SRAT
514 int nb_numa_nodes = qemu_cfg_get_numa_nodes();
516 if (nb_numa_nodes == 0)
519 u64 *numadata = malloc_tmphigh(sizeof(u64) * (MaxCountCPUs + nb_numa_nodes));
525 qemu_cfg_get_numa_data(numadata, MaxCountCPUs + nb_numa_nodes);
527 struct system_resource_affinity_table *srat;
528 int srat_size = sizeof(*srat) +
529 sizeof(struct srat_processor_affinity) * MaxCountCPUs +
530 sizeof(struct srat_memory_affinity) * (nb_numa_nodes + 2);
532 srat = malloc_high(srat_size);
539 memset(srat, 0, srat_size);
541 struct srat_processor_affinity *core = (void*)(srat + 1);
545 for (i = 0; i < MaxCountCPUs; ++i) {
546 core->type = SRAT_PROCESSOR;
547 core->length = sizeof(*core);
548 core->local_apic_id = i;
549 curnode = *numadata++;
550 core->proximity_lo = curnode;
551 memset(core->proximity_hi, 0, 3);
552 core->local_sapic_eid = 0;
554 core->flags = cpu_to_le32(1);
561 /* the memory map is a bit tricky, it contains at least one hole
562 * from 640k-1M and possibly another one from 3.5G-4G.
564 struct srat_memory_affinity *numamem = (void*)core;
566 u64 mem_len, mem_base, next_base = 0;
568 acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
569 next_base = 1024 * 1024;
572 for (i = 1; i < nb_numa_nodes + 1; ++i) {
573 mem_base = next_base;
574 mem_len = *numadata++;
576 mem_len -= 1024 * 1024;
577 next_base = mem_base + mem_len;
579 /* Cut out the PCI hole */
580 if (mem_base <= RamSize && next_base > RamSize) {
581 mem_len -= next_base - RamSize;
583 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
587 mem_base = 1ULL << 32;
588 mem_len = next_base - RamSize;
589 next_base += (1ULL << 32) - RamSize;
591 acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
595 for (; slots < nb_numa_nodes + 2; slots++) {
596 acpi_build_srat_memory(numamem, 0, 0, 0, 0);
600 build_header((void*)srat, SRAT_SIGNATURE, srat_size, 1);
606 static const struct pci_device_id acpi_find_tbl[] = {
607 /* PIIX4 Power Management device. */
608 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, NULL),
613 struct rsdp_descriptor *RsdpAddr;
615 #define MAX_ACPI_TABLES 20
622 dprintf(3, "init ACPI tables\n");
624 // This code is hardcoded for PIIX4 Power Management device.
625 struct pci_device *pci = pci_find_init_device(acpi_find_tbl, NULL);
631 u32 tables[MAX_ACPI_TABLES], tbl_idx = 0;
633 #define ACPI_INIT_TABLE(X) \
635 tables[tbl_idx] = (u32)(X); \
636 if (tables[tbl_idx]) \
640 ACPI_INIT_TABLE(build_fadt(pci));
641 ACPI_INIT_TABLE(build_ssdt());
642 ACPI_INIT_TABLE(build_madt());
643 ACPI_INIT_TABLE(build_hpet());
644 ACPI_INIT_TABLE(build_srat());
646 u16 i, external_tables = qemu_cfg_acpi_additional_tables();
648 for (i = 0; i < external_tables; i++) {
649 u16 len = qemu_cfg_next_acpi_table_len();
650 void *addr = malloc_high(len);
655 ACPI_INIT_TABLE(qemu_cfg_next_acpi_table_load(addr, len));
656 if (tbl_idx == MAX_ACPI_TABLES) {
662 // Build final rsdt table
663 struct rsdt_descriptor_rev1 *rsdt;
664 size_t rsdt_len = sizeof(*rsdt) + sizeof(u32) * tbl_idx;
665 rsdt = malloc_high(rsdt_len);
670 memset(rsdt, 0, rsdt_len);
671 memcpy(rsdt->table_offset_entry, tables, sizeof(u32) * tbl_idx);
672 build_header((void*)rsdt, RSDT_SIGNATURE, rsdt_len, 1);
674 // Build rsdp pointer table
675 struct rsdp_descriptor *rsdp = malloc_fseg(sizeof(*rsdp));
680 memset(rsdp, 0, sizeof(*rsdp));
681 rsdp->signature = RSDP_SIGNATURE;
682 memcpy(rsdp->oem_id, CONFIG_APPNAME6, 6);
683 rsdp->rsdt_physical_address = cpu_to_le32((u32)rsdt);
684 rsdp->checksum -= checksum(rsdp, 20);
686 dprintf(1, "ACPI tables: RSDP=%p RSDT=%p\n", rsdp, rsdt);
690 find_resume_vector(void)
692 dprintf(4, "rsdp=%p\n", RsdpAddr);
693 if (!RsdpAddr || RsdpAddr->signature != RSDP_SIGNATURE)
695 struct rsdt_descriptor_rev1 *rsdt = (void*)RsdpAddr->rsdt_physical_address;
696 dprintf(4, "rsdt=%p\n", rsdt);
697 if (!rsdt || rsdt->signature != RSDT_SIGNATURE)
699 void *end = (void*)rsdt + rsdt->length;
701 for (i=0; (void*)&rsdt->table_offset_entry[i] < end; i++) {
702 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[i];
703 if (!fadt || fadt->signature != FACP_SIGNATURE)
705 dprintf(4, "fadt=%p\n", fadt);
706 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
707 dprintf(4, "facs=%p\n", facs);
708 if (! facs || facs->signature != FACS_SIGNATURE)
711 dprintf(4, "resume addr=%d\n", facs->firmware_waking_vector);
712 return facs->firmware_waking_vector;