2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
101 config COMPRESS_RAMSTAGE
102 bool "Compress ramstage with LZMA"
105 Compress ramstage to save memory in the flash image. Note
106 that decompression might slow down booting if the boot flash
107 is connected through a slow Link (i.e. SPI)
109 config INCLUDE_CONFIG_FILE
110 bool "Include the coreboot config file into the ROM image"
113 Include in CBFS the coreboot config file that was used to compile the ROM image
115 config EARLY_CBMEM_INIT
116 bool "Initialize CBMEM while in ROM stage"
119 Make coreboot initialize the cbmem structures while running in rom
120 stage. This could be useful when the rom stage wants to communicate
121 some, for instance, execution timestamps.
123 config COLLECT_TIMESTAMPS
124 bool "Create a table of timestamps collected during boot"
125 depends on EARLY_CBMEM_INIT
127 Make coreboot create a table of timer id/timer value pairs to
128 allow measuring time spent at different phases of the boot
132 source src/mainboard/Kconfig
134 # This option is used to set the architecture of a mainboard to X86.
135 # It is usually set in mainboard/*/Kconfig.
141 source src/arch/x86/Kconfig
147 source src/cpu/Kconfig
148 comment "Northbridge"
149 source src/northbridge/Kconfig
150 comment "Southbridge"
151 source src/southbridge/Kconfig
153 source src/superio/Kconfig
155 source src/devices/Kconfig
156 comment "Embedded Controllers"
157 source src/ec/Kconfig
161 menu "Generic Drivers"
162 source src/drivers/Kconfig
165 config PCI_BUS_SEGN_BITS
181 config MMCONF_SUPPORT_DEFAULT
185 config MMCONF_SUPPORT
189 source src/console/Kconfig
191 # This should default to N and be set by SuperI/O drivers that have an UART
192 config HAVE_UART_IO_MAPPED
196 config HAVE_UART_MEMORY_MAPPED
200 config HAVE_ACPI_RESUME
204 config HAVE_ACPI_SLIC
208 config ACPI_SSDTX_NUM
212 config HAVE_HARD_RESET
214 default y if BOARD_HAS_HARD_RESET
217 This variable specifies whether a given board has a hard_reset
218 function, no matter if it's provided by board code or chipset code.
220 config HAVE_INIT_TIMER
222 default n if UDELAY_IO
225 config HAVE_MAINBOARD_RESOURCES
229 config USE_OPTION_TABLE
233 config HAVE_OPTION_TABLE
237 This variable specifies whether a given board has a cmos.layout
238 file containing NVRAM/CMOS bit definitions.
239 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
245 config HAVE_SMI_HANDLER
249 config PCI_IO_CFG_EXT
261 # TODO: Can probably be removed once all chipsets have kconfig options for it.
266 config USE_WATCHDOG_ON_BOOT
274 Build board-specific VGA code.
280 Enable Unified Memory Architecture for graphics.
287 config HAVE_ACPI_TABLES
290 This variable specifies whether a given board has ACPI table support.
291 It is usually set in mainboard/*/Kconfig.
292 Whether or not the ACPI tables are actually generated by coreboot
293 is configurable by the user via GENERATE_ACPI_TABLES.
298 This variable specifies whether a given board has MP table support.
299 It is usually set in mainboard/*/Kconfig.
300 Whether or not the MP table is actually generated by coreboot
301 is configurable by the user via GENERATE_MP_TABLE.
303 config HAVE_PIRQ_TABLE
306 This variable specifies whether a given board has PIRQ table support.
307 It is usually set in mainboard/*/Kconfig.
308 Whether or not the PIRQ table is actually generated by coreboot
309 is configurable by the user via GENERATE_PIRQ_TABLE.
311 #These Options are here to avoid "undefined" warnings.
312 #The actual selection and help texts are in the following menu.
314 config GENERATE_ACPI_TABLES
316 default HAVE_ACPI_TABLES
318 config GENERATE_MP_TABLE
320 default HAVE_MP_TABLE
322 config GENERATE_PIRQ_TABLE
324 default HAVE_PIRQ_TABLE
326 config GENERATE_SMBIOS_TABLES
332 config WRITE_HIGH_TABLES
333 bool "Write 'high' tables to avoid being overwritten in F segment"
337 bool "Generate Multiboot tables (for GRUB2)"
340 config GENERATE_ACPI_TABLES
341 depends on HAVE_ACPI_TABLES
342 bool "Generate ACPI tables"
345 Generate ACPI tables for this board.
349 config GENERATE_MP_TABLE
350 depends on HAVE_MP_TABLE
351 bool "Generate an MP table"
354 Generate an MP table (conforming to the Intel MultiProcessor
355 specification 1.4) for this board.
359 config GENERATE_PIRQ_TABLE
360 depends on HAVE_PIRQ_TABLE
361 bool "Generate a PIRQ table"
364 Generate a PIRQ table for this board.
368 config GENERATE_SMBIOS_TABLES
370 bool "Generate SMBIOS tables"
373 Generate SMBIOS tables for this board.
382 prompt "Add a payload"
383 default PAYLOAD_NONE if !ARCH_X86
384 default PAYLOAD_SEABIOS if ARCH_X86
389 Select this option if you want to create an "empty" coreboot
390 ROM image for a certain mainboard, i.e. a coreboot ROM image
391 which does not yet contain a payload.
393 For such an image to be useful, you have to use 'cbfstool'
394 to add a payload to the ROM image later.
397 bool "An ELF executable payload"
399 Select this option if you have a payload image (an ELF file)
400 which coreboot should run as soon as the basic hardware
401 initialization is completed.
403 You will be able to specify the location and file name of the
406 config PAYLOAD_SEABIOS
410 Select this option if you want to build a coreboot image
411 with a SeaBIOS payload. If you don't know what this is
412 about, just leave it enabled.
414 See http://coreboot.org/Payloads for more information.
419 Select this option if you want to build a coreboot image
420 with a FILO payload. If you don't know what this is
421 about, just leave it enabled.
423 See http://coreboot.org/Payloads for more information.
428 prompt "SeaBIOS version"
429 default SEABIOS_STABLE
430 depends on PAYLOAD_SEABIOS
432 config SEABIOS_STABLE
435 Stable SeaBIOS version
436 config SEABIOS_MASTER
439 Newest SeaBIOS version
443 prompt "FILO version"
445 depends on PAYLOAD_FILO
458 string "Payload path and filename"
459 depends on PAYLOAD_ELF
460 default "payload.elf"
462 The path and filename of the ELF executable file to use as payload.
465 depends on PAYLOAD_SEABIOS
466 default "$(obj)/seabios/out/bios.bin.elf"
469 depends on PAYLOAD_FILO
470 default "payloads/external/FILO/filo/build/filo.elf"
472 # TODO: Defined if no payload? Breaks build?
473 config COMPRESSED_PAYLOAD_LZMA
474 bool "Use LZMA compression for payloads"
476 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
478 In order to reduce the size payloads take up in the ROM chip
479 coreboot can compress them using the LZMA algorithm.
481 config COMPRESSED_PAYLOAD_NRV2B
490 bool "Add a VGA BIOS image"
492 Select this option if you have a VGA BIOS image that you would
493 like to add to your ROM.
495 You will be able to specify the location and file name of the
499 string "VGA BIOS path and filename"
501 default "vgabios.bin"
503 The path and filename of the file to use as VGA BIOS.
506 string "VGA device PCI IDs"
510 The comma-separated PCI vendor and device ID that would associate
511 your VGA BIOS to your video card.
515 In the above example 1106 is the PCI vendor ID (in hex, but without
516 the "0x" prefix) and 3230 specifies the PCI device ID of the
517 video card (also in hex, without "0x" prefix).
520 bool "Add an MBI image"
521 depends on NORTHBRIDGE_INTEL_I82830
523 Select this option if you have an Intel MBI image that you would
524 like to add to your ROM.
526 You will be able to specify the location and file name of the
530 string "Intel MBI path and filename"
534 The path and filename of the file to use as VGA BIOS.
539 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
541 config FRAMEBUFFER_SET_VESA_MODE
542 prompt "Set VESA framebuffer mode"
544 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
546 Set VESA framebuffer mode (needed for bootsplash)
548 # TODO: Turn this into a "choice".
549 config FRAMEBUFFER_VESA_MODE
550 prompt "VESA framebuffer video mode"
553 depends on FRAMEBUFFER_SET_VESA_MODE
555 This option sets the resolution used for the coreboot framebuffer (and
556 bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
557 some day make this a "choice".
559 config FRAMEBUFFER_KEEP_VESA_MODE
560 prompt "Keep VESA framebuffer"
562 depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
564 This option keeps the framebuffer mode set after coreboot finishes
565 execution. If this option is enabled, coreboot will pass a
566 framebuffer entry in its coreboot table and the payload will need a
567 framebuffer driver. If this option is disabled, coreboot will switch
568 back to text mode before handing control to a payload.
571 prompt "Show graphical bootsplash"
573 depends on FRAMEBUFFER_SET_VESA_MODE
575 This option shows a graphical bootsplash screen. The grapics are
576 loaded from the CBFS file bootsplash.jpg.
578 config BOOTSPLASH_FILE
579 string "Bootsplash path and filename"
580 depends on BOOTSPLASH
581 default "bootsplash.jpg"
583 The path and filename of the file to use as graphical bootsplash
584 screen. The file format has to be jpg.
589 # TODO: Better help text and detailed instructions.
591 bool "GDB debugging support"
594 If enabled, you will be able to set breakpoints for gdb debugging.
595 See src/arch/x86/lib/c_start.S for details.
597 config HAVE_DEBUG_RAM_SETUP
600 config DEBUG_RAM_SETUP
601 bool "Output verbose RAM init debug messages"
603 depends on HAVE_DEBUG_RAM_SETUP
605 This option enables additional RAM init related debug messages.
606 It is recommended to enable this when debugging issues on your
607 board which might be RAM init related.
609 Note: This option will increase the size of the coreboot image.
613 config HAVE_DEBUG_CAR
618 depends on HAVE_DEBUG_CAR
620 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
621 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
622 # printk(BIOS_DEBUG, ...) calls.
624 bool "Output verbose Cache-as-RAM debug messages"
626 depends on HAVE_DEBUG_CAR
628 This option enables additional CAR related debug messages.
632 bool "Check PIRQ table consistency"
634 depends on GENERATE_PIRQ_TABLE
638 config HAVE_DEBUG_SMBUS
642 bool "Output verbose SMBus debug messages"
644 depends on HAVE_DEBUG_SMBUS
646 This option enables additional SMBus (and SPD) debug messages.
648 Note: This option will increase the size of the coreboot image.
653 bool "Output verbose SMI debug messages"
655 depends on HAVE_SMI_HANDLER
657 This option enables additional SMI related debug messages.
659 Note: This option will increase the size of the coreboot image.
663 config DEBUG_SMM_RELOCATION
664 bool "Debug SMM relocation code"
666 depends on HAVE_SMI_HANDLER
668 This option enables additional SMM handler relocation related
671 Note: This option will increase the size of the coreboot image.
678 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
679 # printk(BIOS_DEBUG, ...) calls.
680 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
682 bool "Output verbose malloc debug messages"
685 This option enables additional malloc related debug messages.
687 Note: This option will increase the size of the coreboot image.
695 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
696 # printk(BIOS_DEBUG, ...) calls.
697 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
699 bool "Output verbose ACPI debug messages"
702 This option enables additional ACPI related debug messages.
704 Note: This option will slightly increase the size of the coreboot image.
709 config REALMODE_DEBUG
711 depends on PCI_OPTION_ROM_RUN_REALMODE
713 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
714 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
715 # printk(BIOS_DEBUG, ...) calls.
716 config REALMODE_DEBUG
717 bool "Enable debug messages for option ROM execution"
719 depends on PCI_OPTION_ROM_RUN_REALMODE
721 This option enables additional x86emu related debug messages.
723 Note: This option will increase the time to emulate a ROM.
729 bool "Output verbose x86emu debug messages"
731 depends on PCI_OPTION_ROM_RUN_YABEL
733 This option enables additional x86emu related debug messages.
735 Note: This option will increase the size of the coreboot image.
739 config X86EMU_DEBUG_JMP
740 bool "Trace JMP/RETF"
742 depends on X86EMU_DEBUG
744 Print information about JMP and RETF opcodes from x86emu.
746 Note: This option will increase the size of the coreboot image.
750 config X86EMU_DEBUG_TRACE
751 bool "Trace all opcodes"
753 depends on X86EMU_DEBUG
755 Print _all_ opcodes that are executed by x86emu.
757 WARNING: This will produce a LOT of output and take a long time.
759 Note: This option will increase the size of the coreboot image.
763 config X86EMU_DEBUG_PNP
764 bool "Log Plug&Play accesses"
766 depends on X86EMU_DEBUG
768 Print Plug And Play accesses made by option ROMs.
770 Note: This option will increase the size of the coreboot image.
774 config X86EMU_DEBUG_DISK
777 depends on X86EMU_DEBUG
779 Print Disk I/O related messages.
781 Note: This option will increase the size of the coreboot image.
785 config X86EMU_DEBUG_PMM
788 depends on X86EMU_DEBUG
790 Print messages related to POST Memory Manager (PMM).
792 Note: This option will increase the size of the coreboot image.
797 config X86EMU_DEBUG_VBE
798 bool "Debug VESA BIOS Extensions"
800 depends on X86EMU_DEBUG
802 Print messages related to VESA BIOS Extension (VBE) functions.
804 Note: This option will increase the size of the coreboot image.
808 config X86EMU_DEBUG_INT10
809 bool "Redirect INT10 output to console"
811 depends on X86EMU_DEBUG
813 Let INT10 (i.e. character output) calls print messages to debug output.
815 Note: This option will increase the size of the coreboot image.
819 config X86EMU_DEBUG_INTERRUPTS
820 bool "Log intXX calls"
822 depends on X86EMU_DEBUG
824 Print messages related to interrupt handling.
826 Note: This option will increase the size of the coreboot image.
830 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
831 bool "Log special memory accesses"
833 depends on X86EMU_DEBUG
835 Print messages related to accesses to certain areas of the virtual
836 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
838 Note: This option will increase the size of the coreboot image.
842 config X86EMU_DEBUG_MEM
843 bool "Log all memory accesses"
845 depends on X86EMU_DEBUG
847 Print memory accesses made by option ROM.
848 Note: This also includes accesses to fetch instructions.
850 Note: This option will increase the size of the coreboot image.
854 config X86EMU_DEBUG_IO
855 bool "Log IO accesses"
857 depends on X86EMU_DEBUG
859 Print I/O accesses made by option ROM.
861 Note: This option will increase the size of the coreboot image.
866 bool "Built-in low-level shell"
869 If enabled, you will have a low level shell to examine your machine.
870 Put llshell() in your (romstage) code to start the shell.
871 See src/arch/x86/llshell/llshell.inc for details.
874 bool "Trace function calls"
877 If enabled, every function will print information to console once
878 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
879 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
880 of calling function. Please note some printk releated functions
881 are omitted from trace to have good looking console dumps.
884 config LIFT_BSP_APIC_ID
888 # These probably belong somewhere else, but they are needed somewhere.
889 config AP_CODE_IN_CAR
893 config RAMINIT_SYSINFO
897 config ENABLE_APIC_EXT_ID
901 config WARNINGS_ARE_ERRORS
905 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
906 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
907 # mutually exclusive. One of these options must be selected in the
908 # mainboard Kconfig if the chipset supports enabling and disabling of
909 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
910 # in mainboard/Kconfig to know if the button should be enabled or not.
912 config POWER_BUTTON_DEFAULT_ENABLE
915 Select when the board has a power button which can optionally be
916 disabled by the user.
918 config POWER_BUTTON_DEFAULT_DISABLE
921 Select when the board has a power button which can optionally be
922 enabled by the user, e.g. when the board ships with a jumper over
923 the power switch contacts.
925 config POWER_BUTTON_FORCE_ENABLE
928 Select when the board requires that the power button is always
931 config POWER_BUTTON_FORCE_DISABLE
934 Select when the board requires that the power button is always
935 disabled, e.g. when it has been hardwired to ground.
937 config POWER_BUTTON_IS_OPTIONAL
939 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
940 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
942 Internal option that controls ENABLE_POWER_BUTTON visibility.
944 source src/Kconfig.deprecated_options
945 source src/vendorcode/Kconfig