2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
83 config SCONFIG_GENPARSER
84 bool "Generate SCONFIG parser using flex and bison"
88 Enable this option if you are working on the sconfig
89 device tree parser and made changes to sconfig.l and
93 config USE_OPTION_TABLE
94 bool "Use CMOS for configuration values"
96 depends on HAVE_OPTION_TABLE
98 Enable this option if coreboot shall read options from the "CMOS"
99 NVRAM instead of using hard coded values.
103 source src/mainboard/Kconfig
105 # This option is used to set the architecture of a mainboard to X86.
106 # It is usually set in mainboard/*/Kconfig.
112 source src/arch/x86/Kconfig
118 source src/cpu/Kconfig
119 comment "Northbridge"
120 source src/northbridge/Kconfig
121 comment "Southbridge"
122 source src/southbridge/Kconfig
124 source src/superio/Kconfig
126 source src/devices/Kconfig
127 comment "Embedded Controllers"
128 source src/ec/Kconfig
132 menu "Generic Drivers"
133 source src/drivers/Kconfig
136 config PCI_BUS_SEGN_BITS
152 config MMCONF_SUPPORT_DEFAULT
156 config MMCONF_SUPPORT
160 source src/console/Kconfig
162 config HAVE_ACPI_RESUME
166 config HAVE_ACPI_SLIC
170 config ACPI_SSDTX_NUM
174 config HAVE_HARD_RESET
176 default y if BOARD_HAS_HARD_RESET
179 This variable specifies whether a given board has a hard_reset
180 function, no matter if it's provided by board code or chipset code.
182 config HAVE_INIT_TIMER
184 default n if UDELAY_IO
187 config HAVE_MAINBOARD_RESOURCES
191 config USE_OPTION_TABLE
195 config HAVE_OPTION_TABLE
199 This variable specifies whether a given board has a cmos.layout
200 file containing NVRAM/CMOS bit definitions.
201 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
207 config HAVE_SMI_HANDLER
211 config PCI_IO_CFG_EXT
219 # TODO: Can probably be removed once all chipsets have kconfig options for it.
224 config USE_WATCHDOG_ON_BOOT
232 Build board-specific VGA code.
238 Enable Unified Memory Architecture for graphics.
245 config HAVE_ACPI_TABLES
248 This variable specifies whether a given board has ACPI table support.
249 It is usually set in mainboard/*/Kconfig.
250 Whether or not the ACPI tables are actually generated by coreboot
251 is configurable by the user via GENERATE_ACPI_TABLES.
256 This variable specifies whether a given board has MP table support.
257 It is usually set in mainboard/*/Kconfig.
258 Whether or not the MP table is actually generated by coreboot
259 is configurable by the user via GENERATE_MP_TABLE.
261 config HAVE_PIRQ_TABLE
264 This variable specifies whether a given board has PIRQ table support.
265 It is usually set in mainboard/*/Kconfig.
266 Whether or not the PIRQ table is actually generated by coreboot
267 is configurable by the user via GENERATE_PIRQ_TABLE.
269 #These Options are here to avoid "undefined" warnings.
270 #The actual selection and help texts are in the following menu.
272 config GENERATE_ACPI_TABLES
274 default HAVE_ACPI_TABLES
276 config GENERATE_MP_TABLE
278 default HAVE_MP_TABLE
280 config GENERATE_PIRQ_TABLE
282 default HAVE_PIRQ_TABLE
286 config WRITE_HIGH_TABLES
287 bool "Write 'high' tables to avoid being overwritten in F segment"
291 bool "Generate Multiboot tables (for GRUB2)"
294 config GENERATE_ACPI_TABLES
295 depends on HAVE_ACPI_TABLES
296 bool "Generate ACPI tables"
299 Generate ACPI tables for this board.
303 config GENERATE_MP_TABLE
304 depends on HAVE_MP_TABLE
305 bool "Generate an MP table"
308 Generate an MP table (conforming to the Intel MultiProcessor
309 specification 1.4) for this board.
313 config GENERATE_PIRQ_TABLE
314 depends on HAVE_PIRQ_TABLE
315 bool "Generate a PIRQ table"
318 Generate a PIRQ table for this board.
327 prompt "Add a payload"
328 default PAYLOAD_NONE if !ARCH_X86
329 default PAYLOAD_SEABIOS if ARCH_X86
334 Select this option if you want to create an "empty" coreboot
335 ROM image for a certain mainboard, i.e. a coreboot ROM image
336 which does not yet contain a payload.
338 For such an image to be useful, you have to use 'cbfstool'
339 to add a payload to the ROM image later.
342 bool "An ELF executable payload"
344 Select this option if you have a payload image (an ELF file)
345 which coreboot should run as soon as the basic hardware
346 initialization is completed.
348 You will be able to specify the location and file name of the
351 config PAYLOAD_SEABIOS
355 Select this option if you want to build a coreboot image
356 with a SeaBIOS payload. If you don't know what this is
357 about, just leave it enabled.
359 See http://coreboot.org/Payloads for more information.
364 Select this option if you want to build a coreboot image
365 with a FILO payload. If you don't know what this is
366 about, just leave it enabled.
368 See http://coreboot.org/Payloads for more information.
373 prompt "SeaBIOS version"
374 default SEABIOS_STABLE
375 depends on PAYLOAD_SEABIOS
377 config SEABIOS_STABLE
380 Stable SeaBIOS version
381 config SEABIOS_MASTER
384 Newest SeaBIOS version
388 prompt "FILO version"
390 depends on PAYLOAD_FILO
403 string "Payload path and filename"
404 depends on PAYLOAD_ELF
405 default "payload.elf"
407 The path and filename of the ELF executable file to use as payload.
410 depends on PAYLOAD_SEABIOS
411 default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
414 depends on PAYLOAD_FILO
415 default "payloads/external/FILO/filo/build/filo.elf"
417 # TODO: Defined if no payload? Breaks build?
418 config COMPRESSED_PAYLOAD_LZMA
419 bool "Use LZMA compression for payloads"
421 depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
423 In order to reduce the size payloads take up in the ROM chip
424 coreboot can compress them using the LZMA algorithm.
426 config COMPRESSED_PAYLOAD_NRV2B
435 bool "Add a VGA BIOS image"
437 Select this option if you have a VGA BIOS image that you would
438 like to add to your ROM.
440 You will be able to specify the location and file name of the
444 string "VGA BIOS path and filename"
446 default "vgabios.bin"
448 The path and filename of the file to use as VGA BIOS.
451 string "VGA device PCI IDs"
455 The comma-separated PCI vendor and device ID that would associate
456 your VGA BIOS to your video card.
460 In the above example 1106 is the PCI vendor ID (in hex, but without
461 the "0x" prefix) and 3230 specifies the PCI device ID of the
462 video card (also in hex, without "0x" prefix).
465 bool "Add an MBI image"
466 depends on NORTHBRIDGE_INTEL_I82830
468 Select this option if you have an Intel MBI image that you would
469 like to add to your ROM.
471 You will be able to specify the location and file name of the
475 string "Intel MBI path and filename"
479 The path and filename of the file to use as VGA BIOS.
484 depends on PCI_OPTION_ROM_RUN_YABEL
487 prompt "Show graphical bootsplash"
489 depends on PCI_OPTION_ROM_RUN_YABEL
491 This option shows a graphical bootsplash screen. The grapics are
492 loaded from the CBFS file bootsplash.jpg.
494 config BOOTSPLASH_FILE
495 string "Bootsplash path and filename"
496 depends on BOOTSPLASH
497 default "bootsplash.jpg"
499 The path and filename of the file to use as graphical bootsplash
500 screen. The file format has to be jpg.
502 # TODO: Turn this into a "choice".
503 config FRAMEBUFFER_VESA_MODE
504 prompt "VESA framebuffer video mode"
507 depends on BOOTSPLASH
509 This option sets the resolution used for the coreboot framebuffer and
510 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
511 some day make this a "choice".
513 config COREBOOT_KEEP_FRAMEBUFFER
514 prompt "Keep VESA framebuffer"
516 depends on BOOTSPLASH
518 This option keeps the framebuffer mode set after coreboot finishes
519 execution. If this option is enabled, coreboot will pass a
520 framebuffer entry in its coreboot table and the payload will need a
521 framebuffer driver. If this option is disabled, coreboot will switch
522 back to text mode before handing control to a payload.
528 # TODO: Better help text and detailed instructions.
530 bool "GDB debugging support"
533 If enabled, you will be able to set breakpoints for gdb debugging.
534 See src/arch/x86/lib/c_start.S for details.
536 config HAVE_DEBUG_RAM_SETUP
539 config DEBUG_RAM_SETUP
540 bool "Output verbose RAM init debug messages"
542 depends on HAVE_DEBUG_RAM_SETUP
544 This option enables additional RAM init related debug messages.
545 It is recommended to enable this when debugging issues on your
546 board which might be RAM init related.
548 Note: This option will increase the size of the coreboot image.
552 config HAVE_DEBUG_CAR
557 depends on HAVE_DEBUG_CAR
559 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
560 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
561 # printk(BIOS_DEBUG, ...) calls.
563 bool "Output verbose Cache-as-RAM debug messages"
565 depends on HAVE_DEBUG_CAR
567 This option enables additional CAR related debug messages.
571 bool "Check PIRQ table consistency"
573 depends on GENERATE_PIRQ_TABLE
577 config HAVE_DEBUG_SMBUS
581 bool "Output verbose SMBus debug messages"
583 depends on HAVE_DEBUG_SMBUS
585 This option enables additional SMBus (and SPD) debug messages.
587 Note: This option will increase the size of the coreboot image.
592 bool "Output verbose SMI debug messages"
594 depends on HAVE_SMI_HANDLER
596 This option enables additional SMI related debug messages.
598 Note: This option will increase the size of the coreboot image.
602 config DEBUG_SMM_RELOCATION
603 bool "Debug SMM relocation code"
605 depends on HAVE_SMI_HANDLER
607 This option enables additional SMM handler relocation related
610 Note: This option will increase the size of the coreboot image.
617 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
618 # printk(BIOS_DEBUG, ...) calls.
619 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
621 bool "Output verbose malloc debug messages"
624 This option enables additional malloc related debug messages.
626 Note: This option will increase the size of the coreboot image.
631 config REALMODE_DEBUG
633 depends on PCI_OPTION_ROM_RUN_REALMODE
635 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
636 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
637 # printk(BIOS_DEBUG, ...) calls.
638 config REALMODE_DEBUG
639 bool "Enable debug messages for option ROM execution"
641 depends on PCI_OPTION_ROM_RUN_REALMODE
643 This option enables additional x86emu related debug messages.
645 Note: This option will increase the time to emulate a ROM.
651 bool "Output verbose x86emu debug messages"
653 depends on PCI_OPTION_ROM_RUN_YABEL
655 This option enables additional x86emu related debug messages.
657 Note: This option will increase the size of the coreboot image.
661 config X86EMU_DEBUG_JMP
662 bool "Trace JMP/RETF"
664 depends on X86EMU_DEBUG
666 Print information about JMP and RETF opcodes from x86emu.
668 Note: This option will increase the size of the coreboot image.
672 config X86EMU_DEBUG_TRACE
673 bool "Trace all opcodes"
675 depends on X86EMU_DEBUG
677 Print _all_ opcodes that are executed by x86emu.
679 WARNING: This will produce a LOT of output and take a long time.
681 Note: This option will increase the size of the coreboot image.
685 config X86EMU_DEBUG_PNP
686 bool "Log Plug&Play accesses"
688 depends on X86EMU_DEBUG
690 Print Plug And Play accesses made by option ROMs.
692 Note: This option will increase the size of the coreboot image.
696 config X86EMU_DEBUG_DISK
699 depends on X86EMU_DEBUG
701 Print Disk I/O related messages.
703 Note: This option will increase the size of the coreboot image.
707 config X86EMU_DEBUG_PMM
710 depends on X86EMU_DEBUG
712 Print messages related to POST Memory Manager (PMM).
714 Note: This option will increase the size of the coreboot image.
719 config X86EMU_DEBUG_VBE
720 bool "Debug VESA BIOS Extensions"
722 depends on X86EMU_DEBUG
724 Print messages related to VESA BIOS Extension (VBE) functions.
726 Note: This option will increase the size of the coreboot image.
730 config X86EMU_DEBUG_INT10
731 bool "Redirect INT10 output to console"
733 depends on X86EMU_DEBUG
735 Let INT10 (i.e. character output) calls print messages to debug output.
737 Note: This option will increase the size of the coreboot image.
741 config X86EMU_DEBUG_INTERRUPTS
742 bool "Log intXX calls"
744 depends on X86EMU_DEBUG
746 Print messages related to interrupt handling.
748 Note: This option will increase the size of the coreboot image.
752 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
753 bool "Log special memory accesses"
755 depends on X86EMU_DEBUG
757 Print messages related to accesses to certain areas of the virtual
758 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
760 Note: This option will increase the size of the coreboot image.
764 config X86EMU_DEBUG_MEM
765 bool "Log all memory accesses"
767 depends on X86EMU_DEBUG
769 Print memory accesses made by option ROM.
770 Note: This also includes accesses to fetch instructions.
772 Note: This option will increase the size of the coreboot image.
776 config X86EMU_DEBUG_IO
777 bool "Log IO accesses"
779 depends on X86EMU_DEBUG
781 Print I/O accesses made by option ROM.
783 Note: This option will increase the size of the coreboot image.
788 bool "Built-in low-level shell"
791 If enabled, you will have a low level shell to examine your machine.
792 Put llshell() in your (romstage) code to start the shell.
793 See src/arch/x86/llshell/llshell.inc for details.
797 config LIFT_BSP_APIC_ID
801 # These probably belong somewhere else, but they are needed somewhere.
802 config AP_CODE_IN_CAR
806 config RAMINIT_SYSINFO
810 config ENABLE_APIC_EXT_ID
814 config WARNINGS_ARE_ERRORS
818 config ID_SECTION_OFFSET
822 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
823 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
824 # mutually exclusive. One of these options must be selected in the
825 # mainboard Kconfig if the chipset supports enabling and disabling of
826 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
827 # in mainboard/Kconfig to know if the button should be enabled or not.
829 config POWER_BUTTON_DEFAULT_ENABLE
832 Select when the board has a power button which can optionally be
833 disabled by the user.
835 config POWER_BUTTON_DEFAULT_DISABLE
838 Select when the board has a power button which can optionally be
839 enabled by the user, e.g. when the board ships with a jumper over
840 the power switch contacts.
842 config POWER_BUTTON_FORCE_ENABLE
845 Select when the board requires that the power button is always
848 config POWER_BUTTON_FORCE_DISABLE
851 Select when the board requires that the power button is always
852 disabled, e.g. when it has been hardwired to ground.
854 config POWER_BUTTON_IS_OPTIONAL
856 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
857 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
859 Internal option that controls ENABLE_POWER_BUTTON visibility.
861 source src/Kconfig.deprecated_options