2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
85 source src/mainboard/Kconfig
86 source src/arch/i386/Kconfig
91 source src/cpu/Kconfig
93 source src/northbridge/Kconfig
95 source src/southbridge/Kconfig
97 source src/superio/Kconfig
99 source src/devices/Kconfig
103 config PCI_BUS_SEGN_BITS
107 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
111 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
135 config USE_PRINTK_IN_CAR
139 config USE_OPTION_TABLE
140 bool "Use CMOS for configuration values"
147 config MMCONF_SUPPORT_DEFAULT
151 config MMCONF_SUPPORT
158 source src/console/Kconfig
160 config HAVE_ACPI_RESUME
164 config ACPI_SSDTX_NUM
168 config HAVE_HARD_RESET
170 default y if BOARD_HAS_HARD_RESET
173 This variable specifies whether a given board has a hard_reset
174 function, no matter if it's provided by board code or chipset code.
176 config HAVE_INIT_TIMER
178 default n if UDELAY_IO
181 config HAVE_MAINBOARD_RESOURCES
185 config HAVE_OPTION_TABLE
189 This variable specifies whether a given board has a cmos.layout
190 file containing NVRAM/CMOS bit definitions.
191 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
197 config HAVE_SMI_HANDLER
201 config PCI_IO_CFG_EXT
209 # TODO: Can probably be removed once all chipsets have kconfig options for it.
214 config USE_WATCHDOG_ON_BOOT
222 Build board-specific VGA code.
228 Enable Unified Memory Architecture for graphics.
235 #TODO Remove this option or make it useful.
236 config HAVE_LOW_TABLES
240 This Option is unused in the code. Since two boards try to set it to
241 'n', they may be broken. We either need to make the option useful or
242 get rid of it. The broken boards are:
246 config HAVE_HIGH_TABLES
250 This variable specifies whether a given northbridge has high table
252 It is set in northbridge/*/Kconfig.
253 Whether or not the high tables are actually written by coreboot is
254 configurable by the user via WRITE_HIGH_TABLES.
256 config HAVE_ACPI_TABLES
259 This variable specifies whether a given board has ACPI table support.
260 It is usually set in mainboard/*/Kconfig.
261 Whether or not the ACPI tables are actually generated by coreboot
262 is configurable by the user via GENERATE_ACPI_TABLES.
267 This variable specifies whether a given board has MP table support.
268 It is usually set in mainboard/*/Kconfig.
269 Whether or not the MP table is actually generated by coreboot
270 is configurable by the user via GENERATE_MP_TABLE.
272 config HAVE_PIRQ_TABLE
275 This variable specifies whether a given board has PIRQ table support.
276 It is usually set in mainboard/*/Kconfig.
277 Whether or not the PIRQ table is actually generated by coreboot
278 is configurable by the user via GENERATE_PIRQ_TABLE.
280 #These Options are here to avoid "undefined" warnings.
281 #The actual selection and help texts are in the following menu.
283 config GENERATE_ACPI_TABLES
285 default HAVE_ACPI_TABLES
287 config GENERATE_MP_TABLE
289 default HAVE_MP_TABLE
291 config GENERATE_PIRQ_TABLE
293 default HAVE_PIRQ_TABLE
295 config WRITE_HIGH_TABLES
297 default HAVE_HIGH_TABLES
301 config WRITE_HIGH_TABLES
302 bool "Write 'high' tables to avoid being overwritten in F segment"
303 depends on HAVE_HIGH_TABLES
307 bool "Generate Multiboot tables (for GRUB2)"
310 config GENERATE_ACPI_TABLES
311 depends on HAVE_ACPI_TABLES
312 bool "Generate ACPI tables"
315 Generate ACPI tables for this board.
319 config GENERATE_MP_TABLE
320 depends on HAVE_MP_TABLE
321 bool "Generate an MP table"
324 Generate an MP table (conforming to the Intel MultiProcessor
325 specification 1.4) for this board.
329 config GENERATE_PIRQ_TABLE
330 depends on HAVE_PIRQ_TABLE
331 bool "Generate a PIRQ table"
334 Generate a PIRQ table for this board.
343 prompt "Add a payload"
349 Select this option if you want to create an "empty" coreboot
350 ROM image for a certain mainboard, i.e. a coreboot ROM image
351 which does not yet contain a payload.
353 For such an image to be useful, you have to use 'cbfstool'
354 to add a payload to the ROM image later.
357 bool "An ELF executable payload"
359 Select this option if you have a payload image (an ELF file)
360 which coreboot should run as soon as the basic hardware
361 initialization is completed.
363 You will be able to specify the location and file name of the
368 config FALLBACK_PAYLOAD_FILE
369 string "Payload path and filename"
370 depends on PAYLOAD_ELF
371 default "payload.elf"
373 The path and filename of the ELF executable file to use as payload.
375 # TODO: Defined if no payload? Breaks build?
376 config COMPRESSED_PAYLOAD_LZMA
377 bool "Use LZMA compression for payloads"
379 depends on PAYLOAD_ELF
381 In order to reduce the size payloads take up in the ROM chip
382 coreboot can compress them using the LZMA algorithm.
384 config COMPRESSED_PAYLOAD_NRV2B
393 bool "Add a VGA BIOS image"
395 Select this option if you have a VGA BIOS image that you would
396 like to add to your ROM.
398 You will be able to specify the location and file name of the
401 config FALLBACK_VGA_BIOS_FILE
402 string "VGA BIOS path and filename"
404 default "vgabios.bin"
406 The path and filename of the file to use as VGA BIOS.
408 config FALLBACK_VGA_BIOS_ID
409 string "VGA device PCI IDs"
413 The comma-separated PCI vendor and device ID that would associate
414 your VGA BIOS to your video card.
418 In the above example 1106 is the PCI vendor ID (in hex, but without
419 the "0x" prefix) and 3230 specifies the PCI device ID of the
420 video card (also in hex, without "0x" prefix).
423 bool "Add an MBI image"
424 depends on NORTHBRIDGE_INTEL_I82830
426 Select this option if you have an Intel MBI image that you would
427 like to add to your ROM.
429 You will be able to specify the location and file name of the
432 config FALLBACK_MBI_FILE
433 string "Intel MBI path and filename"
437 The path and filename of the file to use as VGA BIOS.
442 depends on PCI_OPTION_ROM_RUN_YABEL
445 prompt "Show graphical bootsplash"
447 depends on PCI_OPTION_ROM_RUN_YABEL
449 This option shows a graphical bootsplash screen. The grapics are
450 loaded from the CBFS file bootsplash.jpg.
452 config FALLBACK_BOOTSPLASH_FILE
453 string "Bootsplash path and filename"
454 depends on BOOTSPLASH
455 default "bootsplash.jpg"
457 The path and filename of the file to use as graphical bootsplash
458 screen. The file format has to be jpg.
460 # TODO: Turn this into a "choice".
461 config FRAMEBUFFER_VESA_MODE
462 prompt "VESA framebuffer video mode"
465 depends on BOOTSPLASH
467 This option sets the resolution used for the coreboot framebuffer and
468 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
469 some day make this a "choice".
471 config COREBOOT_KEEP_FRAMEBUFFER
472 prompt "Keep VESA framebuffer"
474 depends on BOOTSPLASH
476 This option keeps the framebuffer mode set after coreboot finishes
477 execution. If this option is enabled, coreboot will pass a
478 framebuffer entry in its coreboot table and the payload will need a
479 framebuffer driver. If this option is disabled, coreboot will switch
480 back to text mode before handing control to a payload.
486 # TODO: Better help text and detailed instructions.
488 bool "GDB debugging support"
491 If enabled, you will be able to set breakpoints for gdb debugging.
492 See src/arch/i386/lib/c_start.S for details.
494 config DEBUG_RAM_SETUP
495 bool "Output verbose RAM init debug messages"
497 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
498 || NORTHBRIDGE_AMD_AMDK8 \
499 || NORTHBRIDGE_VIA_CN700 \
500 || NORTHBRIDGE_VIA_CX700 \
501 || NORTHBRIDGE_VIA_VX800 \
502 || NORTHBRIDGE_INTEL_E7501 \
503 || NORTHBRIDGE_INTEL_I440BX \
504 || NORTHBRIDGE_INTEL_I82810 \
505 || NORTHBRIDGE_INTEL_I82830 \
506 || NORTHBRIDGE_INTEL_I945)
508 This option enables additional RAM init related debug messages.
509 It is recommended to enable this when debugging issues on your
510 board which might be RAM init related.
512 Note: This option will increase the size of the coreboot image.
517 bool "Output verbose SMBus debug messages"
519 depends on (SOUTHBRIDGE_VIA_VT8237R \
520 || NORTHBRIDGE_VIA_VX800 \
521 || NORTHBRIDGE_VIA_CX700 \
522 || NORTHBRIDGE_AMD_AMDK8 \
523 || NORTHBRIDGE_AMD_AMDFAM10 \
524 || SOUTHBRIDGE_VIA_VT8231)
526 This option enables additional SMBus (and SPD) debug messages.
528 Note: This option will increase the size of the coreboot image.
533 bool "Output verbose SMI debug messages"
535 depends on HAVE_SMI_HANDLER
537 This option enables additional SMI related debug messages.
539 Note: This option will increase the size of the coreboot image.
544 bool "Output verbose x86emu debug messages"
546 depends on PCI_OPTION_ROM_RUN_YABEL
548 This option enables additional x86emu related debug messages.
550 Note: This option will increase the size of the coreboot image.
554 config X86EMU_DEBUG_JMP
555 bool "Trace JMP/RETF"
557 depends on X86EMU_DEBUG
559 Print information about JMP and RETF opcodes from x86emu.
561 Note: This option will increase the size of the coreboot image.
565 config X86EMU_DEBUG_TRACE
566 bool "Trace all opcodes"
568 depends on X86EMU_DEBUG
570 Print _all_ opcodes that are executed by x86emu.
572 WARNING: This will produce a LOT of output and take a long time.
574 Note: This option will increase the size of the coreboot image.
578 config X86EMU_DEBUG_PNP
579 bool "Log Plug&Play accesses"
581 depends on X86EMU_DEBUG
583 Print Plug And Play accesses made by option ROMs.
585 Note: This option will increase the size of the coreboot image.
589 config X86EMU_DEBUG_DISK
592 depends on X86EMU_DEBUG
594 Print Disk I/O related messages.
596 Note: This option will increase the size of the coreboot image.
600 config X86EMU_DEBUG_PMM
603 depends on X86EMU_DEBUG
605 Print messages related to POST Memory Manager (PMM).
607 Note: This option will increase the size of the coreboot image.
612 config X86EMU_DEBUG_VBE
613 bool "Debug VESA BIOS Extensions"
615 depends on X86EMU_DEBUG
617 Print messages related to VESA BIOS Extension (VBE) functions.
619 Note: This option will increase the size of the coreboot image.
623 config X86EMU_DEBUG_INT10
624 bool "Redirect INT10 output to console"
626 depends on X86EMU_DEBUG
628 Let INT10 (i.e. character output) calls print messages to debug output.
630 Note: This option will increase the size of the coreboot image.
634 config X86EMU_DEBUG_INTERRUPTS
635 bool "Log intXX calls"
637 depends on X86EMU_DEBUG
639 Print messages related to interrupt handling.
641 Note: This option will increase the size of the coreboot image.
645 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
646 bool "Log special memory accesses"
648 depends on X86EMU_DEBUG
650 Print messages related to accesses to certain areas of the virtual
651 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
653 Note: This option will increase the size of the coreboot image.
657 config X86EMU_DEBUG_MEM
658 bool "Log all memory accesses"
660 depends on X86EMU_DEBUG
662 Print memory accesses made by option ROM.
663 Note: This also includes accesses to fetch instructions.
665 Note: This option will increase the size of the coreboot image.
669 config X86EMU_DEBUG_IO
670 bool "Log IO accesses"
672 depends on X86EMU_DEBUG
674 Print I/O accesses made by option ROM.
676 Note: This option will increase the size of the coreboot image.
681 bool "Built-in low-level shell"
684 If enabled, you will have a low level shell to examine your machine.
685 Put llshell() in your (romstage) code to start the shell.
686 See src/arch/i386/llshell/llshell.inc for details.
690 config LIFT_BSP_APIC_ID
694 # These probably belong somewhere else, but they are needed somewhere.
695 config AP_CODE_IN_CAR
699 config ENABLE_APIC_EXT_ID
703 config WARNINGS_ARE_ERRORS
707 config ID_SECTION_OFFSET
711 source src/Kconfig.deprecated_options