2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2009-2010 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 mainmenu "Coreboot Configuration"
27 This allows you to select certain advanced configuration options.
29 Warning: Only enable this option if you really know what you are
30 doing! You have been warned!
33 string "Local version string"
35 Append an extra string to the end of the coreboot version.
37 This can be useful if, for instance, you want to append the
38 respective board's hostname or some other identifying string to
39 the coreboot version number, so that you can easily distinguish
40 boot logs of different boards from each other.
43 string "CBFS prefix to use"
46 Select the prefix to all files put into the image. It's "fallback"
47 by default, "normal" is a common alternative.
53 This option allows you to select the compiler used for building
58 config COMPILER_LLVM_CLANG
62 config SCANBUILD_ENABLE
63 bool "Build with scan-build for static analysis"
66 Changes the build process to scan-build is used.
67 Requires scan-build in path.
69 config SCANBUILD_REPORT_LOCATION
70 string "Directory to put scan-build report in"
72 depends on SCANBUILD_ENABLE
74 Where the scan-build report should be stored
80 Enables the use of ccache for faster builds.
81 Requires ccache in path.
85 source src/mainboard/Kconfig
86 source src/arch/i386/Kconfig
91 source src/cpu/Kconfig
94 menu "HyperTransport setup"
95 depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
98 prompt "HyperTransport frequency"
99 default LIMIT_HT_SPEED_AUTO
101 This option sets the maximum permissible HyperTransport link
104 Use of this option will only limit the autodetected HT frequency.
105 It will not (and cannot) increase the frequency beyond the
108 This is primarily used to work around poorly designed or laid out
109 HT traces on certain motherboards.
111 config LIMIT_HT_SPEED_200
112 bool "Limit HT frequency to 200MHz"
113 config LIMIT_HT_SPEED_400
114 bool "Limit HT frequency to 400MHz"
115 config LIMIT_HT_SPEED_600
116 bool "Limit HT frequency to 600MHz"
117 config LIMIT_HT_SPEED_800
118 bool "Limit HT frequency to 800MHz"
119 config LIMIT_HT_SPEED_1000
120 bool "Limit HT frequency to 1.0GHz"
121 config LIMIT_HT_SPEED_1200
122 bool "Limit HT frequency to 1.2GHz"
123 config LIMIT_HT_SPEED_1400
124 bool "Limit HT frequency to 1.4GHz"
125 config LIMIT_HT_SPEED_1600
126 bool "Limit HT frequency to 1.6GHz"
127 config LIMIT_HT_SPEED_1800
128 bool "Limit HT frequency to 1.8GHz"
129 config LIMIT_HT_SPEED_2000
130 bool "Limit HT frequency to 2.0GHz"
131 config LIMIT_HT_SPEED_2200
132 bool "Limit HT frequency to 2.2GHz"
133 config LIMIT_HT_SPEED_2400
134 bool "Limit HT frequency to 2.4GHz"
135 config LIMIT_HT_SPEED_2600
136 bool "Limit HT frequency to 2.6GHz"
137 config LIMIT_HT_SPEED_AUTO
138 bool "Autodetect HT frequency"
142 prompt "HyperTransport downlink width"
143 default LIMIT_HT_DOWN_WIDTH_16
145 This option sets the maximum permissible HyperTransport
148 Use of this option will only limit the autodetected HT width.
149 It will not (and cannot) increase the width beyond the autodetected
152 This is primarily used to work around poorly designed or laid out HT
153 traces on certain motherboards.
155 config LIMIT_HT_DOWN_WIDTH_8
157 config LIMIT_HT_DOWN_WIDTH_16
162 prompt "HyperTransport uplink width"
163 default LIMIT_HT_UP_WIDTH_16
165 This option sets the maximum permissible HyperTransport
168 Use of this option will only limit the autodetected HT width.
169 It will not (and cannot) increase the width beyond the autodetected
172 This is primarily used to work around poorly designed or laid out HT
173 traces on certain motherboards.
175 config LIMIT_HT_UP_WIDTH_8
177 config LIMIT_HT_UP_WIDTH_16
183 source src/northbridge/Kconfig
184 comment "Southbridge"
185 source src/southbridge/Kconfig
187 source src/superio/Kconfig
189 source src/devices/Kconfig
193 config PCI_BUS_SEGN_BITS
197 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
201 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
233 config USE_PRINTK_IN_CAR
237 config USE_OPTION_TABLE
245 config MMCONF_SUPPORT_DEFAULT
249 config MMCONF_SUPPORT
260 source src/console/Kconfig
262 config HAVE_ACPI_RESUME
266 config ACPI_SSDTX_NUM
270 config HAVE_HARD_RESET
272 default y if BOARD_HAS_HARD_RESET
275 This variable specifies whether a given board has a hard_reset
276 function, no matter if it's provided by board code or chipset code.
278 config HAVE_INIT_TIMER
280 default n if UDELAY_IO
283 config HAVE_MAINBOARD_RESOURCES
287 config HAVE_OPTION_TABLE
291 This variable specifies whether a given board has a cmos.layout
292 file containing NVRAM/CMOS bit definitions.
293 It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
299 config HAVE_SMI_HANDLER
303 config PCI_IO_CFG_EXT
311 # TODO: Can probably be removed once all chipsets have kconfig options for it.
316 config USE_WATCHDOG_ON_BOOT
324 Build board-specific VGA code.
330 Enable Unified Memory Architecture for graphics.
337 #TODO Remove this option or make it useful.
338 config HAVE_LOW_TABLES
342 This Option is unused in the code. Since two boards try to set it to
343 'n', they may be broken. We either need to make the option useful or
344 get rid of it. The broken boards are:
348 config HAVE_HIGH_TABLES
352 This variable specifies whether a given northbridge has high table
354 It is set in northbridge/*/Kconfig.
355 Whether or not the high tables are actually written by coreboot is
356 configurable by the user via WRITE_HIGH_TABLES.
358 config HAVE_ACPI_TABLES
361 This variable specifies whether a given board has ACPI table support.
362 It is usually set in mainboard/*/Kconfig.
363 Whether or not the ACPI tables are actually generated by coreboot
364 is configurable by the user via GENERATE_ACPI_TABLES.
369 This variable specifies whether a given board has MP table support.
370 It is usually set in mainboard/*/Kconfig.
371 Whether or not the MP table is actually generated by coreboot
372 is configurable by the user via GENERATE_MP_TABLE.
374 config HAVE_PIRQ_TABLE
377 This variable specifies whether a given board has PIRQ table support.
378 It is usually set in mainboard/*/Kconfig.
379 Whether or not the PIRQ table is actually generated by coreboot
380 is configurable by the user via GENERATE_PIRQ_TABLE.
382 #These Options are here to avoid "undefined" warnings.
383 #The actual selection and help texts are in the following menu.
385 config GENERATE_ACPI_TABLES
387 default HAVE_ACPI_TABLES
389 config GENERATE_MP_TABLE
391 default HAVE_MP_TABLE
393 config GENERATE_PIRQ_TABLE
395 default HAVE_PIRQ_TABLE
397 config WRITE_HIGH_TABLES
399 default HAVE_HIGH_TABLES
403 config WRITE_HIGH_TABLES
404 bool "Write 'high' tables to avoid being overwritten in F segment"
405 depends on HAVE_HIGH_TABLES
409 bool "Generate Multiboot tables (for GRUB2)"
412 config GENERATE_ACPI_TABLES
413 depends on HAVE_ACPI_TABLES
414 bool "Generate ACPI tables"
417 Generate ACPI tables for this board.
421 config GENERATE_MP_TABLE
422 depends on HAVE_MP_TABLE
423 bool "Generate an MP table"
426 Generate an MP table (conforming to the Intel MultiProcessor
427 specification 1.4) for this board.
431 config GENERATE_PIRQ_TABLE
432 depends on HAVE_PIRQ_TABLE
433 bool "Generate a PIRQ table"
436 Generate a PIRQ table for this board.
445 prompt "Add a payload"
451 Select this option if you want to create an "empty" coreboot
452 ROM image for a certain mainboard, i.e. a coreboot ROM image
453 which does not yet contain a payload.
455 For such an image to be useful, you have to use 'cbfstool'
456 to add a payload to the ROM image later.
459 bool "An ELF executable payload"
461 Select this option if you have a payload image (an ELF file)
462 which coreboot should run as soon as the basic hardware
463 initialization is completed.
465 You will be able to specify the location and file name of the
470 config FALLBACK_PAYLOAD_FILE
471 string "Payload path and filename"
472 depends on PAYLOAD_ELF
473 default "payload.elf"
475 The path and filename of the ELF executable file to use as payload.
477 # TODO: Defined if no payload? Breaks build?
478 config COMPRESSED_PAYLOAD_LZMA
479 bool "Use LZMA compression for payloads"
481 depends on PAYLOAD_ELF
483 In order to reduce the size payloads take up in the ROM chip
484 coreboot can compress them using the LZMA algorithm.
486 config COMPRESSED_PAYLOAD_NRV2B
495 bool "Add a VGA BIOS image"
497 Select this option if you have a VGA BIOS image that you would
498 like to add to your ROM.
500 You will be able to specify the location and file name of the
503 config FALLBACK_VGA_BIOS_FILE
504 string "VGA BIOS path and filename"
506 default "vgabios.bin"
508 The path and filename of the file to use as VGA BIOS.
510 config FALLBACK_VGA_BIOS_ID
511 string "VGA device PCI IDs"
515 The comma-separated PCI vendor and device ID that would associate
516 your VGA BIOS to your video card.
520 In the above example 1106 is the PCI vendor ID (in hex, but without
521 the "0x" prefix) and 3230 specifies the PCI device ID of the
522 video card (also in hex, without "0x" prefix).
525 bool "Add an MBI image"
526 depends on NORTHBRIDGE_INTEL_I82830
528 Select this option if you have an Intel MBI image that you would
529 like to add to your ROM.
531 You will be able to specify the location and file name of the
534 config FALLBACK_MBI_FILE
535 string "Intel MBI path and filename"
539 The path and filename of the file to use as VGA BIOS.
544 depends on PCI_OPTION_ROM_RUN_YABEL
547 prompt "Show graphical bootsplash"
549 depends on PCI_OPTION_ROM_RUN_YABEL
551 This option shows a graphical bootsplash screen. The grapics are
552 loaded from the CBFS file bootsplash.jpg.
554 config FALLBACK_BOOTSPLASH_FILE
555 string "Bootsplash path and filename"
556 depends on BOOTSPLASH
557 default "bootsplash.jpg"
559 The path and filename of the file to use as graphical bootsplash
560 screen. The file format has to be jpg.
562 # TODO: Turn this into a "choice".
563 config FRAMEBUFFER_VESA_MODE
564 prompt "VESA framebuffer video mode"
567 depends on BOOTSPLASH
569 This option sets the resolution used for the coreboot framebuffer and
570 bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
571 some day make this a "choice".
573 config COREBOOT_KEEP_FRAMEBUFFER
574 prompt "Keep VESA framebuffer"
576 depends on BOOTSPLASH
578 This option keeps the framebuffer mode set after coreboot finishes
579 execution. If this option is enabled, coreboot will pass a
580 framebuffer entry in its coreboot table and the payload will need a
581 framebuffer driver. If this option is disabled, coreboot will switch
582 back to text mode before handing control to a payload.
588 # TODO: Better help text and detailed instructions.
590 bool "GDB debugging support"
593 If enabled, you will be able to set breakpoints for gdb debugging.
594 See src/arch/i386/lib/c_start.S for details.
596 config DEBUG_RAM_SETUP
597 bool "Output verbose RAM init debug messages"
599 depends on (NORTHBRIDGE_AMD_AMDFAM10 \
600 || NORTHBRIDGE_AMD_AMDK8 \
601 || NORTHBRIDGE_VIA_CN700 \
602 || NORTHBRIDGE_VIA_CX700 \
603 || NORTHBRIDGE_VIA_VX800 \
604 || NORTHBRIDGE_INTEL_E7501 \
605 || NORTHBRIDGE_INTEL_I440BX \
606 || NORTHBRIDGE_INTEL_I82810 \
607 || NORTHBRIDGE_INTEL_I82830 \
608 || NORTHBRIDGE_INTEL_I945)
610 This option enables additional RAM init related debug messages.
611 It is recommended to enable this when debugging issues on your
612 board which might be RAM init related.
614 Note: This option will increase the size of the coreboot image.
619 bool "Output verbose SMBus debug messages"
621 depends on (SOUTHBRIDGE_VIA_VT8237R \
622 || NORTHBRIDGE_VIA_VX800 \
623 || NORTHBRIDGE_VIA_CX700 \
624 || NORTHBRIDGE_AMD_AMDK8)
626 This option enables additional SMBus (and SPD) debug messages.
628 Note: This option will increase the size of the coreboot image.
633 bool "Output verbose SMI debug messages"
635 depends on HAVE_SMI_HANDLER
637 This option enables additional SMI related debug messages.
639 Note: This option will increase the size of the coreboot image.
644 bool "Output verbose x86emu debug messages"
646 depends on PCI_OPTION_ROM_RUN_YABEL
648 This option enables additional x86emu related debug messages.
650 Note: This option will increase the size of the coreboot image.
654 config X86EMU_DEBUG_JMP
655 bool "Trace JMP/RETF"
657 depends on X86EMU_DEBUG
659 Print information about JMP and RETF opcodes from x86emu.
661 Note: This option will increase the size of the coreboot image.
665 config X86EMU_DEBUG_TRACE
666 bool "Trace all opcodes"
668 depends on X86EMU_DEBUG
670 Print _all_ opcodes that are executed by x86emu.
672 WARNING: This will produce a LOT of output and take a long time.
674 Note: This option will increase the size of the coreboot image.
678 config X86EMU_DEBUG_PNP
679 bool "Log Plug&Play accesses"
681 depends on X86EMU_DEBUG
683 Print Plug And Play accesses made by option ROMs.
685 Note: This option will increase the size of the coreboot image.
689 config X86EMU_DEBUG_DISK
692 depends on X86EMU_DEBUG
694 Print Disk I/O related messages.
696 Note: This option will increase the size of the coreboot image.
700 config X86EMU_DEBUG_PMM
703 depends on X86EMU_DEBUG
705 Print messages related to POST Memory Manager (PMM).
707 Note: This option will increase the size of the coreboot image.
712 config X86EMU_DEBUG_VBE
713 bool "Debug VESA BIOS Extensions"
715 depends on X86EMU_DEBUG
717 Print messages related to VESA BIOS Extension (VBE) functions.
719 Note: This option will increase the size of the coreboot image.
723 config X86EMU_DEBUG_INT10
724 bool "Redirect INT10 output to console"
726 depends on X86EMU_DEBUG
728 Let INT10 (i.e. character output) calls print messages to debug output.
730 Note: This option will increase the size of the coreboot image.
734 config X86EMU_DEBUG_INTERRUPTS
735 bool "Log intXX calls"
737 depends on X86EMU_DEBUG
739 Print messages related to interrupt handling.
741 Note: This option will increase the size of the coreboot image.
745 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
746 bool "Log special memory accesses"
748 depends on X86EMU_DEBUG
750 Print messages related to accesses to certain areas of the virtual
751 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
753 Note: This option will increase the size of the coreboot image.
757 config X86EMU_DEBUG_MEM
758 bool "Log all memory accesses"
760 depends on X86EMU_DEBUG
762 Print memory accesses made by option ROM.
763 Note: This also includes accesses to fetch instructions.
765 Note: This option will increase the size of the coreboot image.
769 config X86EMU_DEBUG_IO
770 bool "Log IO accesses"
772 depends on X86EMU_DEBUG
774 Print I/O accesses made by option ROM.
776 Note: This option will increase the size of the coreboot image.
781 bool "Built-in low-level shell"
784 If enabled, you will have a low level shell to examine your machine.
785 Put llshell() in your (romstage) code to start the shell.
786 See src/arch/i386/llshell/llshell.inc for details.
790 config LIFT_BSP_APIC_ID
794 # These probably belong somewhere else, but they are needed somewhere.
795 config AP_CODE_IN_CAR
803 config ENABLE_APIC_EXT_ID
807 config WARNINGS_ARE_ERRORS
811 config ID_SECTION_OFFSET
815 source src/Kconfig.deprecated_options