15 exec_op/add_op_b.vhd \
16 exec_op/and_op_b.vhd \
18 exec_op/shift_op_b.vhd \
19 exec_op/xor_op_b.vhd \
24 extension_interrupt_b.vhd \
25 extension_interrupt.vhd \
27 extension_uart_b.vhd \
28 extension_uart_pkg.vhd \
30 extension_7seg_b.vhd \
31 extension_7seg_pkg.vhd \
34 extension_imp_pkg.vhd \
54 writeback_stage_b.vhd \
57 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
62 all: generated/$(NAME).mcs
69 rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
70 rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
71 rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
72 rm -f *.bld *.ncd *.twr *.drc
73 rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
74 rm -rf xst $(NAME).prj
76 rm -rf xlnx_auto_0_xdb _xmsgs
78 #Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
80 # create an ISE project file from the list of VHDL files
81 $(NAME).prj: $(PROJ_VHDL)
82 echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
84 bitfile: generated step0 step1 step2 step3 step4 step5
87 xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
89 ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
91 map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
93 par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
95 trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
97 bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
99 generated/$(NAME).bit: bitfile
101 jtag: generated/$(NAME).bit
102 impact -batch ISE_scripts/loadjtag.cmds
104 jtag_brv1: s3e_bootrom_v1.bit
105 impact -batch ISE_scripts/loadjtag_brv1.cmds
107 mcs: generated/$(NAME).bit
108 impact -batch ISE_scripts/makeprom.cmds
110 generated/$(NAME).mcs: mcs
112 load: generated/$(NAME).mcs
113 impact -batch ISE_scripts/loadprom.cmds