spartan3e/Makefile

   1 SHELL := bash
   2
   3 VHDL_DIR := ../cpu/src
   4 PROJ_VHDL = \
   5         core_top_s3e.vhd \
   6         alu_b.vhd \
   7         alu_pkg.vhd \
   8         alu.vhd \
   9         common_pkg.vhd \
  10         core_pkg.vhd \
  11         decoder_b.vhd \
  12         decoder.vhd \
  13         decode_stage_b.vhd \
  14         decode_stage.vhd \
  15         exec_op/add_op_b.vhd \
  16         exec_op/and_op_b.vhd \
  17         exec_op/or_op_b.vhd \
  18         exec_op/shift_op_b.vhd \
  19         exec_op/xor_op_b.vhd \
  20         exec_op.vhd \
  21         execute_stage_b.vhd \
  22         execute_stage.vhd \
  23         extension_b.vhd \
  24         extension_interrupt_b.vhd \
  25         extension_interrupt.vhd \
  26         extension_pkg.vhd \
  27         extension_uart_b.vhd \
  28         extension_uart_pkg.vhd \
  29         extension_uart.vhd \
  30         extension_7seg_b.vhd \
  31         extension_7seg_pkg.vhd \
  32         extension_7seg.vhd \
  33         extension_imp_b.vhd \
  34         extension_imp_pkg.vhd \
  35         extension_imp.vhd \
  36         extension_timer_b.vhd \
  37         extension_timer_pkg.vhd \
  38         extension_timer.vhd \
  39         extension_lcd_b.vhd \
  40         extension_lcd_pkg.vhd \
  41         extension_lcd.vhd \
  42         extension.vhd \
  43         fetch_stage_b.vhd \
  44         fetch_stage.vhd \
  45         mem_pkg.vhd \
  46         r2_w_ram_b.vhd \
  47         r2_w_ram.vhd \
  48         rom_b.vhd \
  49         rom.vhd \
  50         rs232_rx_arc.vhd \
  51         rs232_rx.vhd \
  52         rs232_tx_arc.vhd \
  53         rs232_tx.vhd \
  54         ram_xilinx.vhd \
  55         ram_xilinx_b.vhd \
  56         r_w_ram_b.vhd \
  57         r_w_ram.vhd \
  58         rw_r_ram_b.vhd \
  59         rw_r_ram.vhd \
  60         writeback_stage_b.vhd \
  61         writeback_stage.vhd
  62
  63 PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
  64
  65 NAME := core_top
  66
  67
  68 all: generated/$(NAME).mcs
  69
  70 generated:
  71         rm -rf generated
  72         mkdir generated
  73
  74 clean:
  75         rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
  76         rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
  77         rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
  78         rm -f *.bld *.ncd *.twr *.drc
  79         rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
  80         rm -rf xst $(NAME).prj
  81         rm -rf generated/
  82         rm -rf xlnx_auto_0_xdb _xmsgs
  83
  84 #Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
  85
  86 # create an ISE project file from the list of VHDL files
  87 $(NAME).prj: $(PROJ_VHDL)
  88         echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
  89
  90 bitfile: generated step0 step1 step2 step3 step4 step5
  91
  92 step0: $(NAME).prj
  93         xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
  94 step1:
  95         ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
  96 step2:
  97         map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
  98 step3:
  99         par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
 100 step4:
 101         trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
 102 step5:
 103         bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
 104
 105 generated/$(NAME).bit: bitfile
 106
 107 jtag: generated/$(NAME).bit
 108         impact -batch ISE_scripts/loadjtag.cmds
 109
 110 jtag_brv1: s3e_bootrom_v1.bit
 111         impact -batch ISE_scripts/loadjtag_brv1.cmds
 112
 113 mcs: generated/$(NAME).bit
 114         impact -batch ISE_scripts/makeprom.cmds
 115
 116 generated/$(NAME).mcs: mcs
 117
 118 load: generated/$(NAME).mcs
 119         impact -batch ISE_scripts/loadprom.cmds
 120
 121 impact:
 122         impact
 123
 124 ise: $(NAME).prj
 125         ise