1 package require ::quartus::project
3 set need_to_close_project 0
6 # Check that the right project is open
7 if {[is_project_open]} {
8 if {[string compare $quartus(project) "calc"]} {
9 puts "Project calc is not open"
10 set make_assignments 0
13 # Only open if not already open
14 if {[project_exists calc]} {
15 project_open -revision calc calc
17 project_new -revision calc calc
19 set need_to_close_project 1
23 if {$make_assignments} {
24 set_global_assignment -name FAMILY Stratix
25 set_global_assignment -name DEVICE %DEVICE%
26 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
27 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
28 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
29 set_global_assignment -name MISC_FILE "calc.dpf"
30 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
31 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
32 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
34 set_global_assignment -name TOP_LEVEL_ENTITY parser
35 set_global_assignment -name VHDL_FILE ../../src/gen_pkg.vhd
36 set_global_assignment -name VHDL_FILE ../../src/math_pkg.vhd
37 set_global_assignment -name VHDL_FILE ../../src/alu.vhd
38 set_global_assignment -name VHDL_FILE ../../src/parser.vhd
41 set_location_assignment PIN_N3 -to sys_clk
42 set_location_assignment PIN_AF17 -to sys_res_n
48 if {$need_to_close_project} {