4 ;=========================================================================================
5 ; 4.1 Controller Device
6 ;=========================================================================================
7 #set MB91464A 2 ; MB91460 series
9 #set MB91467B 10 ; MB91460 series
11 #set MB91467C 11 ; MB91460 series
13 #set MB91467D 4 ; MB91460 series
15 #set MB91469G 6 ; MB91460 series
17 #set MB91465K 3 ; MB91460 series
19 #set MB91463N 8 ; MB91460 series
21 #set MB91461R 1 ; MB91460 series
22 #set MB91467R 5 ; MB91460 series
24 #set MB91465X 9 ; MB91460 series
26 #set others 7 ; MB91460 series
29 #set DEVICE MB91465K ; <<< select device
31 #set BOOT_FLASH_SEC OFF ; <<< BOOT and Flash Security Vector
32 ;=========================================================================================
33 ; 4.3 Stack Type and Stack Size
34 ;=========================================================================================
36 #set USRSTACK 0 ; user stack: for main program
37 #set SYSSTACK 1 ; system stack: for main program and
40 #set STACKUSE SYSSTACK ; <<< set active stack
42 #set STACK_RESERVE ON ; <<< reserve stack area in
44 #set STACK_SYS_SIZE 0x400-4 ; <<< byte size of System stack
45 #set STACK_USR_SIZE 0x2 ; <<< byte size of User stack
47 ; - If the active stack is set to SYSSTACK, it is used for main program and interrupts.
48 ; In this case, the user stack could be set to a dummy size. If the active stack is
49 ; set to user stack, it is used for the main program but the system stack is
50 ; automatically activated, if an interrupt is serviced. Both stack areas must have a
52 ; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved in this module.
53 ; Otherwise, they have to be reserved in other modules. If STACK_RESERVE is OFF, the
54 ; size definitions STACK_SYS_SIZE and STACK_USR_SIZE have no meaning.
55 ; - Even if they are reverved in other modules, they are still initialised in this
58 ; Note: Several library functions require quite a big stack (due to ANSI).
59 ; Check the stack information files (*.stk) in the LIB\911 directory.
61 ;=========================================================================================
62 ; 4.4 Copy code from Flash to I-RAM
63 ;=========================================================================================
65 #set I_RAM ON ; <<< select if code in section IRAM
67 ; If this option is activated code located in the section IRAM is copied during startup
68 ; from ROM to the instruction-RAM. The code is linked for the instruction-RAM.
70 ;=========================================================================================
71 ; 4.7 Clock Configuration
72 ;=========================================================================================
73 ;=========================================================================================
74 ; 4.7.1 Clock Selection
75 ;=========================================================================================
80 ; Sub-oscillation input: 32 kHz
81 #set SUB_32KHZ_CPU__32KHZ_PER_32KHZ_EXT_32KHZ_CAN__2MHZ 0x11
83 ; Oscillation input: 4 MHz
84 #set PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ 0x23
86 ; MB91461R only: Oscillation input: 10 MHz
87 #set PLL_10MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x41
89 ; MB91461R only: Oscillation input: 20 MHz
90 #set PLL_20MHZ_CPU__60MHZ_PER_20MHZ_EXT_30MHZ_CAN_20MHZ 0x51
97 #set CLOCKSPEED PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
98 ; ; <<< Select clock configuration
100 ;=========================================================================================
101 ; 4.7.2 Select Clock Modulator
102 ;=========================================================================================
104 #set CLOMO OFF ; <<< Enable /disable clock modulator
106 #set CMPR 0x026F ; <<< Ref. to the data sheet, CMPR
108 ; Please refer to the data sheet of the device if you enable clock modulation. The
109 ; register CMPR dependant on the PLL-Clock.
111 ; Note: If the CLKCAN source is set either to main oscillator or to PLL output then the
112 ; clock for the CAN is not influenced by the clock modulation. If the CLKCAN
113 ; source is set CPU clock (CLKB) then the clock for the CAN is also modulated (if
114 ; the clock modulator is enabled).
116 ; Note: If the clock modulator is enabled, the wait states of the internal flash wait
117 ; states must be adapted to maximum frequency. Please check the wait states
120 ; Note: This feature is not supported by every device, e.g. MB91461. Please check the
123 ;=========================================================================================
124 ; 4.8 External Bus Interface
126 ; The rest of the configuration is only applicable for devices with an external bus
129 ; If the device does not offer an external bus interface, the configuration can be
130 ; stoped at this point.
132 ;=========================================================================================
133 ; 5 Definition of Configurations
134 ;=========================================================================================
136 #set NOCLOCK 0 ; do not touch CKSCR register
137 #set MAINCLOCK 1 ; select main clock
138 ; ; MB91461R : 1/4 of oscillation input
139 ; ; Others: 1/2 of oscillation input
140 #set MAINPLLCLOCK 2 ; select main clock with PLL
141 #set SUBCLOCK 3 ; select subclock (if available)
143 #set PSCLOCK_CLKB 0x00 ; select core clock (initial)
144 #set PSCLOCK_PLL 0x10 ; select PLL output (x)
145 #set PSCLOCK_MAIN 0x30 ; select Main Oscillation
147 ;=========================================================================================
148 ; 5.2 CLOCKSPEED == NO_CLOCK
149 ;=========================================================================================
151 #if (CLOCKSPEED == NO_CLOCK )
152 #set CLOCKSOURCE NOCLOCK
154 ;=========================================================================================
155 ; 5.5 CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ
156 ;=========================================================================================
158 #if (CLOCKSPEED == PLL_4MHZ__CPU__64MHZ_PER_16MHZ_EXT_32MHZ_CAN_16MHZ )
160 ; Start restriction; Maximum frequency
161 #if (DEVICE == MB91461R)
162 #error: Frequency is not supported by this device.
166 #set CLOCKSOURCE MAINPLLCLOCK ; Clocksource
167 #set ENABLE_SUBCLOCK OFF ; Subclock: ON/OFF
168 #set PLLSPEED 0x010F ; 0x48Ch, 0x48Dh: PLLDIVM/N ; 64 MHz
169 #set DIV_G 0x0F ; 0x48Eh: PLLDIVG;
170 #set MUL_G 0x0F ; 0x48Fh: PLLMULG;
172 #set CPUCLOCK 0x00 ; 0x486h: DIV0R_B; => /1 ; 64 MHz
173 #set PERCLOCK 0x03 ; 0x486h: DIV0R_P; => /4 ; 16 MHz
174 #set EXTBUSCLOCK 0x01 ; 0x487h: DIV1R_T; => /2 ; 32 MHz
176 #set PSCLOCKSOURCE PSCLOCK_PLL ; 0x4C0h: CANPRE; => PLLx ; 128 MHz
177 #set PSDVC 0x07 ; 0x4C0h: CANPRE_DVC; => /8 ; 16 MHz
178 #set CANCLOCK 0x00 ; 0x4C1h: CANCKD; all CAN Clocks enabled
180 #set REGULATORSEL 0x06 ; 0x4CEh: REGSEL;
181 #set REGULATORCTRL 0x00 ; 0x4CFh: REGCTR;
183 #set FLASHCONTROL 0x032 ; 0x7002h: FCHCR;
184 #set FLASHREADT 0xC413 ; 0x7004h: FMWT;
185 #set FLASHMWT2 0x10 ; 0x7006h: FMWT2;
188 ;=========================================================================================
189 ; 6 Section and Data Declaration
190 ;=========================================================================================
195 ;=========================================================================================
196 ; 6.1 Define Stack Size
197 ;=========================================================================================
198 .SECTION SSTACK, STACK, ALIGN=4
199 #if STACK_RESERVE == ON
200 .EXPORT __systemstack, __systemstack_top
202 .RES.B STACK_SYS_SIZE
206 .SECTION USTACK, STACK, ALIGN=4
207 #if STACK_RESERVE == ON
208 .EXPORT __userstack, __userstack_top
210 .RES.B STACK_USR_SIZE
214 ;=========================================================================================
215 ; 6.2 Define Sections
216 ;=========================================================================================
217 .section DATA, data, align=4
218 .section INIT, data, align=4
219 .section IRAM, code, align=4
220 .section CONST, const, align=4
221 .section INTVECT, const, align=4
228 #if (BOOT_FLASH_SEC == OFF)
237 ;-----------------------------------------------------------------------------------------
238 ; MACRO Clear RC Watchdog
239 ;-----------------------------------------------------------------------------------------
240 #macro ClearRCwatchdog
241 LDI #0x4C7,R7 ; clear RC watchdog
244 ;-----------------------------------------------------------------------------------------
246 ;-----------------------------------------------------------------------------------------
247 #macro wait_loop loop_number
254 .section CODE, code, align=4
255 .section CODE_START, code, align=4
256 #pragma section CODE=IRAM,attr=CODE
259 ;=========================================================================================
261 ;=========================================================================================
262 __start: ; start point
266 ANDCCR #0xEF ; disable interrupts
267 STILM #31 ; set interrupt level to low prior
268 ClearRCwatchdog ; clear harware watchdog
270 ;=========================================================================================
271 ; 7.1 Initialise Stack Pointer and Table Base Register
272 ;=========================================================================================
273 #if STACKUSE == SYSSTACK
275 LDI #__userstack_top, SP ; initialize SP
277 LDI #__systemstack_top, SP ; initialize SP
280 #if STACKUSE == USRSTACK
282 LDI #__systemstack_top, SP ; initialize SP
284 LDI #__userstack_top, SP ; initialize SP
287 LDI #INTVECT, R0 ; set Table Base
291 #if (CLOCKSOURCE != NOCLOCK)
292 ;=========================================================================================
293 ; 7.2 Check for CSV reset and set CSV
294 ;=========================================================================================
295 ; Start restriction; No clock supervisor (CSV)
296 #if (DEVICE != MB91461R) && (DEVICE != MB91467R) && (DEVICE != MB91463N)
298 LDI:20 #0x04AD, R0 ; CSVCR
299 BORL #0x8, @R0 ; Enable Main Osc CSV
300 BTSTH #0x4, @R0 ; Check for Main Osc missing
301 BEQ NoMAINCSVreset ; Main osc available -> branch
303 BANDL #0x7, @R0 ; Disable Main Osc CSV
305 LDI #noClockStartup, R0 ; Main Clock missing -> no
306 JMP @R0 ; clock startup
311 BORL #0x4, @R0 ; Enable Sub Osc CSV
312 BTSTH #0x2, @R0 ; Check for Sub Osc missing
313 BEQ NoSUBCSVreset ; Sub osc available -> branch
315 BANDL #0xB, @R0 ; Disable Sub Osc SCSV
316 #if (CLOCKSOURCE == SUBCLOCK)
317 LDI #noClockStartup, R0 ; Sub Clock missing -> no
318 JMP @R0 ; clock startup
322 ;=========================================================================================
323 ; 7.3 Check Clock Condition
324 ;=========================================================================================
325 LDI #0x484, R0 ; Check for Default Values
330 ;=========================================================================================
331 ; 7.4 Restore Default Settings after Reset
332 ;=========================================================================================
333 ;=========================================================================================
334 ; 7.4.1 Disable Clock Modulator
335 ;=========================================================================================
336 LDI #0x04BB, R0 ; Clock Modulator Control Reg
337 BANDL #0xD, @R0 ; Disable Frequency modulation
339 BTSTL #8, @R0 ; Wait until Frequency modulation
340 BNE FMODwait ; is disabled
342 BANDL #0xE, @R0 ; Power down clock modulator
344 ;=========================================================================================
345 ; 7.4.2 Check if running on Sub Clock, change to Main Clock
346 ;=========================================================================================
347 LDI:20 #0x0484,R12 ; Check if running on sub clock
354 LDI:20 #0x04CC,R12 ; Check if Main Clock is stopped
358 BANDL #0xE, @R12 ; Start Main Oscillation
360 LDI #0x4C8, R0 ; Main Stabilisation Wait Time
361 LDI #0x04, R1 ; 32.7 ms
365 mainStabTime: ; Wait for stabilisation time
366 ClearRCwatchdog ; clear harware watchdog
373 LDI:20 #0x0484, R12 ; disable sub clock as source
374 BANDL #0xD, @R12 ; Clock source = 0x01 (Main/2)
377 ;=========================================================================================
378 ; 7.4.3 Disable Sub Clock
379 ;=========================================================================================
380 #if ENABLE_SUBCLOCK != ON
381 LDI #0x0484, R0 ; Clock source control reg CLKR
382 BANDL #0x7, @R0 ; Disable PLL
385 ;=========================================================================================
386 ; 7.4.4 Check if running on PLL, Gear Down PLL
387 ;=========================================================================================
388 LDI:20 #0x0484,R12 ; Check if running on PLL
395 LDI:20 #0x0490, R11 ; clear flags
399 STB R1, @R11 ; Set Flag for Simulator; no Effekt on
402 BANDL #0xC, @R12 ; disable PLL as clock source
403 ; Clock Source = 0x00 (Main/2)
405 LDI:20 #0x048E,R12 ; check if DivG != 0
412 ClearRCwatchdog ; clear harware watchdog
413 BTSTL #4, @R11 ; Gear Down
416 LDI #0x00,R1 ; Clear Flags
420 ;=========================================================================================
422 ;=========================================================================================
423 LDI #0x0484, R0 ; Clock source control reg CLKR
424 BANDL #0xB, @R0 ; Disable PLL
426 ;=========================================================================================
427 ; 7.4.6 Set to Main Clock
428 ;=========================================================================================
429 LDI:20 #0x0484,R12 ; Check if running on PLL
430 BANDL #0xC, @R12 ; disable PLL as clock source
431 ; Clock Source = 0x00 (Main/2)
434 ;=========================================================================================
435 ; 7.5 Set Memory Controller
436 ;=========================================================================================
437 ; Start restriction; No embedded flash
438 #if DEVICE != MB91461R
440 LDI #0x7002, R1 ; FLASH Controller Reg.
441 LDI #FLASHCONTROL, R2 ; Flash Controller Settings
442 STH R2, @R1 ; set register
443 LDI #0x7004, R1 ; FLASH Memory Wait Timing Reg.
444 LDI #FLASHREADT, R2 ; wait settings
445 STH R2, @R1 ; set register
446 LDI #0x7006, R1 ; FLASH Memory Wait Timing Reg.
447 LDI #FLASHMWT2, R2 ; wait settings
448 STB R2, @R1 ; set register
452 ;=========================================================================================
454 ;=========================================================================================
455 ;=========================================================================================
456 ; 7.6.1 Set Voltage Regulator Settings
457 ;=========================================================================================
458 ; Start restriction; No regulator settings
459 #if DEVICE != MB91461R
461 LDI #0x04CF, R0 ; REGCTR
462 LDI #REGULATORCTRL, R1
465 LDI #0x04CE, R0 ; REGSEL
466 LDI #REGULATORSEL, R1
470 ;=========================================================================================
471 ; 7.6.2 Power on Clock Modulator - Clock Modulator Part I
472 ;=========================================================================================
474 LDI #0x04BB, R0 ; Clock Modulator Control Reg
475 LDI #0x11, R1 ; Load value to Power on CM
476 ORB R1, @R0 ; Power on clock modulaor
479 ;=========================================================================================
480 ; 7.6.3 Set CLKR Register w/o Clock Mode
481 ;=========================================================================================
482 ; Set Clock source (Base Clock) for the three clock tree selections
483 ; This select Base clock is used to select afterwards the 3
484 ; Clocks for the diffenrent internal trees.
485 ; When PLL is used, first pll multiplication ratio is set and PLL is
486 ; enabled. After waiting the PLL stabilisation time via timebase
487 ; timer, PLL clock is selected as clock source.
488 LDI #0x048C, R0 ; PLL Cntl Reg. PLLDIVM/N
492 LDI #0x048E, R0 ; PLL Cntl Reg. PLLDIVG
496 LDI #0x048F, R0 ; PLL Cntl Reg. PLLMULG
500 ;=========================================================================================
502 ;=========================================================================================
503 #if ( ( CLOCKSOURCE == MAINPLLCLOCK ) || ( PSCLOCKSOURCE == PSCLOCK_PLL ) )
504 LDI #0x0484, R0 ; Clock source control reg CLKR
505 LDI #0x04, R1 ; Use PLL x1, enable PLL
506 ORB R1, @R0 ; store data to CLKR register
509 ;=========================================================================================
510 ; 7.6.5 Wait for PLL oscillation stabilisation
511 ;=========================================================================================
512 #if ((CLOCKSOURCE==MAINPLLCLOCK)||(PSCLOCKSOURCE==PSCLOCK_PLL))
513 LDI #0x0482, R12 ; TimeBaseTimer TBCR
514 LDI #0x00, R1 ; set 1024 us @ 2 MHz
517 BANDH #7, @R12 ; clear interrupt flag
519 LDI #0x0483, R0 ; clearTimeBaseTimer CTBR
525 BANDH #7, @R12 ; clear interrupt flag
526 BORH #8, @R12 ; set interrupt flag for simulator
529 ClearRCwatchdog ; clear harware watchdog
534 ;=========================================================================================
536 ;=========================================================================================
537 ;=========================================================================================
538 ; 7.6.6.1 Set CPU and peripheral clock
539 ;=========================================================================================
540 ; CPU and peripheral clock are set in one register
541 LDI #0x0486, R2 ; Set DIVR0 (CPU-clock (CLKB)
542 LDI #((CPUCLOCK << 4) + PERCLOCK), R3 ; Load CPU clock setting
544 ;=========================================================================================
545 ; 7.6.6.2 Set External Bus interface clock
546 ;=========================================================================================
547 ; set External Bus clock
548 ; Be aware to do smooth clock setting, to avoid wrong clock setting
549 ; Take care, always write 0 to the lower 4 bits of DIVR1 register
550 LDI #0x0487, R2 ; Set DIVR1
551 LDI #(EXTBUSCLOCK << 4), R3 ; Load Peripheral clock setting
554 ;=========================================================================================
555 ; 7.6.6.3 Set CAN clock prescaler
556 ;=========================================================================================
557 ; Set CAN Prescaler, only clock relevant parameter
558 LDI #0x04C0, R0 ; Set CAN ClockParameter Register
559 LDI #(PSCLOCKSOURCE + PSDVC), R1 ; Load Divider
560 STB R1, @R0 ; Set Divider
562 LDI #0x04c1, R0 ; Set CAN Clock enable Register
563 LDI #CANCLOCK, R1 ; Load CANCLOCK
564 STB R1, @R0 ; set CANCLOCK
566 ;=========================================================================================
567 ; 7.6.7 Switch to PLL Mode
568 ;=========================================================================================
569 #if ( (CLOCKSOURCE == MAINPLLCLOCK) )
572 LDI #0x0490, R0 ; PLL Ctrl Register
574 STB R1, @R0 ; Clear Flag
576 STB R1, @R0 ; Set Flag for Simulator; no Effekt on
579 LDI #0x0484, R3 ; Clock source control reg CLKR
580 BORL #0x2, @R3 ; enable PLL as clock source
584 ClearRCwatchdog ; clear harware watchdog
585 LDUB @R0, R2 ; LOAD PLLCTR to R2
586 AND R1, R2 ; GRUP, counter reach 0
590 STB R1, @R0 ; Clear Gear-Up Flag
595 ;=========================================================================================
596 ; 7.6.8 Enable Frequncy Modulation - Clock Modulator Part II
597 ;=========================================================================================
598 #if CLOMO == ON ; Only applicable if Modulator is on
599 LDI #0x04B8, R0 ; Clock Modulation Parameter Reg
600 LDI #CMPR, R1 ; Load CMP value
601 STH R1, @R0 ; Store CMP value in CMPR
603 LDI #0x04BB, R0 ; Clock Modulator Control Reg
604 LDI #0x13, R1 ; Load value to FM on CM
612 ;=========================================================================================
613 ; 7.8 Copy code from Flash to I-RAM
614 ;=========================================================================================
618 LDI #sizeof(IRAM), R13
630 ;=========================================================================================
632 ;=========================================================================================
633 ;=========================================================================================
635 ;=========================================================================================
637 ; According to ANSI, the DATA section must be cleared during start-up
639 LDI #sizeof DATA &~0x3, R1
648 LDI:8 #sizeof DATA & 0x3, R1
649 LDI #DATA + (sizeof DATA & ~0x3), R13
660 ;=========================================================================================
661 ; 7.11 Copy Init section from ROM to RAM
662 ;=========================================================================================
664 ; All initialised data's (e.g. int i=1) must be stored in ROM/FLASH area.
666 ; The Application must copy the Section (Init) into the RAM area.
669 LDI #sizeof(INIT), R2
695 ;=========================================================================================
696 ; 7.14 call main routine
697 ;=========================================================================================
698 ClearRCwatchdog ; clear harware watchdog
699 LDI:8 #0, r4 ; Set the 1st parameter for main to 0.
701 LDI:8 #0, r5 ; Set the 2nd parameter for main to 0.
702 ;=========================================================================================
703 ; 7.15 Return from main function
704 ;=========================================================================================