2 * This file is part of the coreinfo project.
4 * It is derived from the x86info project, which is GPLv2-licensed.
6 * Copyright (C) 2001-2007 Dave Jones <davej@codemonkey.org.uk>
7 * Copyright (C) 2008 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <arch/rdtsc.h>
26 #define VENDOR_INTEL 0x756e6547
27 #define VENDOR_AMD 0x68747541
28 #define VENDOR_CYRIX 0x69727943
29 #define VENDOR_IDT 0x746e6543
30 #define VENDOR_GEODE 0x646f6547
31 #define VENDOR_RISE 0x52697365
32 #define VENDOR_RISE2 0x65736952
33 #define VENDOR_SIS 0x20536953
35 /* CPUID 0x00000001 EDX flags */
36 const char *generic_cap_flags[] = {
37 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
38 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
39 "pat", "pse36", "psn", "clflsh", NULL, "ds", "acpi", "mmx",
40 "fxsr", "sse", "sse2", "ss", "ht", "tm", NULL, "pbe"
43 /* CPUID 0x00000001 ECX flags */
44 const char *intel_cap_generic_ecx_flags[] = {
45 "sse3", NULL, NULL, "monitor", "ds-cpl", "vmx", NULL, "est",
46 "tm2", "ssse3", "cntx-id", NULL, NULL, "cx16", "xTPR", NULL,
47 NULL, NULL, "dca", NULL, NULL, NULL, NULL, NULL,
48 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
51 /* CPUID 0x80000001 EDX flags */
52 const char *intel_cap_extended_edx_flags[] = {
53 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
54 NULL, NULL, NULL, "SYSCALL", NULL, NULL, NULL, NULL,
55 NULL, NULL, NULL, NULL, "xd", NULL, NULL, NULL,
56 NULL, NULL, NULL, NULL, NULL, "em64t", NULL, NULL,
59 /* CPUID 0x80000001 ECX flags */
60 const char *intel_cap_extended_ecx_flags[] = {
61 "lahf_lm", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
62 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
63 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
64 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
67 const char *amd_cap_generic_ecx_flags[] = {
68 "sse3", NULL, NULL, "mwait", NULL, NULL, NULL, NULL,
69 NULL, NULL, NULL, NULL, NULL, "cmpxchg16b", NULL, NULL,
70 NULL, NULL, NULL, NULL, NULL, NULL, NULL, "popcnt",
71 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
74 const char *amd_cap_extended_edx_flags[] = {
75 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
76 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
77 "pat", "pse36", NULL, "mp", "nx", NULL, "mmxext", "mmx",
78 "fxsr", "ffxsr", "page1gb", "rdtscp",
79 NULL, "lm", "3dnowext", "3dnow"
80 }; /* "mp" defined for CPUs prior to AMD family 0xf */
82 const char *amd_cap_extended_ecx_flags[] = {
83 "lahf/sahf", "CmpLegacy", "svm", "ExtApicSpace",
84 "LockMovCr0", "abm", "sse4a", "misalignsse",
85 "3dnowPref", "osvw", "ibs", NULL, "skinit", "wdt", NULL, NULL,
86 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
87 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
90 static unsigned long vendor;
91 static unsigned int cpu_khz;
93 void decode_flags(WINDOW *win, unsigned long reg, const char **flags, int *row)
100 for (i = 0; i < 32; i++) {
101 if (flags[i] == NULL)
105 wprintw(win, "%s ", flags[i]);
107 if (i && (i % 16) == 0) {
116 static void get_features(WINDOW *win, int *row)
118 unsigned long eax, ebx, ecx, edx;
121 wmove(win, lrow++, 1);
122 wprintw(win, "Features: ");
124 docpuid(0x00000001, &eax, &ebx, &ecx, &edx);
125 decode_flags(win, edx, generic_cap_flags, &lrow);
131 wmove(win, lrow++, 1);
132 wprintw(win, "AMD Extended Flags: ");
133 decode_flags(win, ecx, amd_cap_generic_ecx_flags, &lrow);
134 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
135 decode_flags(win, edx, amd_cap_extended_edx_flags, &lrow);
136 decode_flags(win, ecx, amd_cap_extended_ecx_flags, &lrow);
139 wmove(win, lrow++, 1);
140 wprintw(win, "Intel Extended Flags: ");
141 decode_flags(win, ecx, intel_cap_generic_ecx_flags, &lrow);
142 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
143 decode_flags(win, edx, intel_cap_extended_edx_flags, &lrow);
144 decode_flags(win, ecx, intel_cap_extended_ecx_flags, &lrow);
151 static void do_name(WINDOW *win, int row)
154 unsigned long eax, ebx, ecx, edx;
159 for (i = 0x80000002; i <= 0x80000004; i++) {
160 docpuid(i, &eax, &ebx, &ecx, &edx);
165 for (t = 0; t < 4; t++)
166 *p++ = eax >> (8 * t);
167 for (t = 0; t < 4; t++)
168 *p++ = ebx >> (8 * t);
169 for (t = 0; t < 4; t++)
170 *p++ = ecx >> (8 * t);
171 for (t = 0; t < 4; t++)
172 *p++ = edx >> (8 * t);
175 mvwprintw(win, row, 1, "Processor: %s", name);
178 int cpuinfo_module_redraw(WINDOW *win)
180 unsigned long eax, ebx, ecx, edx;
185 print_module_title(win, "CPU Information");
187 docpuid(0, NULL, &vendor, NULL, NULL);
203 vstr = "NatSemi Geode";
217 mvwprintw(win, row++, 1, "Vendor: %s", vstr);
221 docpuid(0x00000001, &eax, &ebx, &ecx, &edx);
223 mvwprintw(win, row++, 1, "Family: %X", (eax >> 8) & 0x0f);
224 mvwprintw(win, row++, 1, "Model: %X",
225 ((eax >> 4) & 0xf) | ((eax >> 16) & 0xf) << 4);
227 mvwprintw(win, row++, 1, "Stepping: %X", eax & 0xf);
229 if (vendor == VENDOR_AMD) {
230 docpuid(0x80000001, &eax, &ebx, &ecx, &edx);
231 brand = ((ebx >> 9) & 0x1f);
233 mvwprintw(win, row++, 1, "Brand: %X", brand);
237 mvwprintw(win, row++, 1, "CPU Speed: %d Mhz", cpu_khz / 1000);
239 mvwprintw(win, row++, 1, "CPU Speed: Error");
242 get_features(win, &row);
247 unsigned int getticks(void)
249 unsigned long long start, end;
251 /* Read the number of ticks during the period. */
256 return (unsigned int)((end - start) / 100);
259 int cpuinfo_module_init(void)
261 cpu_khz = getticks();
265 struct coreinfo_module cpuinfo_module = {
267 .init = cpuinfo_module_init,
268 .redraw = cpuinfo_module_redraw,