2 * regalloc2.c: Global Register Allocator
5 * Zoltan Varga (vargaz@gmail.com)
7 * (C) 2007 Novell, Inc.
11 #include <mono/metadata/debug-helpers.h>
12 #include <mono/metadata/mempool-internals.h>
14 /* Disable for now to save space */
15 #undef MONO_ARCH_ENABLE_GLOBAL_RA
17 #ifdef MONO_ARCH_ENABLE_GLOBAL_RA
22 * This allocator is based on the paper
23 * "Linear Scan Register Allocation for the Java HotSpot Client Compiler"
24 * by Christian Wimmer.
26 * It differs from the current allocator in the following respects:
27 * - all variables (vregs) are allocated a register, there is no separate local/global
29 * - there are no variables allocated strictly to the stack. Even those variables
30 * allocated to the stack are loaded into a register before they are accessed.
36 * - Only works on amd64.
37 * - Tests in mono/mini and mono/tests work, "Hello, World!" works.
38 * - The quality of generated code is not bad, but needs more optimizations.
39 * - Focus was on correctness and easy debuggability so performance is bad, especially on
40 * large methods (like Main in transparentproxy.exe). Since each interval can be
41 * split at each use position, run time is linear in the number of variable accesses,
42 * not the number of variables.
43 * - Have to think about splitting the available registers between caller saved and callee
44 * saved, and take this into account during allocation (callee saved - good for
45 * variables which are accessed a lot, and/or are live across calls, caller saved -
46 * good for scratch registers used only in a bblock and not live across calls).
47 * - FIXME: Fix mono_arch_get_ireg_clobbered_by_call () to only return caller saved
54 typedef struct MonoRegallocInterval {
56 * 0..MONO_MAX_IREGS - iregs
57 * MONO_MAX_IREGS + 1...MONO_MAX_IREGS+MONO_MAX_FREGS - fregs
58 * MONO_MAX_IREGS+MONO_MAX_FREGS... cfg->next_vreg - vregs
59 * cfg->next_vreg... - split intervals
63 * Hard register assigned to this interval, -1 if no register is assigned or the
64 * interval is spilled.
69 * The actual interval data
71 MonoLiveInterval *interval;
74 * Split children of this interval. NULL if the interval is not split.
76 struct MonoRegallocInterval *child1, *child2;
79 * List of use positions, each position is identified by (bb->dfn << 16) + ins_pos
80 * The list is sorted by increasing position.
85 * The offset relative to the frame pointer where this interval is spilled.
90 * If we are a split child of an interval, this points to our parent
92 struct MonoRegallocInterval *parent;
95 * Whenever vreg is an fp vreg
100 * Whenever the variable is volatile
102 guint is_volatile : 1;
105 * The exact type of the variable
110 * The register where this interval should be allocated
113 } MonoRegallocInterval;
115 typedef struct MonoRegallocContext {
117 MonoRegallocInterval *varinfo;
120 * Maps ins pos -> GSList of intervals split at that pos.
122 GHashTable *split_positions;
124 * Used to avoid lookups in split_positions for every position.
126 GHashTable *split_position_set;
128 * Contains MonoInst's representing spill loads/stores
130 GHashTable *spill_ins;
131 } MonoRegallocContext;
137 #define NEW_UNALU(cfg,dest,op,dr,sr1) do { \
138 MONO_INST_NEW ((cfg), (dest), (op)); \
140 (dest)->sreg1 = sr1; \
143 #define NEW_STORE_MEMBASE(cfg,dest,op,base,offset,sr) do { \
144 MONO_INST_NEW ((cfg), (dest), (op)); \
145 (dest)->sreg1 = sr; \
146 (dest)->inst_destbasereg = base; \
147 (dest)->inst_offset = offset; \
150 #define NEW_LOAD_MEMBASE(cfg,dest,op,dr,base,offset) do { \
151 MONO_INST_NEW ((cfg), (dest), (op)); \
152 (dest)->dreg = (dr); \
153 (dest)->inst_basereg = (base); \
154 (dest)->inst_offset = (offset); \
155 (dest)->type = STACK_I4; \
158 #if SIZEOF_VOID_P == 8
159 #define BITS_PER_CHUNK 64
161 #define BITS_PER_CHUNK 32
164 #define MONO_FIRST_VREG (MONO_MAX_IREGS+MONO_MAX_FREGS)
167 * Each instruction is allocated 4 liveness phases:
168 * 0 - USE - the instruction reads its input registers in this phase
169 * 1 - CLOB - the instruction clobbers some registers in this phase
170 * 2 - DEF - the instruction writes its output register(s) in this phase
171 * 3 - SPILL - spill code
172 * In liveness ranges, the start position of the range is the DEF position of the
173 * instruction which defines the vreg.
176 #define INS_POS_USE 0
177 #define INS_POS_CLOB 1
178 #define INS_POS_DEF 2
179 #define INS_POS_SPILL 3
181 /* 16 is used instead of 4 so liveness ranges are easier to read */
182 #define INS_POS_INTERVAL 16
184 #define is_hard_reg(r,fp) ((fp) ? ((r) < MONO_MAX_FREGS) : ((r) < MONO_MAX_IREGS))
185 #define is_soft_reg(r,fp) (!is_hard_reg((r),(fp)))
187 #ifdef MONO_ARCH_INST_IS_FLOAT
188 #define dreg_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_DEST]))
189 #define sreg1_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC1]))
190 #define sreg2_is_fp(spec) (MONO_ARCH_INST_IS_FLOAT (spec [MONO_INST_SRC2]))
192 #define sreg1_is_fp(spec) (spec [MONO_INST_SRC1] == 'f')
193 #define sreg2_is_fp(spec) (spec [MONO_INST_SRC2] == 'f')
194 #define dreg_is_fp(spec) (spec [MONO_INST_DEST] == 'f')
197 static inline GSList*
198 g_slist_append_mempool (MonoMemPool *mp, GSList *list,
201 GSList *new_list, *last;
203 last = g_slist_last (list);
204 new_list = mono_mempool_alloc (mp, sizeof (GSList));
205 new_list->data = data;
206 new_list->next = NULL;
208 last->next = new_list;
216 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *insert_after)
218 if (insert_after == NULL) {
219 insert_after = bb->code;
221 ins->next = insert_after;
223 if (bb->last_ins == NULL)
227 ins->next = insert_after->next;
228 insert_after->next = ins;
230 if (bb->last_ins == insert_after)
236 create_move (MonoCompile *cfg, int dreg, int sreg)
240 MONO_INST_NEW (cfg, ins, OP_MOVE);
248 create_fp_move (MonoCompile *cfg, int dreg, int sreg)
252 MONO_INST_NEW (cfg, ins, OP_FMOVE);
260 emit_move (MonoCompile *cfg, int dreg, int sreg, MonoInst *insert_after)
262 MonoInst *ins = create_move (cfg, dreg, sreg);
264 insert_after_ins (cfg->cbb, ins, insert_after);
268 emit_fp_move (MonoCompile *cfg, int dreg, int sreg, MonoInst *insert_after)
270 MonoInst *ins = create_fp_move (cfg, dreg, sreg);
272 insert_after_ins (cfg->cbb, ins, insert_after);
276 emit_nop (MonoCompile *cfg, MonoInst *insert_after)
280 MONO_INST_NEW (cfg, ins, OP_NOP);
282 insert_after_ins (cfg->cbb, ins, insert_after);
286 * handle_reg_constraints:
288 * Rewrite the IR so it satisfies the register constraints of the architecture.
291 handle_reg_constraints (MonoCompile *cfg)
293 MonoMethodSignature *sig;
297 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
298 MonoInst *ins = bb->code;
299 MonoInst *prev = NULL;
301 if (cfg->verbose_level > 1) mono_print_bb (bb, "BEFORE HANDLE-REG-CONSTRAINTS ");
304 for (; ins; ins = ins->next) {
305 const char *spec = ins_get_spec (ins->opcode);
306 int dest_sreg1, dest_sreg2, dest_dreg;
308 dest_sreg1 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC1]);
309 dest_sreg2 = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_SRC2]);
310 dest_dreg = MONO_ARCH_INST_FIXED_REG (spec [MONO_INST_DEST]);
312 if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST]) ||
313 MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC1]) ||
314 MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_SRC2]))
316 g_assert_not_reached ();
318 if (spec [MONO_INST_CLOB] == 'c') {
319 MonoCallInst *call = (MonoCallInst*)ins;
323 * FIXME: mono_arch_emit_call () already adds moves for each argument,
324 * it might be better to rewrite those by changing the dreg to the hreg.
326 for (list = call->out_ireg_args; list; list = list->next) {
331 regpair = (guint32)(gssize)(list->data);
332 hreg = regpair >> 24;
333 reg = regpair & 0xffffff;
335 move = create_move (cfg, hreg, reg);
336 insert_after_ins (bb, move, prev);
340 for (list = call->out_freg_args; list; list = list->next) {
345 regpair = (guint32)(gssize)(list->data);
346 hreg = regpair >> 24;
347 reg = regpair & 0xffffff;
349 move = create_fp_move (cfg, hreg + MONO_MAX_IREGS, reg);
350 insert_after_ins (bb, move, prev);
355 if (spec [MONO_INST_CLOB] == '1') {
356 /* Copying sreg1 to dreg could clobber sreg2 so make a copy of sreg2 */
357 if (spec [MONO_INST_SRC2] && (ins->dreg == ins->sreg2)) {
358 int new_sreg2 = mono_alloc_preg (cfg);
360 g_assert (spec [MONO_INST_DEST] != 'f');
361 move = create_move (cfg, new_sreg2, ins->sreg2);
362 insert_after_ins (cfg->cbb, move, prev);
364 ins->sreg2 = new_sreg2;
366 if (spec [MONO_INST_DEST] == 'f')
367 emit_fp_move (cfg, ins->dreg, ins->sreg1, prev);
369 emit_move (cfg, ins->dreg, ins->sreg1, prev);
370 ins->sreg1 = ins->dreg;
373 if (dest_sreg1 != -1) {
374 emit_move (cfg, dest_sreg1, ins->sreg1, prev);
375 ins->sreg1 = dest_sreg1;
378 if (dest_sreg2 != -1) {
379 emit_move (cfg, dest_sreg2, ins->sreg2, prev);
380 ins->sreg2 = dest_sreg2;
383 if (dest_dreg != -1) {
384 emit_move (cfg, ins->dreg, dest_dreg, ins);
385 g_assert (spec [MONO_INST_CLOB] != '1');
386 ins->dreg = dest_dreg;
389 /* FIXME: Add fixed fp regs to the machine description */
390 if (ins->opcode == OP_FCALL || ins->opcode == OP_FCALL_REG || ins->opcode == OP_FCALL_MEMBASE) {
391 emit_fp_move (cfg, ins->dreg, MONO_MAX_IREGS + MONO_ARCH_FP_RETURN_REG, ins);
392 ins->dreg = MONO_MAX_IREGS + MONO_ARCH_FP_RETURN_REG;
396 * Add a dummy instruction after each definition of a volatile vreg, this is
397 * needed by the code in decompose_volatile_intervals ().
399 if (get_vreg_to_inst (cfg, ins->dreg) && (get_vreg_to_inst (cfg, ins->dreg)->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))) {
406 sig = mono_method_signature (cfg->method);
408 /* Add move of arguments */
410 * FIXME: Maybe this should be done by the allocator.
412 if (bb == cfg->bb_entry) {
416 if (cfg->vret_addr) {
417 g_assert (cfg->vret_addr->opcode == OP_REGVAR);
418 emit_move (cfg, cfg->vret_addr->dreg, cfg->vret_addr->inst_c0, prev);
422 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
425 if (sig->hasthis && (i == 0))
426 arg_type = &mono_defaults.object_class->byval_arg;
428 arg_type = sig->params [i - sig->hasthis];
430 // FIXME: vtypes in registers (pass + return)
432 if (ins->opcode == OP_REGVAR) {
433 if (!arg_type->byref && ((arg_type->type == MONO_TYPE_R4) || (arg_type->type == MONO_TYPE_R8)))
434 /* For R4, the prolog is assumed to do the conversion */
435 emit_fp_move (cfg, ins->dreg, ins->inst_c0 + MONO_MAX_IREGS, prev);
437 emit_move (cfg, ins->dreg, ins->inst_c0, prev);
444 /* Add move of return value */
445 for (i = 0; i < bb->out_count; ++i) {
446 if (cfg->ret && !cfg->vret_addr && !MONO_TYPE_ISSTRUCT (sig->ret) && bb->out_bb [i] == cfg->bb_exit) {
447 MonoInst *ins = NULL;
450 hreg = cfg->ret->inst_c0;
452 if ((sig->ret->type == MONO_TYPE_R4) || (sig->ret->type == MONO_TYPE_R8))
453 /* For R4, the JIT has already emitted code to do the conversion */
454 ins = create_fp_move (cfg, hreg + MONO_MAX_IREGS, cfg->ret->dreg);
456 ins = create_move (cfg, hreg, cfg->ret->dreg);
457 mono_add_ins_to_end (bb, ins);
461 if (cfg->verbose_level > 1) mono_print_bb (bb, "AFTER HANDLE-REG-CONSTRAINTS ");
468 * Set varinfo->fp for all float vregs
471 collect_fp_vregs (MonoCompile *cfg, MonoRegallocContext *ctx)
475 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
476 MonoInst *ins = bb->code;
478 for (; ins; ins = ins->next) {
479 const char *spec = ins_get_spec (ins->opcode);
481 if (G_UNLIKELY (sreg1_is_fp (spec) || sreg2_is_fp (spec) || dreg_is_fp (spec))) {
482 if (sreg1_is_fp (spec)) {
483 g_assert (ins->sreg1 >= MONO_MAX_IREGS);
484 ctx->varinfo [ins->sreg1].fp = TRUE;
485 if (ctx->varinfo [ins->sreg1].type->type != MONO_TYPE_R4)
486 ctx->varinfo [ins->sreg1].type = &mono_defaults.double_class->byval_arg;
488 if (sreg2_is_fp (spec)) {
489 g_assert (ins->sreg2 >= MONO_MAX_IREGS);
490 ctx->varinfo [ins->sreg2].fp = TRUE;
491 if (ctx->varinfo [ins->sreg2].type->type != MONO_TYPE_R4)
492 ctx->varinfo [ins->sreg2].type = &mono_defaults.double_class->byval_arg;
494 if (dreg_is_fp (spec)) {
495 g_assert (ins->dreg >= MONO_MAX_IREGS);
496 ctx->varinfo [ins->dreg].fp = TRUE;
497 if (ctx->varinfo [ins->dreg].type->type != MONO_TYPE_R4)
498 ctx->varinfo [ins->dreg].type = &mono_defaults.double_class->byval_arg;
506 #define LIVENESS_DEBUG(a) do { if (cfg->verbose_level > 2) { a; } } while (0)
508 #define LIVENESS_DEBUG(a)
511 // #define DEBUG_LIVENESS 1
513 G_GNUC_UNUSED static void
514 mono_bitset_print (MonoBitSet *set)
519 for (i = 0; i < mono_bitset_size (set); i++) {
521 if (mono_bitset_test (set, i))
529 update_gen_kill_set (MonoCompile *cfg, MonoRegallocContext *ctx, MonoBasicBlock *bb, MonoInst *ins)
531 const char *spec = INS_INFO (ins->opcode);
536 if (spec [MONO_INST_SRC1] != ' ') {
537 if (!mono_bitset_test_fast (bb->kill_set, sreg))
538 mono_bitset_set_fast (bb->gen_set, sreg);
543 if (spec [MONO_INST_SRC2] != ' ') {
544 if (!mono_bitset_test_fast (bb->kill_set, sreg))
545 mono_bitset_set_fast (bb->gen_set, sreg);
549 if (spec [MONO_INST_DEST] != ' ') {
550 if (MONO_IS_STORE_MEMBASE (ins)) {
551 if (!mono_bitset_test_fast (bb->kill_set, ins->dreg))
552 mono_bitset_set_fast (bb->gen_set, ins->dreg);
554 mono_bitset_set_fast (bb->kill_set, ins->dreg);
560 compute_gen_kill_sets (MonoCompile *cfg, MonoRegallocContext *ctx)
562 int i, max_vars = cfg->next_vreg;
566 bitsize = mono_bitset_alloc_size (max_vars, 0);
567 mem = mono_mempool_alloc0 (cfg->mempool, cfg->num_bblocks * bitsize * 3);
569 for (i = 0; i < cfg->num_bblocks; ++i) {
570 MonoBasicBlock *bb = cfg->bblocks [i];
572 bb->gen_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
574 bb->kill_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
576 /* Initialized later */
577 bb->live_in_set = NULL;
578 bb->live_out_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
582 for (i = 0; i < cfg->num_bblocks; ++i) {
583 MonoBasicBlock *bb = cfg->bblocks [i];
585 #ifdef DEBUG_LIVENESS
589 for (ins = bb->code; ins; ins = ins->next)
590 update_gen_kill_set (cfg, ctx, bb, ins);
592 #ifdef DEBUG_LIVENESS
593 printf ("BLOCK BB%d (", bb->block_num);
594 for (j = 0; j < bb->out_count; j++)
595 printf ("BB%d, ", bb->out_bb [j]->block_num);
598 printf ("GEN BB%d: ", bb->block_num); mono_bitset_print (bb->gen_set);
599 printf ("KILL BB%d: ", bb->block_num); mono_bitset_print (bb->kill_set);
603 if (cfg->ret && cfg->ret->opcode == OP_REGVAR) {
604 int hreg = cfg->ret->inst_c0;
606 /* gen_set might be empty if bb_exit is not reachable, like when using a tail call */
607 if (cfg->bb_exit->gen_set)
608 mono_bitset_set (cfg->bb_exit->gen_set, hreg);
613 compute_live_in_out_sets (MonoCompile *cfg, MonoRegallocContext *ctx)
615 MonoBitSet *old_live_out_set;
616 int i, j, max_vars = cfg->next_vreg;
618 gboolean *in_worklist;
619 MonoBasicBlock **worklist;
624 bitsize = mono_bitset_alloc_size (max_vars, 0);
625 mem = mono_mempool_alloc0 (cfg->mempool, cfg->num_bblocks * bitsize);
627 old_live_out_set = mono_bitset_new (max_vars, 0);
628 in_worklist = g_new0 (gboolean, cfg->num_bblocks + 1);
630 worklist = g_new (MonoBasicBlock *, cfg->num_bblocks + 1);
634 * This is a backward dataflow analysis problem, so we process blocks in
635 * decreasing dfn order, this speeds up the iteration.
637 for (i = 0; i < cfg->num_bblocks; i ++) {
638 MonoBasicBlock *bb = cfg->bblocks [i];
640 worklist [l_end ++] = bb;
641 in_worklist [bb->dfn] = TRUE;
647 MonoBasicBlock *bb = worklist [--l_end];
648 MonoBasicBlock *out_bb;
651 in_worklist [bb->dfn] = FALSE;
653 #ifdef DEBUG_LIVENESS
654 printf ("P: %d(%d): IN: ", bb->block_num, bb->dfn);
655 for (j = 0; j < bb->in_count; ++j)
656 printf ("BB%d ", bb->in_bb [j]->block_num);
658 for (j = 0; j < bb->out_count; ++j)
659 printf ("BB%d ", bb->out_bb [j]->block_num);
664 if (bb->out_count == 0)
669 if (!bb->live_in_set) {
670 /* First pass over this bblock */
675 mono_bitset_copyto_fast (bb->live_out_set, old_live_out_set);
678 for (j = 0; j < bb->out_count; j++) {
679 out_bb = bb->out_bb [j];
681 if (!out_bb->live_in_set) {
682 out_bb->live_in_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
685 mono_bitset_copyto_fast (out_bb->live_out_set, out_bb->live_in_set);
686 mono_bitset_sub_fast (out_bb->live_in_set, out_bb->kill_set);
687 mono_bitset_union_fast (out_bb->live_in_set, out_bb->gen_set);
690 mono_bitset_union_fast (bb->live_out_set, out_bb->live_in_set);
693 if (changed || !mono_bitset_equal (old_live_out_set, bb->live_out_set)) {
694 if (!bb->live_in_set) {
695 bb->live_in_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
698 mono_bitset_copyto_fast (bb->live_out_set, bb->live_in_set);
699 mono_bitset_sub_fast (bb->live_in_set, bb->kill_set);
700 mono_bitset_union_fast (bb->live_in_set, bb->gen_set);
702 for (j = 0; j < bb->in_count; j++) {
703 MonoBasicBlock *in_bb = bb->in_bb [j];
705 * Some basic blocks do not seem to be in the
706 * cfg->bblocks array...
708 if (in_bb->gen_set && !in_worklist [in_bb->dfn]) {
709 #ifdef DEBUG_LIVENESS
710 printf ("\tADD: %d\n", in_bb->block_num);
713 * Put the block at the top of the stack, so it
714 * will be processed right away.
716 worklist [l_end ++] = in_bb;
717 in_worklist [in_bb->dfn] = TRUE;
723 #ifdef DEBUG_LIVENESS
724 printf ("IT: %d %d.\n", cfg->num_bblocks, out_iter);
727 mono_bitset_free (old_live_out_set);
730 g_free (in_worklist);
732 /* Compute live_in_set for bblocks skipped earlier */
733 for (i = 0; i < cfg->num_bblocks; ++i) {
734 MonoBasicBlock *bb = cfg->bblocks [i];
736 if (!bb->live_in_set) {
737 bb->live_in_set = mono_bitset_mem_new (mem, max_vars, MONO_BITSET_DONT_FREE);
740 mono_bitset_copyto_fast (bb->live_out_set, bb->live_in_set);
741 mono_bitset_sub_fast (bb->live_in_set, bb->kill_set);
742 mono_bitset_union_fast (bb->live_in_set, bb->gen_set);
746 #ifdef DEBUG_LIVENESS
747 for (i = cfg->num_bblocks - 1; i >= 0; i--) {
748 MonoBasicBlock *bb = cfg->bblocks [i];
750 printf ("LIVE IN BB%d: ", bb->block_num);
751 mono_bitset_print (bb->live_in_set);
752 printf ("LIVE OUT BB%d: ", bb->block_num);
753 mono_bitset_print (bb->live_out_set);
759 update_liveness (MonoCompile *cfg, MonoRegallocContext *ctx, MonoInst *ins, int inst_num, gint32 *last_use)
761 const char *spec = INS_INFO (ins->opcode);
764 LIVENESS_DEBUG (printf ("\t%x: ", inst_num); mono_print_ins (ins));
767 if (spec [MONO_INST_DEST] != ' ') {
768 if (MONO_IS_STORE_MEMBASE (ins)) {
769 if (last_use [ins->dreg] == 0) {
770 LIVENESS_DEBUG (printf ("\tlast use of R%d set to %x\n", ins->dreg, inst_num + INS_POS_USE));
771 last_use [ins->dreg] = inst_num + INS_POS_USE;
774 if (last_use [ins->dreg] > 0) {
775 LIVENESS_DEBUG (printf ("\tadd range to R%d: [%x, %x]\n", ins->dreg, inst_num + INS_POS_DEF, last_use [ins->dreg]));
776 mono_linterval_add_range (ctx->cfg, ctx->varinfo [ins->dreg].interval, inst_num + INS_POS_DEF, last_use [ins->dreg]);
777 last_use [ins->dreg] = 0;
780 if (!vreg_is_volatile (cfg, ins->dreg) && ((ins->opcode == OP_ICONST) || (ins->opcode == OP_I8CONST) || (ins->opcode == OP_R8CONST) || (ins->opcode == OP_MOVE) || (ins->opcode == OP_FMOVE))) {
781 LIVENESS_DEBUG (printf ("\tdead def of R%d eliminated\n", ins->dreg));
783 spec = INS_INFO (ins->opcode);
785 LIVENESS_DEBUG (printf ("\tdead def of R%d, add range to R%d: [%x, %x]\n", ins->dreg, ins->dreg, inst_num + INS_POS_DEF, inst_num + INS_POS_DEF));
786 mono_linterval_add_range (ctx->cfg, ctx->varinfo [ins->dreg].interval, inst_num + INS_POS_DEF, inst_num + INS_POS_DEF);
790 if (ins->opcode != OP_NOP)
791 /* Since we process instructions backwards, the list will be properly sorted */
792 ctx->varinfo [ins->dreg].use_pos = g_slist_prepend_mempool (ctx->cfg->mempool, ctx->varinfo [ins->dreg].use_pos, GINT_TO_POINTER (inst_num));
794 /* Set preferred vregs */
795 if ((ins->opcode == OP_MOVE) || (ins->opcode == OP_FMOVE)) {
796 if (ins->sreg1 < MONO_FIRST_VREG) {
797 ctx->varinfo [ins->dreg].preferred_reg = ins->sreg1;
798 } else if (ins->dreg < MONO_FIRST_VREG) {
799 ctx->varinfo [ins->sreg1].preferred_reg = ins->dreg;
800 } else if (ctx->varinfo [ins->dreg].preferred_reg != -1) {
802 * Propagate preferred vregs. This works because instructions are
803 * processed in reverse order.
805 ctx->varinfo [ins->sreg1].preferred_reg = ctx->varinfo [ins->dreg].preferred_reg;
812 if (spec [MONO_INST_SRC1] != ' ') {
813 if (last_use [sreg] == 0) {
814 LIVENESS_DEBUG (printf ("\tlast use of R%d set to %x\n", sreg, inst_num + INS_POS_USE));
815 last_use [sreg] = inst_num + INS_POS_USE;
817 ctx->varinfo [sreg].use_pos = g_slist_prepend_mempool (ctx->cfg->mempool, ctx->varinfo [sreg].use_pos, GINT_TO_POINTER (inst_num));
822 if (spec [MONO_INST_SRC2] != ' ') {
823 if (last_use [sreg] == 0) {
824 LIVENESS_DEBUG (printf ("\tlast use of R%d set to %x\n", sreg, inst_num + INS_POS_USE));
825 last_use [sreg] = inst_num + INS_POS_USE;
827 ctx->varinfo [sreg].use_pos = g_slist_prepend_mempool (ctx->cfg->mempool, ctx->varinfo [sreg].use_pos, GINT_TO_POINTER (inst_num));
830 if (ins_get_spec (ins->opcode)[MONO_INST_CLOB] == 'c') {
831 MonoCallInst *call = (MonoCallInst*)ins;
834 for (list = call->out_ireg_args; list; list = list->next) {
837 regpair = (guint32)(gssize)(list->data);
838 sreg = regpair >> 24;
840 if (last_use [sreg] == 0) {
841 LIVENESS_DEBUG (printf ("\tlast use of R%d set to %x\n", sreg, inst_num + INS_POS_USE));
842 last_use [sreg] = inst_num + INS_POS_USE;
844 ctx->varinfo [sreg].use_pos = g_slist_prepend_mempool (ctx->cfg->mempool, ctx->varinfo [sreg].use_pos, GINT_TO_POINTER (inst_num));
847 for (list = call->out_freg_args; list; list = list->next) {
850 regpair = (guint32)(gssize)(list->data);
851 sreg = (regpair >> 24) + MONO_MAX_IREGS;
853 if (last_use [sreg] == 0) {
854 LIVENESS_DEBUG (printf ("\tlast use of R%d set to %x\n", sreg, inst_num + INS_POS_USE));
855 last_use [sreg] = inst_num + INS_POS_USE;
857 ctx->varinfo [sreg].use_pos = g_slist_prepend_mempool (ctx->cfg->mempool, ctx->varinfo [sreg].use_pos, GINT_TO_POINTER (inst_num));
862 if (ins_get_spec (ins->opcode)[MONO_INST_CLOB]) {
863 char clob = ins_get_spec (ins->opcode)[MONO_INST_CLOB];
867 /* A call clobbers some int/fp registers */
868 for (l = mono_arch_get_iregs_clobbered_by_call ((MonoCallInst*)ins); l; l = l->next)
869 mono_linterval_add_range (ctx->cfg, ctx->varinfo [GPOINTER_TO_INT (l->data)].interval, inst_num + INS_POS_CLOB, inst_num + INS_POS_CLOB);
870 for (l = mono_arch_get_fregs_clobbered_by_call ((MonoCallInst*)ins); l; l = l->next)
871 mono_linterval_add_range (ctx->cfg, ctx->varinfo [GPOINTER_TO_INT (l->data)].interval, inst_num + INS_POS_CLOB, inst_num + INS_POS_CLOB);
874 int clob_reg = MONO_ARCH_INST_FIXED_REG (clob);
877 mono_linterval_add_range (ctx->cfg, ctx->varinfo [clob_reg].interval, inst_num + INS_POS_CLOB, inst_num + INS_POS_CLOB);
885 * Compute liveness intervals for all vregs.
888 compute_intervals (MonoCompile *cfg, MonoRegallocContext *ctx)
890 int bnum, idx, i, j, nins, rem, max, max_vars, block_from, block_to, pos, reverse_len;
894 max_vars = cfg->next_vreg;
895 last_use = g_new0 (gint32, max_vars);
898 reverse = mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * reverse_len);
900 for (idx = 0; idx < max_vars; ++idx) {
901 ctx->varinfo [idx].interval = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoLiveInterval));
905 * Process bblocks in reverse order, so the addition of new live ranges
906 * to the intervals is faster.
908 for (bnum = cfg->num_bblocks - 1; bnum >= 0; --bnum) {
909 MonoBasicBlock *bb = cfg->bblocks [bnum];
912 block_from = (bb->dfn << 16); /* so pos > 0 */
913 if (bnum < cfg->num_bblocks - 1)
914 /* Beginning of the next bblock */
915 block_to = (cfg->bblocks [bnum + 1]->dfn << 16);
917 block_to = (bb->dfn << 16) + 0xffff;
919 LIVENESS_DEBUG (printf ("LIVENESS BLOCK BB%d:\n", bb->block_num));
921 memset (last_use, 0, max_vars * sizeof (gint32));
923 /* For variables in bb->live_out, set last_use to block_to */
925 rem = max_vars % BITS_PER_CHUNK;
926 max = ((max_vars + (BITS_PER_CHUNK -1)) / BITS_PER_CHUNK);
927 for (j = 0; j < max; ++j) {
931 bits_out = mono_bitset_get_fast (bb->live_out_set, j);
932 k = (j * BITS_PER_CHUNK);
935 LIVENESS_DEBUG (printf ("Var R%d live at exit, set last_use to %x\n", k, block_to));
936 last_use [k] = block_to;
943 for (nins = 0, pos = block_from, ins = bb->code; ins; ins = ins->next, ++nins, pos += INS_POS_INTERVAL) {
944 if (nins >= reverse_len) {
945 int new_reverse_len = reverse_len * 2;
946 MonoInst **new_reverse = mono_mempool_alloc (cfg->mempool, sizeof (MonoInst*) * new_reverse_len);
947 memcpy (new_reverse, reverse, sizeof (MonoInst*) * reverse_len);
948 reverse = new_reverse;
949 reverse_len = new_reverse_len;
952 reverse [nins] = ins;
955 g_assert (pos < block_to);
957 /* Process instructions backwards */
958 for (i = nins - 1; i >= 0; --i) {
959 MonoInst *ins = (MonoInst*)reverse [i];
961 update_liveness (cfg, ctx, ins, pos, last_use);
963 pos -= INS_POS_INTERVAL;
966 for (idx = 0; idx < max_vars; ++idx) {
967 if (last_use [idx] != 0) {
968 /* Live at exit, not written -> live on enter */
969 LIVENESS_DEBUG (printf ("Var R%d live at enter, add range to R%d: [%x, %x)\n", idx, idx, block_from, last_use [idx]));
970 mono_linterval_add_range (cfg, ctx->varinfo [idx].interval, block_from, last_use [idx]);
978 * Arguments need to have their live ranges extended to the beginning of
979 * the method to account for the arg reg/memory -> global register copies
980 * in the prolog (bug #74992).
982 for (i = 0; i < cfg->num_varinfo; i ++) {
983 MonoMethodVar *vi = MONO_VARINFO (cfg, i);
984 if ((cfg->varinfo [vi->idx]->opcode == OP_ARG) && (cfg->varinfo [vi->idx] != cfg->ret))
985 mono_linterval_add_range (cfg, ctx->varinfo [cfg->varinfo [i]->dreg].interval, 0, 1);
990 for (idx = 0; idx < max_vars; ++idx) {
991 printf ("LIVENESS R%d: ", idx);
992 mono_linterval_print (ctx->varinfo [idx].interval);
1004 * Perform liveness analysis.
1007 analyze_liveness (MonoCompile *cfg, MonoRegallocContext *ctx)
1009 LIVENESS_DEBUG (printf ("LIVENESS 3 %s\n", mono_method_full_name (cfg->method, TRUE)));
1011 /* FIXME: Make only one pass over the IR */
1013 compute_gen_kill_sets (cfg, ctx);
1015 compute_live_in_out_sets (cfg, ctx);
1017 compute_intervals (cfg, ctx);
1022 compare_by_interval_start_pos_func (gconstpointer a, gconstpointer b)
1024 MonoRegallocInterval *v1 = (MonoRegallocInterval*)a;
1025 MonoRegallocInterval *v2 = (MonoRegallocInterval*)b;
1029 else if (v1->interval->range && v2->interval->range)
1030 return v1->interval->range->from - v2->interval->range->from;
1031 else if (v1->interval->range)
1037 #define LSCAN_DEBUG(a) MINI_DEBUG(cfg->verbose_level, 2, a;)
1042 * Split the interval into two child intervals at POS.
1043 * [a, b] becomes [a, POS - 1], [POS, b].
1046 split_interval (MonoCompile *cfg, MonoRegallocContext *ctx, MonoRegallocInterval *interval, int pos)
1048 MonoRegallocInterval *child1, *child2;
1049 GSList *l, *split_list;
1051 child1 = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoRegallocInterval));
1052 child2 = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoRegallocInterval));
1053 child1->vreg = ctx->num_intervals ++;
1055 child1->offset = -1;
1056 child1->preferred_reg = -1;
1057 child1->is_volatile = interval->is_volatile;
1058 child1->fp = interval->fp;
1059 child1->type = interval->type;
1060 child2->vreg = ctx->num_intervals ++;
1062 child2->offset = -1;
1063 child2->preferred_reg = -1;
1064 child2->is_volatile = interval->is_volatile;
1065 child2->fp = interval->fp;
1066 child2->type = interval->type;
1068 interval->child1 = child1;
1069 interval->child2 = child2;
1070 child1->parent = interval;
1071 child2->parent = interval;
1073 mono_linterval_split (cfg, interval->interval, &child1->interval, &child2->interval, pos);
1075 /* Split use positions */
1076 for (l = interval->use_pos; l; l = l->next) {
1077 int use_pos = GPOINTER_TO_INT (l->data);
1080 child1->use_pos = g_slist_append_mempool (cfg->mempool, child1->use_pos, l->data);
1082 child2->use_pos = g_slist_append_mempool (cfg->mempool, child2->use_pos, l->data);
1085 /* Remember where spill code needs to be inserted */
1086 split_list = g_hash_table_lookup (ctx->split_positions, GUINT_TO_POINTER (pos));
1087 split_list = g_slist_prepend (split_list, interval);
1088 g_hash_table_insert (ctx->split_positions, GUINT_TO_POINTER (pos), split_list);
1089 g_hash_table_insert (ctx->split_position_set, GUINT_TO_POINTER (pos - (pos % INS_POS_INTERVAL)), GUINT_TO_POINTER (pos));
1091 if (cfg->verbose_level > 2) {
1092 printf ("\tSplit R%d into R%d and R%d at %x\n", interval->vreg, child1->vreg, child2->vreg, pos);
1093 printf ("\t R%d ", interval->vreg);
1094 mono_linterval_print (interval->interval);
1095 printf ("-> R%d ", child1->vreg);
1096 mono_linterval_print (child1->interval);
1097 printf ("||| R%d ", child2->vreg);
1098 mono_linterval_print (child2->interval);
1106 * Return L or one of its children which covers POS.
1108 static MonoRegallocInterval*
1109 child_at (MonoRegallocInterval *l, int pos)
1111 if (l->vreg < MONO_FIRST_VREG)
1115 g_assert (mono_linterval_covers (l->interval, pos));
1119 if (mono_linterval_covers (l->child1->interval, pos))
1120 return child_at (l->child1, pos);
1121 else if (mono_linterval_covers (l->child2->interval, pos))
1122 return child_at (l->child2, pos);
1124 g_assert_not_reached ();
1130 * decompose_volatile_intervals:
1132 * Decompose intervals belonging to volatile variables. Return the decomposed intervals
1133 * which should be allocated to registers.
1136 decompose_volatile_intervals (MonoCompile *cfg, MonoRegallocContext *ctx, GList *intervals)
1138 GList *new_intervals;
1142 * We model volatile intervals by splitting them at use positions and spilling the
1143 * sub intervals, ie. [a, b] is transformed to [a, a], [a + 1, b], [b, b] with the
1144 * middle interval spilled. This ensures that the variable will be spilled after each
1145 * def, and it will be loaded before each use.
1146 * FIXME: Stress test this by making most variables volatile
1148 new_intervals = g_list_copy (intervals);
1149 for (l = intervals; l; l = l->next) {
1150 MonoRegallocInterval *current = l->data;
1153 if (!current->is_volatile)
1157 * Instead of trying to split the arbitrary interval produced by the liveness
1158 * analysis phase, just use one big interval.
1160 current->interval = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoLiveInterval));
1161 mono_linterval_add_range (cfg, current->interval, 0, (32767 << 16));
1163 LSCAN_DEBUG (printf ("R%d is volatile ", current->vreg));
1164 LSCAN_DEBUG (mono_linterval_print (current->interval));
1165 LSCAN_DEBUG (printf ("\n"));
1167 new_intervals = g_list_remove (new_intervals, current);
1169 use_pos = current->use_pos;
1171 int pos = GPOINTER_TO_INT (use_pos->data);
1172 use_pos = use_pos->next;
1174 LSCAN_DEBUG (printf ("\tUse pos: %x\n", pos));
1176 /* Split the part of the interval before the definition into its own interval */
1177 if (pos > current->interval->range->from) {
1178 split_interval (cfg, ctx, current, pos);
1179 current = current->child2;
1182 /* Split the use into its own interval */
1183 split_interval (cfg, ctx, current, pos + INS_POS_INTERVAL);
1184 new_intervals = g_list_insert_sorted (new_intervals, current->child1, compare_by_interval_start_pos_func);
1185 current = current->child2;
1187 /* No need to (and hard to) split between use positions at the same place */
1188 while (use_pos && GPOINTER_TO_INT (use_pos->data) == pos)
1189 use_pos = use_pos->next;
1193 return new_intervals;
1199 * The actual linear scan register allocation algorithm.
1202 linear_scan (MonoCompile *cfg, MonoRegallocContext *ctx)
1204 GList *int_regs = mono_arch_get_global_int_regs (cfg);
1205 GList *fp_regs = mono_arch_get_global_fp_regs (cfg);
1207 GList *unhandled, *active, *inactive, *l, *next;
1208 gint32 free_pos [MONO_MAX_IREGS + MONO_MAX_FREGS];
1209 gboolean allocateable [MONO_MAX_IREGS + MONO_MAX_FREGS];
1211 MonoMethodSignature *sig;
1212 MonoMethodHeader *header;
1214 LSCAN_DEBUG (printf ("\nLinear Scan 2 for %s:\n", mono_method_full_name (cfg->method, TRUE)));
1216 header = mono_method_get_header (cfg->method);
1218 sig = mono_method_signature (cfg->method);
1220 /* Create list of allocatable variables */
1222 for (i = MONO_FIRST_VREG; i < cfg->next_vreg; ++i) {
1223 if (ctx->varinfo [i].interval->range)
1224 vars = g_list_prepend (vars, &ctx->varinfo [i]);
1227 for (i = 0; i < MONO_MAX_IREGS; ++i)
1228 allocateable [i] = g_list_find (int_regs, GINT_TO_POINTER (i)) != NULL;
1229 for (i = 0; i < MONO_MAX_FREGS; ++i)
1230 allocateable [MONO_MAX_IREGS + i] = g_list_find (fp_regs, GINT_TO_POINTER (i)) != NULL;
1231 g_list_free (int_regs);
1232 g_list_free (fp_regs);
1234 unhandled = g_list_sort (g_list_copy (vars), compare_by_interval_start_pos_func);
1238 /* The hard registers are assigned to themselves */
1239 for (i = 0; i < MONO_MAX_IREGS + MONO_MAX_FREGS; ++i) {
1240 ctx->varinfo [i].hreg = i;
1241 if (ctx->varinfo [i].interval->range)
1242 inactive = g_list_append (inactive, &ctx->varinfo [i]);
1245 unhandled = decompose_volatile_intervals (cfg, ctx, unhandled);
1248 * Handle arguments received on the stack by splitting their interval, and later
1249 * allocating the spilled part to the arg location.
1251 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1252 MonoInst *ins = cfg->args [i];
1253 MonoRegallocInterval *current = &ctx->varinfo [ins->dreg];
1256 if (sig->hasthis && (i == 0))
1257 arg_type = &mono_defaults.object_class->byval_arg;
1259 arg_type = sig->params [i - sig->hasthis];
1261 if (ins->opcode != OP_REGVAR && !MONO_TYPE_ISSTRUCT (arg_type) && !current->is_volatile && current->interval->range) {
1262 /* This ensures there is some part of the interval before the use pos */
1263 g_assert (current->interval->range->from == 0);
1265 /* Have to split at an use pos so a spill load can be inserted */
1266 if (current->use_pos) {
1267 guint32 pos = GPOINTER_TO_INT (current->use_pos->data);
1269 split_interval (cfg, ctx, current, pos);
1270 unhandled = g_list_remove (unhandled, current);
1271 unhandled = g_list_insert_sorted (unhandled, current->child2, compare_by_interval_start_pos_func);
1277 MonoRegallocInterval *current = unhandled->data;
1278 int pos, reg, max_free_pos;
1281 unhandled = g_list_delete_link (unhandled, unhandled);
1283 LSCAN_DEBUG (printf ("Processing R%d: ", current->vreg));
1284 LSCAN_DEBUG (mono_linterval_print (current->interval));
1285 LSCAN_DEBUG (printf ("\n"));
1287 if (!current->interval->range)
1290 /* Happens when splitting intervals */
1291 if (!current->use_pos)
1294 pos = current->interval->range->from;
1296 /* Check for intervals in active which expired or inactive */
1298 /* FIXME: Optimize this */
1301 MonoRegallocInterval *v = l->data;
1304 if (v->interval->last_range->to < pos) {
1305 active = g_list_delete_link (active, l);
1306 LSCAN_DEBUG (printf ("\tInterval R%d has expired\n", v->vreg));
1307 } else if (!mono_linterval_covers (v->interval, pos)) {
1308 inactive = g_list_append (inactive, v);
1309 active = g_list_delete_link (active, l);
1310 LSCAN_DEBUG (printf ("\tInterval R%d became inactive\n", v->vreg));
1315 /* Check for intervals in inactive which are expired or active */
1318 MonoRegallocInterval *v = l->data;
1321 if (v->interval->last_range->to < pos) {
1322 inactive = g_list_delete_link (inactive, l);
1323 LSCAN_DEBUG (printf ("\tInterval R%d has expired\n", v->vreg));
1324 } else if (mono_linterval_covers (v->interval, pos)) {
1325 active = g_list_append (active, v);
1326 inactive = g_list_delete_link (inactive, l);
1327 LSCAN_DEBUG (printf ("\tInterval R%d became active\n", v->vreg));
1332 /* Find a register for the current interval */
1333 if (G_UNLIKELY (current->fp)) {
1334 for (i = MONO_MAX_IREGS; i < MONO_MAX_IREGS + MONO_MAX_FREGS; ++i)
1335 if (allocateable [i])
1336 free_pos [i] = G_MAXINT32;
1340 for (i = 0; i < MONO_MAX_IREGS; ++i)
1341 if (allocateable [i])
1342 free_pos [i] = G_MAXINT32;
1347 for (l = active; l != NULL; l = l->next) {
1348 MonoRegallocInterval *v = l->data;
1351 free_pos [v->hreg] = 0;
1352 LSCAN_DEBUG (printf ("\threg %d is busy (R%d)\n", v->hreg, v->vreg));
1356 for (l = inactive; l != NULL; l = l->next) {
1357 MonoRegallocInterval *v = l->data;
1358 gint32 intersect_pos;
1360 if ((v->hreg >= 0) && (current->fp == v->fp)) {
1361 intersect_pos = mono_linterval_get_intersect_pos (current->interval, v->interval);
1362 if (intersect_pos != -1) {
1363 if (intersect_pos < free_pos [v->hreg])
1364 free_pos [v->hreg] = intersect_pos;
1365 LSCAN_DEBUG (printf ("\threg %d becomes free at %x\n", v->hreg, intersect_pos));
1375 * Arguments should be allocated to the registers they reside in at the start of
1378 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1379 MonoInst *ins = cfg->args [i];
1381 g_assert (ins->opcode == OP_REGVAR);
1382 if (ins->dreg == current->vreg)
1388 if (G_UNLIKELY (current->fp)) {
1389 for (i = MONO_MAX_IREGS; i < MONO_MAX_IREGS + MONO_MAX_FREGS; ++i)
1390 if (free_pos [i] > max_free_pos) {
1392 max_free_pos = free_pos [i];
1395 for (i = 0; i < MONO_MAX_IREGS; ++i)
1396 if (free_pos [i] > max_free_pos) {
1398 max_free_pos = free_pos [i];
1402 if (current->preferred_reg != -1) {
1403 LSCAN_DEBUG (printf ("\tPreferred register is hreg %d\n", current->preferred_reg));
1404 /* FIXME: Add more cases */
1405 if (free_pos [current->preferred_reg] >= free_pos [reg]) {
1406 reg = current->preferred_reg;
1410 * We have a choice to make: assigning to the preferred reg avoids
1411 * a move, while assigning to 'reg' will keep the variable in a
1412 * register for longer.
1414 if (free_pos [current->preferred_reg] >= current->interval->range->from)
1415 reg = current->preferred_reg;
1421 g_assert (reg != -1);
1423 if (!(free_pos [reg] > 0 && free_pos [reg] >= current->interval->range->from) &&
1424 GPOINTER_TO_INT (current->use_pos->data) <= current->interval->range->from) {
1426 * No register is available, and current is needed in a register right now.
1427 * So free up a register by spilling an interval in active.
1429 MonoRegallocInterval *to_spill;
1432 g_assert (!current->is_volatile);
1434 /* Spill the first */
1435 /* FIXME: Optimize the selection of the interval */
1438 for (l = active; l; l = l->next) {
1441 /* Fixed intervals cannot be spilled */
1442 if (to_spill->vreg >= MONO_FIRST_VREG)
1445 g_assert (to_spill);
1447 LSCAN_DEBUG (printf ("\tNo free register found, splitting and spilling R%d\n", to_spill->vreg));
1448 split_pos = GPOINTER_TO_INT (current->use_pos->data);
1450 * Avoid splitting to_spill before the start of current, since
1451 * its second child, which is added to unhandled would begin before
1454 if (split_pos < current->interval->range->from)
1455 split_pos = current->interval->range->from;
1456 split_interval (cfg, ctx, to_spill, split_pos);
1457 to_spill->child1->hreg = to_spill->hreg;
1458 active = g_list_remove (active, to_spill);
1459 unhandled = g_list_insert_sorted (unhandled, to_spill->child2, compare_by_interval_start_pos_func);
1460 reg = to_spill->hreg;
1462 /* Recompute free_pos [reg] */
1463 free_pos [reg] = G_MAXINT32;
1464 for (l = active; l != NULL; l = l->next) {
1465 MonoRegallocInterval *v = l->data;
1467 if (v->hreg == reg) {
1468 free_pos [v->hreg] = 0;
1469 LSCAN_DEBUG (printf ("\threg %d is busy (R%d)\n", v->hreg, v->vreg));
1473 for (l = inactive; l != NULL; l = l->next) {
1474 MonoRegallocInterval *v = l->data;
1475 gint32 intersect_pos;
1477 if ((v->hreg == reg) && (current->fp == v->fp)) {
1478 intersect_pos = mono_linterval_get_intersect_pos (current->interval, v->interval);
1479 if (intersect_pos != -1) {
1480 if (intersect_pos < free_pos [v->hreg])
1481 free_pos [v->hreg] = intersect_pos;
1482 LSCAN_DEBUG (printf ("\threg %d becomes free at %x\n", v->hreg, intersect_pos));
1488 if (free_pos [reg] > 0 && free_pos [reg] >= current->interval->last_range->to) {
1489 /* Register available for whole interval */
1490 current->hreg = reg;
1492 cfg->used_int_regs |= (1 << reg);
1493 LSCAN_DEBUG (printf ("\tAssigned hreg %d to R%d\n", reg, current->vreg));
1495 active = g_list_append (active, current);
1497 else if (free_pos [reg] > 0 && free_pos [reg] >= current->interval->range->from) {
1499 * The register is available for some part of the interval.
1500 * Split the interval, assign the register to the first part of the
1501 * interval, and save the second part for later processing.
1503 LSCAN_DEBUG (printf ("\tRegister %d is available until %x, splitting current.\n", reg, free_pos [reg]));
1504 split_interval (cfg, ctx, current, free_pos [reg]);
1506 current->child1->hreg = reg;
1508 cfg->used_int_regs |= (1 << reg);
1509 LSCAN_DEBUG (printf ("\tAssigned hreg %d to R%d\n", reg, current->child1->vreg));
1510 active = g_list_append (active, current->child1);
1512 unhandled = g_list_insert_sorted (unhandled, current->child2, compare_by_interval_start_pos_func);
1514 /* No register is available */
1515 if (GPOINTER_TO_INT (current->use_pos->data) > current->interval->range->from) {
1517 * The interval is not currently needed in a register. So split it, and
1518 * spill the first part to memory, and save the second part for later
1521 LSCAN_DEBUG (printf ("\tSplitting current at first use pos %x, spilling the first part.\n", GPOINTER_TO_INT (current->use_pos->data)));
1522 split_interval (cfg, ctx, current, GPOINTER_TO_INT (current->use_pos->data));
1523 unhandled = g_list_insert_sorted (unhandled, current->child2, compare_by_interval_start_pos_func);
1525 /* Handled previously */
1526 g_assert_not_reached ();
1532 * The fp registers are numbered from MONO_MAX_IREGS during allocation, but they are
1533 * numbered from 0 in machine code.
1535 for (i = 0; i < cfg->next_vreg; ++i) {
1536 if (ctx->varinfo [i].fp) {
1539 /* Need to process child intervals as well */
1540 /* This happens rarely so it is not perf critical */
1542 children = g_slist_prepend (children, &ctx->varinfo [i]);
1544 MonoRegallocInterval *interval = children->data;
1546 children = g_slist_delete_link (children, children);
1547 if (interval->hreg != -1)
1548 interval->hreg -= MONO_MAX_IREGS;
1549 if (interval->child1)
1550 children = g_slist_prepend (children, interval->child1);
1551 if (interval->child2)
1552 children = g_slist_prepend (children, interval->child2);
1559 collect_spilled_intervals (MonoRegallocInterval *interval, GSList *list)
1561 if ((interval->hreg == -1) && !interval->child1 && interval->interval->range)
1562 list = g_slist_prepend (list, interval);
1564 if (interval->is_volatile && !interval->interval->range)
1565 /* Variables which are only referenced by ldaddr */
1566 list = g_slist_prepend (list, interval);
1568 if (interval->child1) {
1569 list = collect_spilled_intervals (interval->child1, list);
1570 list = collect_spilled_intervals (interval->child2, list);
1577 alloc_spill_slot (MonoCompile *cfg, guint32 size, guint32 align)
1582 res = cfg->stack_offset;
1584 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
1585 cfg->stack_offset += align - 1;
1586 cfg->stack_offset &= ~(align - 1);
1587 res = cfg->stack_offset;
1588 cfg->stack_offset += size;
1590 cfg->stack_offset += align - 1;
1591 cfg->stack_offset &= ~(align - 1);
1592 cfg->stack_offset += size;
1593 res = - cfg->stack_offset;
1601 assign_spill_slots (MonoCompile *cfg, MonoRegallocContext *ctx)
1603 GSList *spilled_intervals = NULL;
1605 MonoMethodSignature *sig;
1608 /* Handle arguments passed on the stack */
1609 sig = mono_method_signature (cfg->method);
1610 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1611 MonoInst *ins = cfg->args [i];
1614 if (sig->hasthis && (i == 0))
1615 arg_type = &mono_defaults.object_class->byval_arg;
1617 arg_type = sig->params [i - sig->hasthis];
1619 if (MONO_TYPE_ISSTRUCT (arg_type) || (ins->opcode != OP_REGVAR)) {
1620 g_assert (ins->opcode == OP_REGOFFSET);
1621 // FIXME: Add a basereg field to varinfo
1623 g_assert (ins->inst_offset != -1);
1624 ctx->varinfo [ins->dreg].offset = ins->inst_offset;
1628 /* Handle a vtype return */
1629 if (!cfg->vret_addr && MONO_TYPE_ISSTRUCT (sig->ret)) {
1630 MonoInst *ins = cfg->ret;
1632 ctx->varinfo [ins->dreg].offset = ins->inst_offset;
1635 for (i = 0; i < cfg->next_vreg; ++i) {
1636 spilled_intervals = collect_spilled_intervals (&ctx->varinfo [i], spilled_intervals);
1639 LSCAN_DEBUG (printf ("\nSPILL OFFSETS:\n\n"));
1641 for (l = spilled_intervals; l; l = l->next) {
1642 MonoRegallocInterval *interval = l->data;
1643 MonoRegallocInterval *parent;
1646 * All spilled sub-intervals of a interval must share the stack slot.
1647 * This is accomplished by storing the stack offset in the original interval
1648 * and using that offset for all its children.
1651 for (parent = interval; parent->parent != NULL; parent = parent->parent)
1653 if (parent->offset != -1) {
1654 interval->offset = parent->offset;
1655 } else if (interval->offset != -1) {
1656 /* Already allocated (for example, valuetypes as arguments) */
1658 guint32 size, align;
1660 if (MONO_TYPE_ISSTRUCT (interval->type)) {
1661 // FIXME: pinvoke, gsctx
1663 size = mini_type_stack_size (NULL, interval->type, NULL);
1664 } else if (interval->fp) {
1665 size = sizeof (double);
1667 size = sizeof (gpointer);
1670 align = sizeof (gpointer);
1671 interval->offset = alloc_spill_slot (cfg, size, align);
1674 for (parent = interval; parent != NULL; parent = parent->parent) {
1675 if (parent->offset == -1)
1676 parent->offset = interval->offset;
1679 LSCAN_DEBUG (printf ("R%d %d", interval->vreg, interval->offset));
1680 LSCAN_DEBUG (mono_linterval_print (interval->interval));
1681 LSCAN_DEBUG (printf ("\n"));
1688 * Order the instructions in MOVES so earlier moves don't overwrite the sources of
1692 order_moves (MonoCompile *cfg, MonoRegallocContext *ctx, MonoInst **moves, int nmoves)
1698 * Sort the moves so earlier moves don't overwrite the sources of later
1701 /* FIXME: Do proper cycle detection instead of the current ugly hack */
1703 for (i = 0; i < nmoves; ++i) {
1709 for (j = i + 1; j < nmoves; ++j)
1710 if (moves [i]->dreg == moves [j]->sreg1) {
1718 moves [j] = moves [i];
1722 if (niter > nmoves * 2)
1723 /* Possible cycle */
1727 if (niter > nmoves * 2)
1732 if (niter > nmoves * 2) {
1737 * Save all registers to the stack and reload them again.
1738 * FIXME: Optimize this.
1741 /* Allocate spill slots */
1742 offsets = mono_mempool_alloc (cfg->mempool, nmoves * sizeof (int));
1743 for (i = 0; i < nmoves; ++i) {
1744 guint32 size = sizeof (gpointer);
1746 if (cfg->flags & MONO_CFG_HAS_SPILLUP) {
1747 cfg->stack_offset += size - 1;
1748 cfg->stack_offset &= ~(size - 1);
1749 offsets [i] = cfg->stack_offset;
1750 cfg->stack_offset += size;
1752 cfg->stack_offset += size - 1;
1753 cfg->stack_offset &= ~(size - 1);
1754 cfg->stack_offset += size;
1755 offsets [i] = - cfg->stack_offset;
1760 for (i = 0; i < nmoves; ++i) {
1761 if (moves [i]->opcode != OP_MOVE)
1763 MONO_INST_NEW (cfg, ins, OP_STORE_MEMBASE_REG);
1764 ins->sreg1 = moves [i]->sreg1;
1765 ins->inst_destbasereg = cfg->frame_reg;
1766 ins->inst_offset = offsets [i];
1768 l = g_slist_append_mempool (cfg->mempool, l, ins);
1769 g_hash_table_insert (ctx->spill_ins, ins, ins);
1773 for (i = 0; i < nmoves; ++i) {
1774 if (moves [i]->opcode != OP_MOVE)
1776 MONO_INST_NEW (cfg, ins, OP_LOAD_MEMBASE);
1777 ins->dreg = moves [i]->dreg;
1778 ins->inst_basereg = cfg->frame_reg;
1779 ins->inst_offset = offsets [i];
1781 l = g_slist_append_mempool (cfg->mempool, l, ins);
1782 g_hash_table_insert (ctx->spill_ins, ins, ins);
1787 for (i = 0; i < nmoves; ++i)
1788 l = g_slist_append_mempool (cfg->mempool, l, moves [i]);
1797 * Add spill loads and stores to the IR at the locations where intervals were split.
1800 add_spill_code (MonoCompile *cfg, MonoRegallocContext *ctx)
1803 MonoInst *ins, *prev, *store, *load, *move, *insert_after;
1804 GSList *spill_list, *l, *ins_to_add, *moves_to_add;
1805 MonoRegallocInterval *child1, *child2;
1806 int pos, pos_interval, pos_interval_limit;
1807 MonoBasicBlock *out_bb;
1808 int i, bb_count, from_pos, to_pos, iter;
1809 gboolean after_last_ins, add_at_head;
1811 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
1812 if (cfg->verbose_level > 1)
1813 printf ("\nREGALLOC-ADD SPILL CODE %d (DFN 0x%x):\n", bb->block_num, bb->dfn);
1815 /* First pass: Add spill loads/stores to the IR */
1816 pos = (bb->dfn << 16) + INS_POS_INTERVAL;
1818 after_last_ins = FALSE;
1819 for (ins = bb->code; !after_last_ins;) {
1821 after_last_ins = TRUE;
1822 } else if (g_hash_table_lookup (ctx->spill_ins, ins)) {
1823 /* Spill instruction added by an earlier bblock */
1824 /* No need to increase pos */
1826 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1827 printf (" <spill ins>\n");
1835 if (!g_hash_table_lookup (ctx->split_position_set, GUINT_TO_POINTER (pos))) {
1836 /* No split position at this instruction */
1837 pos_interval_limit = 0;
1838 pos += INS_POS_INTERVAL;
1840 pos_interval_limit = INS_POS_INTERVAL;
1843 for (pos_interval = 0; pos_interval < pos_interval_limit; ++pos_interval) {
1844 spill_list = g_hash_table_lookup (ctx->split_positions, GUINT_TO_POINTER (pos));
1845 /* Insert stores first, then loads so registers don't get overwritten */
1846 for (iter = 0; iter < 2; ++iter) {
1847 for (l = spill_list; l; l = l->next) {
1848 MonoRegallocInterval *interval = l->data;
1850 /* The childs might be split */
1851 if (interval->child1->child1)
1852 child1 = child_at (interval->child1, pos - pos_interval);
1854 child1 = interval->child1;
1855 if (pos < interval->child2->interval->range->from)
1856 /* Happens when volatile intervals are split */
1858 child2 = child_at (interval->child2, pos);
1860 if ((child1->hreg == -1) && (child2->hreg == -1))
1862 * Happens when an interval is split, then the first child
1867 // FIXME: Why is !is_volatile needed ?
1868 // It seems to fail when the same volatile var is a source and a
1869 // destination of the same instruction
1870 if ((iter == 0) && (child1->hreg != -1) && (child2->hreg != -1) && !interval->is_volatile) {
1874 * This is complex situation: the vreg is expected to be in
1875 * child1->hreg before the instruction, and in child2->hreg
1876 * after the instruction. We can't insert a move before,
1877 * because that could overwrite the input regs of the
1878 * instruction, and we can't insert a move after, since the
1879 * instruction could overwrite the source reg of the move.
1880 * Instead, we insert a store before the instruction, and a
1882 * FIXME: Optimize child1->hreg == child2->hreg
1884 offset = alloc_spill_slot (cfg, sizeof (gpointer), sizeof (gpointer));
1886 NEW_STORE_MEMBASE (cfg, store, mono_type_to_store_membase (cfg, interval->type), cfg->frame_reg, offset, child1->hreg);
1894 g_hash_table_insert (ctx->spill_ins, store, store);
1896 NEW_LOAD_MEMBASE (cfg, load, mono_type_to_load_membase (cfg, interval->type), child2->hreg, cfg->frame_reg, offset);
1898 insert_after_ins (bb, load, ins);
1899 g_hash_table_insert (ctx->spill_ins, load, load);
1901 LSCAN_DEBUG (printf (" Spill store/load added for R%d (R%d -> R%d) at %x\n", interval->vreg, child1->vreg, child2->vreg, pos));
1902 } else if ((iter == 0) && (child1->hreg != -1) && (child2->hreg == -1)) {
1903 g_assert (child2->offset != -1);
1905 NEW_STORE_MEMBASE (cfg, store, mono_type_to_store_membase (cfg, interval->type), cfg->frame_reg, child2->offset, child1->hreg);
1913 g_hash_table_insert (ctx->spill_ins, store, store);
1915 LSCAN_DEBUG (printf (" Spill store added for R%d (R%d -> R%d) at %x\n", interval->vreg, child1->vreg, child2->vreg, pos));
1916 } else if ((iter == 1) && (child1->hreg == -1) && (child2->hreg != -1)) {
1917 g_assert (child1->offset != -1);
1918 NEW_LOAD_MEMBASE (cfg, load, mono_type_to_load_membase (cfg, interval->type), child2->hreg, cfg->frame_reg, child1->offset);
1926 g_hash_table_insert (ctx->spill_ins, load, load);
1928 LSCAN_DEBUG (printf (" Spill load added for R%d (R%d -> R%d) at %x\n", interval->vreg, child1->vreg, child2->vreg, pos));
1936 if (G_UNLIKELY (cfg->verbose_level > 1))
1938 mono_print_ins (ins);
1946 /* Second pass: Resolve data flow */
1947 for (bb_count = 0; bb_count < bb->out_count; ++bb_count) {
1948 out_bb = bb->out_bb [bb_count];
1950 if (!out_bb->live_in_set)
1951 /* Exception handling block */
1954 from_pos = (bb->dfn << 16) + 0xffff;
1955 to_pos = (out_bb->dfn << 16);
1958 for (i = 0; i < cfg->next_vreg; ++i) {
1959 MonoRegallocInterval *interval = &ctx->varinfo [i];
1961 if (mono_bitset_test_fast (out_bb->live_in_set, i) && mono_linterval_covers (interval->interval, from_pos) && mono_linterval_covers (interval->interval, to_pos)) {
1962 child1 = child_at (interval, from_pos);
1963 child2 = child_at (interval, to_pos);
1964 if (child1 != child2) {
1965 if ((child1->hreg != -1) && (child2->hreg == -1)) {
1966 LSCAN_DEBUG (printf (" Add store for R%d (R%d -> R%d) at BB%d -> BB%d [%x - %x]\n", interval->vreg, child1->vreg, child2->vreg, bb->block_num, out_bb->block_num, from_pos, to_pos));
1967 NEW_STORE_MEMBASE (cfg, store, mono_type_to_store_membase (cfg, interval->type), cfg->frame_reg, child2->offset, child1->hreg);
1968 ins_to_add = g_slist_prepend_mempool (cfg->mempool, ins_to_add, store);
1969 g_hash_table_insert (ctx->spill_ins, store, store);
1970 } else if ((child1->hreg != -1) && (child2->hreg != -1)) {
1971 if (child1->hreg != child2->hreg) {
1972 LSCAN_DEBUG (printf (" Add move for R%d (R%d -> R%d) at BB%d -> BB%d [%x - %x]\n", interval->vreg, child1->vreg, child2->vreg, bb->block_num, out_bb->block_num, from_pos, to_pos));
1973 NEW_UNALU (cfg, move, interval->fp ? OP_FMOVE : OP_MOVE, child2->hreg, child1->hreg);
1974 ins_to_add = g_slist_prepend_mempool (cfg->mempool, ins_to_add, move);
1975 g_hash_table_insert (ctx->spill_ins, move, move);
1977 } else if ((child1->hreg == -1) && (child2->hreg != -1)) {
1978 LSCAN_DEBUG (printf (" Add load for R%d (R%d -> R%d) at BB%d -> BB%d [%x - %x]\n", interval->vreg, child1->vreg, child2->vreg, bb->block_num, out_bb->block_num, from_pos, to_pos));
1979 NEW_LOAD_MEMBASE (cfg, load, mono_type_to_load_membase (cfg, interval->type), child2->hreg, cfg->frame_reg, child1->offset);
1980 ins_to_add = g_slist_prepend_mempool (cfg->mempool, ins_to_add, load);
1981 g_hash_table_insert (ctx->spill_ins, load, load);
1983 g_assert (child1->offset == child2->offset);
1989 if (bb->out_count == 1) {
1991 } else if (out_bb->in_count == 1) {
1992 add_at_head = FALSE;
1994 // FIXME: Split critical edges
1999 insert_after = NULL;
2006 * Emit spill instructions in such a way that instructions don't
2007 * overwrite the source registers of instructions coming after them.
2009 /* Simply emit stores, then moves then loads */
2010 for (l = ins_to_add; l; l = l->next) {
2011 MonoInst *ins = l->data;
2013 if (MONO_IS_STORE_MEMBASE (ins)) {
2015 mono_add_ins_to_end (bb, ins);
2017 insert_after_ins (out_bb, ins, insert_after);
2023 /* Collect the moves */
2025 for (l = ins_to_add; l; l = l->next) {
2026 MonoInst *ins = l->data;
2028 if (MONO_IS_MOVE (ins))
2031 moves = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoInst*) * nmoves);
2033 for (l = ins_to_add; l; l = l->next) {
2034 MonoInst *ins = l->data;
2036 if (MONO_IS_MOVE (ins))
2037 moves [nmoves ++] = ins;
2040 moves_to_add = order_moves (cfg, ctx, moves, nmoves);
2042 for (l = moves_to_add; l; l = l->next) {
2043 MonoInst *ins = l->data;
2046 mono_add_ins_to_end (bb, ins);
2048 insert_after_ins (out_bb, ins, insert_after);
2053 for (l = ins_to_add; l; l = l->next) {
2054 MonoInst *ins = l->data;
2056 if (MONO_IS_LOAD_MEMBASE (ins)) {
2058 mono_add_ins_to_end (bb, ins);
2060 insert_after_ins (out_bb, ins, insert_after);
2073 * Replace references to vregs with their assigned physical registers or spill
2077 rewrite_code (MonoCompile *cfg, MonoRegallocContext *ctx)
2080 MonoInst *ins, *prev;
2083 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
2084 if (cfg->verbose_level > 1)
2085 printf ("\nREGALLOC-REWRITE BLOCK %d:\n", bb->block_num);
2087 pos = (bb->dfn << 16);
2089 for (ins = bb->code; ins; ins = ins->next) {
2090 const char *spec = INS_INFO (ins->opcode);
2091 pos += INS_POS_INTERVAL;
2093 if (G_UNLIKELY (cfg->verbose_level > 1))
2094 mono_print_ins (ins);
2096 if (g_hash_table_lookup (ctx->spill_ins, ins)) {
2098 * This instruction was added after liveness info was computed, and thus
2099 * screws up the pos calculation. The instruction already uses hregs.
2101 pos -= INS_POS_INTERVAL;
2107 if (ins->opcode == OP_NOP)
2110 if (ins->opcode == OP_LDADDR) {
2111 MonoRegallocInterval *l = child_at (&ctx->varinfo [ins->dreg], pos + INS_POS_DEF);
2112 MonoInst *var = ins->inst_p0;
2115 g_assert (ctx->varinfo [var->dreg].hreg == -1);
2116 g_assert (ctx->varinfo [var->dreg].offset != -1);
2118 if (ctx->varinfo [var->dreg].offset != 0) {
2120 * The ADD_IMM does not satisfy register constraints on x86/amd64.
2122 MONO_INST_NEW (cfg, move, OP_MOVE);
2123 move->dreg = l->hreg;
2124 move->sreg1 = cfg->frame_reg;
2132 ins->opcode = OP_ADD_IMM;
2133 ins->dreg = l->hreg;
2134 ins->sreg1 = l->hreg;
2135 ins->inst_imm = ctx->varinfo [var->dreg].offset;
2137 ins->opcode = OP_MOVE;
2138 ins->dreg = l->hreg;
2139 ins->sreg1 = cfg->frame_reg;
2141 spec = INS_INFO (OP_NOP);
2144 if (spec [MONO_INST_DEST] != ' ') {
2145 if (MONO_IS_STORE_MEMBASE (ins)) {
2146 MonoRegallocInterval *l = child_at (&ctx->varinfo [ins->dreg], pos + INS_POS_USE);
2147 g_assert (l->hreg != -1);
2148 ins->dreg = l->hreg;
2150 MonoRegallocInterval *l = child_at (&ctx->varinfo [ins->dreg], pos + INS_POS_DEF);
2151 g_assert (l->hreg != -1);
2152 ins->dreg = l->hreg;
2155 if (spec [MONO_INST_SRC1] != ' ') {
2156 MonoRegallocInterval *l = child_at (&ctx->varinfo [ins->sreg1], pos + INS_POS_USE);
2157 g_assert (l->hreg != -1);
2158 ins->sreg1 = l->hreg;
2160 if (spec [MONO_INST_SRC2] != ' ') {
2161 MonoRegallocInterval *l = child_at (&ctx->varinfo [ins->sreg2], pos + INS_POS_USE);
2162 g_assert (l->hreg != -1);
2163 ins->sreg2 = l->hreg;
2166 if (cfg->verbose_level > 1)
2167 mono_print_ins_index (1, ins);
2174 static MonoRegallocContext*
2175 regalloc_ctx_create (MonoCompile *cfg)
2177 MonoRegallocContext *ctx;
2180 ctx = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoRegallocContext));
2182 ctx->varinfo = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoRegallocInterval) * cfg->next_vreg);
2183 ctx->num_intervals = cfg->next_vreg;
2184 for (i = 0; i < cfg->next_vreg; ++i) {
2187 ctx->varinfo [i].vreg = i;
2188 ctx->varinfo [i].hreg = -1;
2189 ctx->varinfo [i].offset = -1;
2190 ctx->varinfo [i].preferred_reg = -1;
2192 if (i >= MONO_MAX_IREGS && i < MONO_MAX_IREGS + MONO_MAX_FREGS)
2193 ctx->varinfo [i].fp = TRUE;
2195 var = get_vreg_to_inst (cfg, i);
2196 if (var && (var != cfg->ret) && (var->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))) {
2197 ctx->varinfo [i].is_volatile = TRUE;
2200 ctx->varinfo [i].type = var->inst_vtype;
2202 ctx->varinfo [i].type = sizeof (gpointer) == 8 ? &mono_defaults.int64_class->byval_arg : &mono_defaults.int_class->byval_arg;
2205 ctx->split_positions = g_hash_table_new (NULL, NULL);
2206 ctx->split_position_set = g_hash_table_new (NULL, NULL);
2207 ctx->spill_ins = g_hash_table_new (NULL, NULL);
2213 mono_global_regalloc (MonoCompile *cfg)
2215 MonoRegallocContext *ctx;
2217 mono_arch_fill_argument_info (cfg);
2219 /* This could create vregs, so it has to come before ctx_create */
2220 handle_reg_constraints (cfg);
2222 ctx = regalloc_ctx_create (cfg);
2224 collect_fp_vregs (cfg, ctx);
2226 analyze_liveness (cfg, ctx);
2228 linear_scan (cfg, ctx);
2230 mono_arch_allocate_vars (cfg);
2232 assign_spill_slots (cfg, ctx);
2234 add_spill_code (cfg, ctx);
2236 rewrite_code (cfg, ctx);
2242 mono_global_regalloc (MonoCompile *cfg)