2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/abi-details.h>
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/metadata/gc-internal.h>
27 #include <mono/utils/mono-math.h>
28 #include <mono/utils/mono-counters.h>
29 #include <mono/utils/mono-mmap.h>
30 #include <mono/utils/mono-memory-model.h>
31 #include <mono/utils/mono-hwcap-x86.h>
41 static gboolean optimize_for_xen = TRUE;
43 #define optimize_for_xen 0
47 /* This mutex protects architecture specific caches */
48 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
49 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
50 static mono_mutex_t mini_arch_mutex;
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
57 /* Under windows, the default pinvoke calling convention is stdcall */
58 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
60 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_THISCALL))
63 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
69 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target);
71 #ifdef __native_client_codegen__
73 /* Default alignment for Native Client is 32-byte. */
74 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
76 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
77 /* Check that alignment doesn't cross an alignment boundary. */
79 mono_arch_nacl_pad (guint8 *code, int pad)
81 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
83 if (pad == 0) return code;
84 /* assertion: alignment cannot cross a block boundary */
85 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
86 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
87 while (pad >= kMaxPadding) {
88 x86_padding (code, kMaxPadding);
91 if (pad != 0) x86_padding (code, pad);
96 mono_arch_nacl_skip_nops (guint8 *code)
102 #endif /* __native_client_codegen__ */
105 * The code generated for sequence points reads from this location, which is
106 * made read-only when single stepping is enabled.
108 static gpointer ss_trigger_page;
110 /* Enabled breakpoints read from this trigger page */
111 static gpointer bp_trigger_page;
114 mono_arch_regname (int reg)
117 case X86_EAX: return "%eax";
118 case X86_EBX: return "%ebx";
119 case X86_ECX: return "%ecx";
120 case X86_EDX: return "%edx";
121 case X86_ESP: return "%esp";
122 case X86_EBP: return "%ebp";
123 case X86_EDI: return "%edi";
124 case X86_ESI: return "%esi";
130 mono_arch_fregname (int reg)
155 mono_arch_xregname (int reg)
180 mono_x86_patch (unsigned char* code, gpointer target)
182 x86_patch (code, (unsigned char*)target);
193 /* gsharedvt argument passed by addr */
205 /* Only if storage == ArgValuetypeInReg */
206 ArgStorage pair_storage [2];
215 gboolean need_stack_align;
216 guint32 stack_align_amount;
217 gboolean vtype_retaddr;
218 /* The index of the vret arg in the argument list */
221 /* Argument space popped by the callee */
222 int callee_stack_pop;
228 #define FLOAT_PARAM_REGS 0
230 static const guint32 thiscall_param_regs [] = { X86_ECX, X86_NREG };
232 static const guint32 *callconv_param_regs(MonoMethodSignature *sig)
237 switch (sig->call_convention) {
238 case MONO_CALL_THISCALL:
239 return thiscall_param_regs;
245 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
246 #define SMALL_STRUCTS_IN_REGS
247 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
251 add_general (guint32 *gr, const guint32 *param_regs, guint32 *stack_size, ArgInfo *ainfo)
253 ainfo->offset = *stack_size;
255 if (!param_regs || param_regs [*gr] == X86_NREG) {
256 ainfo->storage = ArgOnStack;
258 (*stack_size) += sizeof (gpointer);
261 ainfo->storage = ArgInIReg;
262 ainfo->reg = param_regs [*gr];
268 add_general_pair (guint32 *gr, const guint32 *param_regs , guint32 *stack_size, ArgInfo *ainfo)
270 ainfo->offset = *stack_size;
272 g_assert(!param_regs || param_regs[*gr] == X86_NREG);
274 ainfo->storage = ArgOnStack;
275 (*stack_size) += sizeof (gpointer) * 2;
280 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
282 ainfo->offset = *stack_size;
284 if (*gr >= FLOAT_PARAM_REGS) {
285 ainfo->storage = ArgOnStack;
286 (*stack_size) += is_double ? 8 : 4;
287 ainfo->nslots = is_double ? 2 : 1;
290 /* A double register */
292 ainfo->storage = ArgInDoubleSSEReg;
294 ainfo->storage = ArgInFloatSSEReg;
302 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
304 guint32 *gr, const guint32 *param_regs, guint32 *fr, guint32 *stack_size)
309 klass = mono_class_from_mono_type (type);
310 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
312 #ifdef SMALL_STRUCTS_IN_REGS
313 if (sig->pinvoke && is_return) {
314 MonoMarshalType *info;
317 * the exact rules are not very well documented, the code below seems to work with the
318 * code generated by gcc 3.3.3 -mno-cygwin.
320 info = mono_marshal_load_type_info (klass);
323 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
325 /* Special case structs with only a float member */
326 if (info->num_fields == 1) {
327 int ftype = mini_replace_type (info->fields [0].field->type)->type;
328 if ((info->native_size == 8) && (ftype == MONO_TYPE_R8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
333 if ((info->native_size == 4) && (ftype == MONO_TYPE_R4)) {
334 ainfo->storage = ArgValuetypeInReg;
335 ainfo->pair_storage [0] = ArgOnFloatFpStack;
339 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
340 ainfo->storage = ArgValuetypeInReg;
341 ainfo->pair_storage [0] = ArgInIReg;
342 ainfo->pair_regs [0] = return_regs [0];
343 if (info->native_size > 4) {
344 ainfo->pair_storage [1] = ArgInIReg;
345 ainfo->pair_regs [1] = return_regs [1];
352 if (param_regs && param_regs [*gr] != X86_NREG && !is_return) {
353 g_assert (size <= 4);
354 ainfo->storage = ArgValuetypeInReg;
355 ainfo->reg = param_regs [*gr];
360 ainfo->offset = *stack_size;
361 ainfo->storage = ArgOnStack;
362 *stack_size += ALIGN_TO (size, sizeof (gpointer));
363 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
369 * Obtain information about a call according to the calling convention.
370 * For x86 ELF, see the "System V Application Binary Interface Intel386
371 * Architecture Processor Supplment, Fourth Edition" document for more
373 * For x86 win32, see ???.
376 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
378 guint32 i, gr, fr, pstart;
379 const guint32 *param_regs;
381 int n = sig->hasthis + sig->param_count;
382 guint32 stack_size = 0;
383 gboolean is_pinvoke = sig->pinvoke;
389 param_regs = callconv_param_regs(sig);
393 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
394 switch (ret_type->type) {
395 case MONO_TYPE_BOOLEAN:
406 case MONO_TYPE_FNPTR:
407 case MONO_TYPE_CLASS:
408 case MONO_TYPE_OBJECT:
409 case MONO_TYPE_SZARRAY:
410 case MONO_TYPE_ARRAY:
411 case MONO_TYPE_STRING:
412 cinfo->ret.storage = ArgInIReg;
413 cinfo->ret.reg = X86_EAX;
417 cinfo->ret.storage = ArgInIReg;
418 cinfo->ret.reg = X86_EAX;
419 cinfo->ret.is_pair = TRUE;
422 cinfo->ret.storage = ArgOnFloatFpStack;
425 cinfo->ret.storage = ArgOnDoubleFpStack;
427 case MONO_TYPE_GENERICINST:
428 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
429 cinfo->ret.storage = ArgInIReg;
430 cinfo->ret.reg = X86_EAX;
433 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
434 cinfo->ret.storage = ArgOnStack;
435 cinfo->vtype_retaddr = TRUE;
439 case MONO_TYPE_VALUETYPE:
440 case MONO_TYPE_TYPEDBYREF: {
441 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
443 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, NULL, &tmp_fr, &tmp_stacksize);
444 if (cinfo->ret.storage == ArgOnStack) {
445 cinfo->vtype_retaddr = TRUE;
446 /* The caller passes the address where the value is stored */
452 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
453 cinfo->ret.storage = ArgOnStack;
454 cinfo->vtype_retaddr = TRUE;
457 cinfo->ret.storage = ArgNone;
460 g_error ("Can't handle as return value 0x%x", ret_type->type);
466 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
467 * the first argument, allowing 'this' to be always passed in the first arg reg.
468 * Also do this if the first argument is a reference type, since virtual calls
469 * are sometimes made using calli without sig->hasthis set, like in the delegate
472 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
474 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
476 add_general (&gr, param_regs, &stack_size, &cinfo->args [sig->hasthis + 0]);
479 cinfo->vret_arg_offset = stack_size;
480 add_general (&gr, NULL, &stack_size, &cinfo->ret);
481 cinfo->vret_arg_index = 1;
485 add_general (&gr, param_regs, &stack_size, cinfo->args + 0);
487 if (cinfo->vtype_retaddr)
488 add_general (&gr, NULL, &stack_size, &cinfo->ret);
491 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
492 fr = FLOAT_PARAM_REGS;
494 /* Emit the signature cookie just before the implicit arguments */
495 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
498 for (i = pstart; i < sig->param_count; ++i) {
499 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
502 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
503 /* We allways pass the sig cookie on the stack for simplicity */
505 * Prevent implicit arguments + the sig cookie from being passed
508 fr = FLOAT_PARAM_REGS;
510 /* Emit the signature cookie just before the implicit arguments */
511 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
514 if (sig->params [i]->byref) {
515 add_general (&gr, param_regs, &stack_size, ainfo);
518 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
519 switch (ptype->type) {
520 case MONO_TYPE_BOOLEAN:
523 add_general (&gr, param_regs, &stack_size, ainfo);
528 add_general (&gr, param_regs, &stack_size, ainfo);
532 add_general (&gr, param_regs, &stack_size, ainfo);
537 case MONO_TYPE_FNPTR:
538 case MONO_TYPE_CLASS:
539 case MONO_TYPE_OBJECT:
540 case MONO_TYPE_STRING:
541 case MONO_TYPE_SZARRAY:
542 case MONO_TYPE_ARRAY:
543 add_general (&gr, param_regs, &stack_size, ainfo);
545 case MONO_TYPE_GENERICINST:
546 if (!mono_type_generic_inst_is_valuetype (ptype)) {
547 add_general (&gr, param_regs, &stack_size, ainfo);
550 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
551 /* gsharedvt arguments are passed by ref */
552 add_general (&gr, param_regs, &stack_size, ainfo);
553 g_assert (ainfo->storage == ArgOnStack);
554 ainfo->storage = ArgGSharedVt;
558 case MONO_TYPE_VALUETYPE:
559 case MONO_TYPE_TYPEDBYREF:
560 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, param_regs, &fr, &stack_size);
564 add_general_pair (&gr, param_regs, &stack_size, ainfo);
567 add_float (&fr, &stack_size, ainfo, FALSE);
570 add_float (&fr, &stack_size, ainfo, TRUE);
574 /* gsharedvt arguments are passed by ref */
575 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
576 add_general (&gr, param_regs, &stack_size, ainfo);
577 g_assert (ainfo->storage == ArgOnStack);
578 ainfo->storage = ArgGSharedVt;
581 g_error ("unexpected type 0x%x", ptype->type);
582 g_assert_not_reached ();
586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
587 fr = FLOAT_PARAM_REGS;
589 /* Emit the signature cookie just before the implicit arguments */
590 add_general (&gr, param_regs, &stack_size, &cinfo->sig_cookie);
593 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
594 cinfo->need_stack_align = TRUE;
595 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
596 stack_size += cinfo->stack_align_amount;
599 if (cinfo->vtype_retaddr) {
600 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
601 cinfo->callee_stack_pop = 4;
604 cinfo->stack_usage = stack_size;
605 cinfo->reg_usage = gr;
606 cinfo->freg_usage = fr;
611 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
613 int n = sig->hasthis + sig->param_count;
617 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
619 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
621 return get_call_info_internal (gsctx, cinfo, sig);
625 * mono_arch_get_argument_info:
626 * @csig: a method signature
627 * @param_count: the number of parameters to consider
628 * @arg_info: an array to store the result infos
630 * Gathers information on parameters such as size, alignment and
631 * padding. arg_info should be large enought to hold param_count + 1 entries.
633 * Returns the size of the argument area on the stack.
634 * This should be signal safe, since it is called from
635 * mono_arch_find_jit_info ().
636 * FIXME: The metadata calls might not be signal safe.
639 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
641 int len, k, args_size = 0;
647 /* Avoid g_malloc as it is not signal safe */
648 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
649 cinfo = (CallInfo*)g_newa (guint8*, len);
650 memset (cinfo, 0, len);
652 cinfo = get_call_info_internal (gsctx, cinfo, csig);
654 arg_info [0].offset = offset;
656 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
657 args_size += sizeof (gpointer);
662 args_size += sizeof (gpointer);
666 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
667 /* Emitted after this */
668 args_size += sizeof (gpointer);
672 arg_info [0].size = args_size;
674 for (k = 0; k < param_count; k++) {
675 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
677 /* ignore alignment for now */
680 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
681 arg_info [k].pad = pad;
683 arg_info [k + 1].pad = 0;
684 arg_info [k + 1].size = size;
686 arg_info [k + 1].offset = offset;
689 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
690 /* Emitted after the first arg */
691 args_size += sizeof (gpointer);
696 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
697 align = MONO_ARCH_FRAME_ALIGNMENT;
700 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
701 arg_info [k].pad = pad;
707 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
709 MonoType *callee_ret;
713 if (cfg->compile_aot && !cfg->full_aot)
714 /* OP_TAILCALL doesn't work with AOT */
717 c1 = get_call_info (NULL, NULL, caller_sig);
718 c2 = get_call_info (NULL, NULL, callee_sig);
720 * Tail calls with more callee stack usage than the caller cannot be supported, since
721 * the extra stack space would be left on the stack after the tail call.
723 res = c1->stack_usage >= c2->stack_usage;
724 callee_ret = mini_replace_type (callee_sig->ret);
725 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
726 /* An address on the callee's stack is passed as the first argument */
736 * Initialize the cpu to execute managed code.
739 mono_arch_cpu_init (void)
741 /* spec compliance requires running with double precision */
745 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
746 fpcw &= ~X86_FPCW_PRECC_MASK;
747 fpcw |= X86_FPCW_PREC_DOUBLE;
748 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
749 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
751 _control87 (_PC_53, MCW_PC);
756 * Initialize architecture specific code.
759 mono_arch_init (void)
761 mono_mutex_init_recursive (&mini_arch_mutex);
763 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
764 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
765 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
767 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
768 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
769 #if defined(ENABLE_GSHAREDVT)
770 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
775 * Cleanup architecture specific code.
778 mono_arch_cleanup (void)
781 mono_vfree (ss_trigger_page, mono_pagesize ());
783 mono_vfree (bp_trigger_page, mono_pagesize ());
784 mono_mutex_destroy (&mini_arch_mutex);
788 * This function returns the optimizations supported on this cpu.
791 mono_arch_cpu_optimizations (guint32 *exclude_mask)
793 #if !defined(__native_client__)
798 if (mono_hwcap_x86_has_cmov) {
799 opts |= MONO_OPT_CMOV;
801 if (mono_hwcap_x86_has_fcmov)
802 opts |= MONO_OPT_FCMOV;
804 *exclude_mask |= MONO_OPT_FCMOV;
806 *exclude_mask |= MONO_OPT_CMOV;
809 if (mono_hwcap_x86_has_sse2)
810 opts |= MONO_OPT_SSE2;
812 *exclude_mask |= MONO_OPT_SSE2;
814 #ifdef MONO_ARCH_SIMD_INTRINSICS
815 /*SIMD intrinsics require at least SSE2.*/
816 if (!mono_hwcap_x86_has_sse2)
817 *exclude_mask |= MONO_OPT_SIMD;
822 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
827 * This function test for all SSE functions supported.
829 * Returns a bitmask corresponding to all supported versions.
833 mono_arch_cpu_enumerate_simd_versions (void)
835 guint32 sse_opts = 0;
837 if (mono_hwcap_x86_has_sse1)
838 sse_opts |= SIMD_VERSION_SSE1;
840 if (mono_hwcap_x86_has_sse2)
841 sse_opts |= SIMD_VERSION_SSE2;
843 if (mono_hwcap_x86_has_sse3)
844 sse_opts |= SIMD_VERSION_SSE3;
846 if (mono_hwcap_x86_has_ssse3)
847 sse_opts |= SIMD_VERSION_SSSE3;
849 if (mono_hwcap_x86_has_sse41)
850 sse_opts |= SIMD_VERSION_SSE41;
852 if (mono_hwcap_x86_has_sse42)
853 sse_opts |= SIMD_VERSION_SSE42;
855 if (mono_hwcap_x86_has_sse4a)
856 sse_opts |= SIMD_VERSION_SSE4a;
862 * Determine whenever the trap whose info is in SIGINFO is caused by
866 mono_arch_is_int_overflow (void *sigctx, void *info)
871 mono_sigctx_to_monoctx (sigctx, &ctx);
873 ip = (guint8*)ctx.eip;
875 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
879 switch (x86_modrm_rm (ip [1])) {
899 g_assert_not_reached ();
911 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
916 for (i = 0; i < cfg->num_varinfo; i++) {
917 MonoInst *ins = cfg->varinfo [i];
918 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
921 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
924 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
925 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
928 /* we dont allocate I1 to registers because there is no simply way to sign extend
929 * 8bit quantities in caller saved registers on x86 */
930 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
931 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
932 g_assert (i == vmv->idx);
933 vars = g_list_prepend (vars, vmv);
937 vars = mono_varlist_sort (cfg, vars, 0);
943 mono_arch_get_global_int_regs (MonoCompile *cfg)
947 /* we can use 3 registers for global allocation */
948 regs = g_list_prepend (regs, (gpointer)X86_EBX);
949 regs = g_list_prepend (regs, (gpointer)X86_ESI);
950 regs = g_list_prepend (regs, (gpointer)X86_EDI);
956 * mono_arch_regalloc_cost:
958 * Return the cost, in number of memory references, of the action of
959 * allocating the variable VMV into a register during global register
963 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
965 MonoInst *ins = cfg->varinfo [vmv->idx];
967 if (cfg->method->save_lmf)
968 /* The register is already saved */
969 return (ins->opcode == OP_ARG) ? 1 : 0;
971 /* push+pop+possible load if it is an argument */
972 return (ins->opcode == OP_ARG) ? 3 : 2;
976 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
978 static int inited = FALSE;
979 static int count = 0;
981 if (cfg->arch.need_stack_frame_inited) {
982 g_assert (cfg->arch.need_stack_frame == flag);
986 cfg->arch.need_stack_frame = flag;
987 cfg->arch.need_stack_frame_inited = TRUE;
993 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
998 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1002 needs_stack_frame (MonoCompile *cfg)
1004 MonoMethodSignature *sig;
1005 MonoMethodHeader *header;
1006 gboolean result = FALSE;
1008 #if defined(__APPLE__)
1009 /*OSX requires stack frame code to have the correct alignment. */
1013 if (cfg->arch.need_stack_frame_inited)
1014 return cfg->arch.need_stack_frame;
1016 header = cfg->header;
1017 sig = mono_method_signature (cfg->method);
1019 if (cfg->disable_omit_fp)
1021 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1023 else if (cfg->method->save_lmf)
1025 else if (cfg->stack_offset)
1027 else if (cfg->param_area)
1029 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1031 else if (header->num_clauses)
1033 else if (sig->param_count + sig->hasthis)
1035 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1037 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1038 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1041 set_needs_stack_frame (cfg, result);
1043 return cfg->arch.need_stack_frame;
1047 * Set var information according to the calling convention. X86 version.
1048 * The locals var stuff should most likely be split in another method.
1051 mono_arch_allocate_vars (MonoCompile *cfg)
1053 MonoMethodSignature *sig;
1054 MonoMethodHeader *header;
1056 guint32 locals_stack_size, locals_stack_align;
1061 header = cfg->header;
1062 sig = mono_method_signature (cfg->method);
1064 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1066 cfg->frame_reg = X86_EBP;
1069 if (cfg->has_atomic_add_i4 || cfg->has_atomic_exchange_i4) {
1070 /* The opcode implementations use callee-saved regs as scratch regs by pushing and pop-ing them, but that is not async safe */
1071 cfg->used_int_regs |= (1 << X86_EBX) | (1 << X86_EDI) | (1 << X86_ESI);
1074 /* Reserve space to save LMF and caller saved registers */
1076 if (cfg->method->save_lmf) {
1077 /* The LMF var is allocated normally */
1079 if (cfg->used_int_regs & (1 << X86_EBX)) {
1083 if (cfg->used_int_regs & (1 << X86_EDI)) {
1087 if (cfg->used_int_regs & (1 << X86_ESI)) {
1092 switch (cinfo->ret.storage) {
1093 case ArgValuetypeInReg:
1094 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1096 cfg->ret->opcode = OP_REGOFFSET;
1097 cfg->ret->inst_basereg = X86_EBP;
1098 cfg->ret->inst_offset = - offset;
1104 /* Allocate locals */
1105 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1106 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1107 char *mname = mono_method_full_name (cfg->method, TRUE);
1108 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1109 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1113 if (locals_stack_align) {
1114 int prev_offset = offset;
1116 offset += (locals_stack_align - 1);
1117 offset &= ~(locals_stack_align - 1);
1119 while (prev_offset < offset) {
1121 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1124 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1125 cfg->locals_max_stack_offset = - offset;
1127 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1128 * have locals larger than 8 bytes we need to make sure that
1129 * they have the appropriate offset.
1131 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1132 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1133 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1134 if (offsets [i] != -1) {
1135 MonoInst *inst = cfg->varinfo [i];
1136 inst->opcode = OP_REGOFFSET;
1137 inst->inst_basereg = X86_EBP;
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1142 offset += locals_stack_size;
1146 * Allocate arguments+return value
1149 switch (cinfo->ret.storage) {
1151 if (cfg->vret_addr) {
1153 * In the new IR, the cfg->vret_addr variable represents the
1154 * vtype return value.
1156 cfg->vret_addr->opcode = OP_REGOFFSET;
1157 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1158 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1159 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1160 printf ("vret_addr =");
1161 mono_print_ins (cfg->vret_addr);
1164 cfg->ret->opcode = OP_REGOFFSET;
1165 cfg->ret->inst_basereg = X86_EBP;
1166 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1169 case ArgValuetypeInReg:
1172 cfg->ret->opcode = OP_REGVAR;
1173 cfg->ret->inst_c0 = cinfo->ret.reg;
1174 cfg->ret->dreg = cinfo->ret.reg;
1177 case ArgOnFloatFpStack:
1178 case ArgOnDoubleFpStack:
1181 g_assert_not_reached ();
1184 if (sig->call_convention == MONO_CALL_VARARG) {
1185 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1186 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1189 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1190 ArgInfo *ainfo = &cinfo->args [i];
1191 inst = cfg->args [i];
1192 if (inst->opcode != OP_REGVAR) {
1193 inst->opcode = OP_REGOFFSET;
1194 inst->inst_basereg = X86_EBP;
1196 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1199 cfg->stack_offset = offset;
1203 mono_arch_create_vars (MonoCompile *cfg)
1206 MonoMethodSignature *sig;
1209 sig = mono_method_signature (cfg->method);
1211 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1212 sig_ret = mini_replace_type (sig->ret);
1214 if (cinfo->ret.storage == ArgValuetypeInReg)
1215 cfg->ret_var_is_local = TRUE;
1216 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig_ret) || mini_is_gsharedvt_variable_type (cfg, sig_ret))) {
1217 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1220 if (cfg->method->save_lmf) {
1221 cfg->create_lmf_var = TRUE;
1224 cfg->lmf_ir_mono_lmf = TRUE;
1228 cfg->arch_eh_jit_info = 1;
1232 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1233 * so we try to do it just once when we have multiple fp arguments in a row.
1234 * We don't use this mechanism generally because for int arguments the generated code
1235 * is slightly bigger and new generation cpus optimize away the dependency chains
1236 * created by push instructions on the esp value.
1237 * fp_arg_setup is the first argument in the execution sequence where the esp register
1240 static G_GNUC_UNUSED int
1241 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1246 for (; start_arg < sig->param_count; ++start_arg) {
1247 t = mini_replace_type (sig->params [start_arg]);
1248 if (!t->byref && t->type == MONO_TYPE_R8) {
1249 fp_space += sizeof (double);
1250 *fp_arg_setup = start_arg;
1259 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1261 MonoMethodSignature *tmp_sig;
1265 * mono_ArgIterator_Setup assumes the signature cookie is
1266 * passed first and all the arguments which were before it are
1267 * passed on the stack after the signature. So compensate by
1268 * passing a different signature.
1270 tmp_sig = mono_metadata_signature_dup (call->signature);
1271 tmp_sig->param_count -= call->signature->sentinelpos;
1272 tmp_sig->sentinelpos = 0;
1273 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1275 if (cfg->compile_aot) {
1276 sig_reg = mono_alloc_ireg (cfg);
1277 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1278 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->sig_cookie.offset, sig_reg);
1280 MONO_EMIT_NEW_STORE_MEMBASE_IMM (cfg, OP_STORE_MEMBASE_IMM, X86_ESP, cinfo->sig_cookie.offset, tmp_sig);
1286 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1291 LLVMCallInfo *linfo;
1292 MonoType *t, *sig_ret;
1294 n = sig->param_count + sig->hasthis;
1296 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1299 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1302 * LLVM always uses the native ABI while we use our own ABI, the
1303 * only difference is the handling of vtypes:
1304 * - we only pass/receive them in registers in some cases, and only
1305 * in 1 or 2 integer registers.
1307 if (cinfo->ret.storage == ArgValuetypeInReg) {
1309 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1310 cfg->disable_llvm = TRUE;
1314 cfg->exception_message = g_strdup ("vtype ret in call");
1315 cfg->disable_llvm = TRUE;
1317 linfo->ret.storage = LLVMArgVtypeInReg;
1318 for (j = 0; j < 2; ++j)
1319 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1323 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage == ArgInIReg) {
1324 /* Vtype returned using a hidden argument */
1325 linfo->ret.storage = LLVMArgVtypeRetAddr;
1326 linfo->vret_arg_index = cinfo->vret_arg_index;
1329 if (mini_type_is_vtype (cfg, sig_ret) && cinfo->ret.storage != ArgInIReg) {
1331 cfg->exception_message = g_strdup ("vtype ret in call");
1332 cfg->disable_llvm = TRUE;
1335 for (i = 0; i < n; ++i) {
1336 ainfo = cinfo->args + i;
1338 if (i >= sig->hasthis)
1339 t = sig->params [i - sig->hasthis];
1341 t = &mono_defaults.int_class->byval_arg;
1343 linfo->args [i].storage = LLVMArgNone;
1345 switch (ainfo->storage) {
1347 linfo->args [i].storage = LLVMArgInIReg;
1349 case ArgInDoubleSSEReg:
1350 case ArgInFloatSSEReg:
1351 linfo->args [i].storage = LLVMArgInFPReg;
1354 if (mini_type_is_vtype (cfg, t)) {
1355 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1356 /* LLVM seems to allocate argument space for empty structures too */
1357 linfo->args [i].storage = LLVMArgNone;
1359 linfo->args [i].storage = LLVMArgVtypeByVal;
1361 linfo->args [i].storage = LLVMArgInIReg;
1363 if (t->type == MONO_TYPE_R4)
1364 linfo->args [i].storage = LLVMArgInFPReg;
1365 else if (t->type == MONO_TYPE_R8)
1366 linfo->args [i].storage = LLVMArgInFPReg;
1370 case ArgValuetypeInReg:
1372 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1373 cfg->disable_llvm = TRUE;
1377 cfg->exception_message = g_strdup ("vtype arg");
1378 cfg->disable_llvm = TRUE;
1380 linfo->args [i].storage = LLVMArgVtypeInReg;
1381 for (j = 0; j < 2; ++j)
1382 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1386 linfo->args [i].storage = LLVMArgGSharedVt;
1389 cfg->exception_message = g_strdup ("ainfo->storage");
1390 cfg->disable_llvm = TRUE;
1400 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1402 if (cfg->compute_gc_maps) {
1405 /* Needs checking if the feature will be enabled again */
1406 g_assert_not_reached ();
1408 /* On x86, the offsets are from the sp value before the start of the call sequence */
1410 t = &mono_defaults.int_class->byval_arg;
1411 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1416 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1420 MonoMethodSignature *sig;
1423 int sentinelpos = 0, sp_offset = 0;
1425 sig = call->signature;
1426 n = sig->param_count + sig->hasthis;
1427 sig_ret = mini_replace_type (sig->ret);
1429 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1430 call->call_info = cinfo;
1432 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1433 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1435 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
1436 if (cinfo->ret.storage == ArgValuetypeInReg) {
1438 * Tell the JIT to use a more efficient calling convention: call using
1439 * OP_CALL, compute the result location after the call, and save the
1442 call->vret_in_reg = TRUE;
1443 #if defined(__APPLE__)
1444 if (cinfo->ret.pair_storage [0] == ArgOnDoubleFpStack || cinfo->ret.pair_storage [0] == ArgOnFloatFpStack)
1445 call->vret_in_reg_fp = TRUE;
1448 NULLIFY_INS (call->vret_var);
1452 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1454 /* Handle the case where there are no implicit arguments */
1455 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1456 emit_sig_cookie (cfg, call, cinfo);
1457 sp_offset = cinfo->sig_cookie.offset;
1458 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1461 /* Arguments are pushed in the reverse order */
1462 for (i = n - 1; i >= 0; i --) {
1463 ArgInfo *ainfo = cinfo->args + i;
1464 MonoType *orig_type, *t;
1467 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1470 /* Push the vret arg before the first argument */
1471 MONO_INST_NEW (cfg, vtarg, OP_STORE_MEMBASE_REG);
1472 vtarg->type = STACK_MP;
1473 vtarg->inst_destbasereg = X86_ESP;
1474 vtarg->sreg1 = call->vret_var->dreg;
1475 vtarg->inst_offset = cinfo->ret.offset;
1476 MONO_ADD_INS (cfg->cbb, vtarg);
1477 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1480 if (i >= sig->hasthis)
1481 t = sig->params [i - sig->hasthis];
1483 t = &mono_defaults.int_class->byval_arg;
1485 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1487 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1489 in = call->args [i];
1490 arg->cil_code = in->cil_code;
1491 arg->sreg1 = in->dreg;
1492 arg->type = in->type;
1494 g_assert (in->dreg != -1);
1496 if (ainfo->storage == ArgGSharedVt) {
1497 arg->opcode = OP_OUTARG_VT;
1498 arg->sreg1 = in->dreg;
1499 arg->klass = in->klass;
1500 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1501 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1503 MONO_ADD_INS (cfg->cbb, arg);
1504 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1508 g_assert (in->klass);
1510 if (t->type == MONO_TYPE_TYPEDBYREF) {
1511 size = sizeof (MonoTypedRef);
1512 align = sizeof (gpointer);
1515 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1519 arg->opcode = OP_OUTARG_VT;
1520 arg->sreg1 = in->dreg;
1521 arg->klass = in->klass;
1522 arg->backend.size = size;
1523 arg->inst_p0 = call;
1524 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1525 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1527 MONO_ADD_INS (cfg->cbb, arg);
1528 if (ainfo->storage != ArgValuetypeInReg) {
1529 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1533 switch (ainfo->storage) {
1536 if (t->type == MONO_TYPE_R4) {
1537 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1539 } else if (t->type == MONO_TYPE_R8) {
1540 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1542 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1543 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset + 4, in->dreg + 2);
1544 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg + 1);
1547 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1551 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, in->dreg);
1556 arg->opcode = OP_MOVE;
1557 arg->dreg = ainfo->reg;
1558 MONO_ADD_INS (cfg->cbb, arg);
1562 g_assert_not_reached ();
1565 if (cfg->compute_gc_maps) {
1567 /* FIXME: The == STACK_OBJ check might be fragile ? */
1568 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1570 if (call->need_unbox_trampoline)
1571 /* The unbox trampoline transforms this into a managed pointer */
1572 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.int_class->this_arg);
1574 emit_gc_param_slot_def (cfg, ainfo->offset, &mono_defaults.object_class->byval_arg);
1576 emit_gc_param_slot_def (cfg, ainfo->offset, orig_type);
1580 for (j = 0; j < argsize; j += 4)
1581 emit_gc_param_slot_def (cfg, ainfo->offset + j, NULL);
1586 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1587 /* Emit the signature cookie just before the implicit arguments */
1588 emit_sig_cookie (cfg, call, cinfo);
1589 emit_gc_param_slot_def (cfg, cinfo->sig_cookie.offset, NULL);
1593 if (sig_ret && (MONO_TYPE_ISSTRUCT (sig_ret) || cinfo->vtype_retaddr)) {
1596 if (cinfo->ret.storage == ArgValuetypeInReg) {
1599 else if (cinfo->ret.storage == ArgInIReg) {
1601 /* The return address is passed in a register */
1602 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1603 vtarg->sreg1 = call->inst.dreg;
1604 vtarg->dreg = mono_alloc_ireg (cfg);
1605 MONO_ADD_INS (cfg->cbb, vtarg);
1607 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1608 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1609 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, cinfo->ret.offset, call->vret_var->dreg);
1610 emit_gc_param_slot_def (cfg, cinfo->ret.offset, NULL);
1614 call->stack_usage = cinfo->stack_usage;
1615 call->stack_align_amount = cinfo->stack_align_amount;
1619 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1621 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
1622 ArgInfo *ainfo = ins->inst_p1;
1623 int size = ins->backend.size;
1625 if (ainfo->storage == ArgValuetypeInReg) {
1626 int dreg = mono_alloc_ireg (cfg);
1629 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU1_MEMBASE, dreg, src->dreg, 0);
1632 MONO_EMIT_NEW_LOAD_MEMBASE_OP (cfg, OP_LOADU2_MEMBASE, dreg, src->dreg, 0);
1635 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1639 g_assert_not_reached ();
1641 mono_call_inst_add_outarg_reg (cfg, call, dreg, ainfo->reg, FALSE);
1644 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1646 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, src->dreg);
1647 } else if (size <= 4) {
1648 int dreg = mono_alloc_ireg (cfg);
1649 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
1650 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, X86_ESP, ainfo->offset, dreg);
1651 } else if (size <= 20) {
1652 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1654 // FIXME: Code growth
1655 mini_emit_memcpy (cfg, X86_ESP, ainfo->offset, src->dreg, 0, size, 4);
1661 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1663 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1666 if (ret->type == MONO_TYPE_R4) {
1667 if (COMPILE_LLVM (cfg))
1668 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1671 } else if (ret->type == MONO_TYPE_R8) {
1672 if (COMPILE_LLVM (cfg))
1673 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1676 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1677 if (COMPILE_LLVM (cfg))
1678 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1680 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1681 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1687 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1691 * Allow tracing to work with this interface (with an optional argument)
1694 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1698 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1699 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1701 /* if some args are passed in registers, we need to save them here */
1702 x86_push_reg (code, X86_EBP);
1704 if (cfg->compile_aot) {
1705 x86_push_imm (code, cfg->method);
1706 x86_mov_reg_imm (code, X86_EAX, func);
1707 x86_call_reg (code, X86_EAX);
1709 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1710 x86_push_imm (code, cfg->method);
1711 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1712 x86_call_code (code, 0);
1714 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1728 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1731 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1732 MonoMethod *method = cfg->method;
1733 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1735 switch (ret_type->type) {
1736 case MONO_TYPE_VOID:
1737 /* special case string .ctor icall */
1738 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1739 save_mode = SAVE_EAX;
1740 stack_usage = enable_arguments ? 8 : 4;
1742 save_mode = SAVE_NONE;
1746 save_mode = SAVE_EAX_EDX;
1747 stack_usage = enable_arguments ? 16 : 8;
1751 save_mode = SAVE_FP;
1752 stack_usage = enable_arguments ? 16 : 8;
1754 case MONO_TYPE_GENERICINST:
1755 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1756 save_mode = SAVE_EAX;
1757 stack_usage = enable_arguments ? 8 : 4;
1761 case MONO_TYPE_VALUETYPE:
1762 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1763 save_mode = SAVE_STRUCT;
1764 stack_usage = enable_arguments ? 4 : 0;
1767 save_mode = SAVE_EAX;
1768 stack_usage = enable_arguments ? 8 : 4;
1772 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1774 switch (save_mode) {
1776 x86_push_reg (code, X86_EDX);
1777 x86_push_reg (code, X86_EAX);
1778 if (enable_arguments) {
1779 x86_push_reg (code, X86_EDX);
1780 x86_push_reg (code, X86_EAX);
1785 x86_push_reg (code, X86_EAX);
1786 if (enable_arguments) {
1787 x86_push_reg (code, X86_EAX);
1792 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1793 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1794 if (enable_arguments) {
1795 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1796 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1801 if (enable_arguments) {
1802 x86_push_membase (code, X86_EBP, 8);
1811 if (cfg->compile_aot) {
1812 x86_push_imm (code, method);
1813 x86_mov_reg_imm (code, X86_EAX, func);
1814 x86_call_reg (code, X86_EAX);
1816 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1817 x86_push_imm (code, method);
1818 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1819 x86_call_code (code, 0);
1822 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1824 switch (save_mode) {
1826 x86_pop_reg (code, X86_EAX);
1827 x86_pop_reg (code, X86_EDX);
1830 x86_pop_reg (code, X86_EAX);
1833 x86_fld_membase (code, X86_ESP, 0, TRUE);
1834 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1841 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1846 #define EMIT_COND_BRANCH(ins,cond,sign) \
1847 if (ins->inst_true_bb->native_offset) { \
1848 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1850 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1851 if ((cfg->opt & MONO_OPT_BRANCH) && \
1852 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1853 x86_branch8 (code, cond, 0, sign); \
1855 x86_branch32 (code, cond, 0, sign); \
1859 * Emit an exception if condition is fail and
1860 * if possible do a directly branch to target
1862 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1864 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1865 if (tins == NULL) { \
1866 mono_add_patch_info (cfg, code - cfg->native_code, \
1867 MONO_PATCH_INFO_EXC, exc_name); \
1868 x86_branch32 (code, cond, 0, signed); \
1870 EMIT_COND_BRANCH (tins, cond, signed); \
1874 #define EMIT_FPCOMPARE(code) do { \
1875 x86_fcompp (code); \
1876 x86_fnstsw (code); \
1881 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1883 gboolean needs_paddings = TRUE;
1885 MonoJumpInfo *jinfo = NULL;
1887 if (cfg->abs_patches) {
1888 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1889 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1890 needs_paddings = FALSE;
1893 if (cfg->compile_aot)
1894 needs_paddings = FALSE;
1895 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1896 This is required for code patching to be safe on SMP machines.
1898 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1899 #ifndef __native_client_codegen__
1900 if (needs_paddings && pad_size)
1901 x86_padding (code, 4 - pad_size);
1904 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1905 x86_call_code (code, 0);
1910 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1913 * mono_peephole_pass_1:
1915 * Perform peephole opts which should/can be performed before local regalloc
1918 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1922 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1923 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
1925 switch (ins->opcode) {
1928 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1930 * X86_LEA is like ADD, but doesn't have the
1931 * sreg1==dreg restriction.
1933 ins->opcode = OP_X86_LEA_MEMBASE;
1934 ins->inst_basereg = ins->sreg1;
1935 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1936 ins->opcode = OP_X86_INC_REG;
1940 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
1941 ins->opcode = OP_X86_LEA_MEMBASE;
1942 ins->inst_basereg = ins->sreg1;
1943 ins->inst_imm = -ins->inst_imm;
1944 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1945 ins->opcode = OP_X86_DEC_REG;
1947 case OP_COMPARE_IMM:
1948 case OP_ICOMPARE_IMM:
1949 /* OP_COMPARE_IMM (reg, 0)
1951 * OP_X86_TEST_NULL (reg)
1954 ins->opcode = OP_X86_TEST_NULL;
1956 case OP_X86_COMPARE_MEMBASE_IMM:
1958 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1959 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1961 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1962 * OP_COMPARE_IMM reg, imm
1964 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1966 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1967 ins->inst_basereg == last_ins->inst_destbasereg &&
1968 ins->inst_offset == last_ins->inst_offset) {
1969 ins->opcode = OP_COMPARE_IMM;
1970 ins->sreg1 = last_ins->sreg1;
1972 /* check if we can remove cmp reg,0 with test null */
1974 ins->opcode = OP_X86_TEST_NULL;
1978 case OP_X86_PUSH_MEMBASE:
1979 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
1980 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1981 ins->inst_basereg == last_ins->inst_destbasereg &&
1982 ins->inst_offset == last_ins->inst_offset) {
1983 ins->opcode = OP_X86_PUSH;
1984 ins->sreg1 = last_ins->sreg1;
1989 mono_peephole_ins (bb, ins);
1994 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1998 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1999 switch (ins->opcode) {
2001 /* reg = 0 -> XOR (reg, reg) */
2002 /* XOR sets cflags on x86, so we cant do it always */
2003 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2006 ins->opcode = OP_IXOR;
2007 ins->sreg1 = ins->dreg;
2008 ins->sreg2 = ins->dreg;
2011 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2012 * since it takes 3 bytes instead of 7.
2014 for (ins2 = mono_inst_next (ins, FILTER_IL_SEQ_POINT); ins2; ins2 = ins2->next) {
2015 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2016 ins2->opcode = OP_STORE_MEMBASE_REG;
2017 ins2->sreg1 = ins->dreg;
2019 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2020 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2021 ins2->sreg1 = ins->dreg;
2023 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2024 /* Continue iteration */
2033 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2034 ins->opcode = OP_X86_INC_REG;
2038 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2039 ins->opcode = OP_X86_DEC_REG;
2043 mono_peephole_ins (bb, ins);
2048 * mono_arch_lowering_pass:
2050 * Converts complex opcodes into simpler ones so that each IR instruction
2051 * corresponds to one machine instruction.
2054 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2056 MonoInst *ins, *next;
2059 * FIXME: Need to add more instructions, but the current machine
2060 * description can't model some parts of the composite instructions like
2063 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2064 switch (ins->opcode) {
2067 case OP_IDIV_UN_IMM:
2068 case OP_IREM_UN_IMM:
2070 * Keep the cases where we could generated optimized code, otherwise convert
2071 * to the non-imm variant.
2073 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2075 mono_decompose_op_imm (cfg, bb, ins);
2082 bb->max_vreg = cfg->next_vreg;
2086 branch_cc_table [] = {
2087 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2088 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2089 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2092 /* Maps CMP_... constants to X86_CC_... constants */
2095 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2096 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2100 cc_signed_table [] = {
2101 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2102 FALSE, FALSE, FALSE, FALSE
2105 static unsigned char*
2106 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2108 #define XMM_TEMP_REG 0
2109 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2110 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2111 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2112 /* optimize by assigning a local var for this use so we avoid
2113 * the stack manipulations */
2114 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2115 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2116 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2117 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2118 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2120 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2122 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2125 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2126 x86_fnstcw_membase(code, X86_ESP, 0);
2127 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2128 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2129 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2130 x86_fldcw_membase (code, X86_ESP, 2);
2132 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2133 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2134 x86_pop_reg (code, dreg);
2135 /* FIXME: need the high register
2136 * x86_pop_reg (code, dreg_high);
2139 x86_push_reg (code, X86_EAX); // SP = SP - 4
2140 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2141 x86_pop_reg (code, dreg);
2143 x86_fldcw_membase (code, X86_ESP, 0);
2144 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2147 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2149 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2153 static unsigned char*
2154 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2156 int sreg = tree->sreg1;
2157 int need_touch = FALSE;
2159 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2168 * If requested stack size is larger than one page,
2169 * perform stack-touch operation
2172 * Generate stack probe code.
2173 * Under Windows, it is necessary to allocate one page at a time,
2174 * "touching" stack after each successful sub-allocation. This is
2175 * because of the way stack growth is implemented - there is a
2176 * guard page before the lowest stack page that is currently commited.
2177 * Stack normally grows sequentially so OS traps access to the
2178 * guard page and commits more pages when needed.
2180 x86_test_reg_imm (code, sreg, ~0xFFF);
2181 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2183 br[2] = code; /* loop */
2184 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2185 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2188 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2189 * that follows only initializes the last part of the area.
2191 /* Same as the init code below with size==0x1000 */
2192 if (tree->flags & MONO_INST_INIT) {
2193 x86_push_reg (code, X86_EAX);
2194 x86_push_reg (code, X86_ECX);
2195 x86_push_reg (code, X86_EDI);
2196 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2197 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2198 if (cfg->param_area)
2199 x86_lea_membase (code, X86_EDI, X86_ESP, 12 + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2201 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2203 x86_prefix (code, X86_REP_PREFIX);
2205 x86_pop_reg (code, X86_EDI);
2206 x86_pop_reg (code, X86_ECX);
2207 x86_pop_reg (code, X86_EAX);
2210 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2211 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2212 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2213 x86_patch (br[3], br[2]);
2214 x86_test_reg_reg (code, sreg, sreg);
2215 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2216 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2218 br[1] = code; x86_jump8 (code, 0);
2220 x86_patch (br[0], code);
2221 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2222 x86_patch (br[1], code);
2223 x86_patch (br[4], code);
2226 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2228 if (tree->flags & MONO_INST_INIT) {
2230 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2231 x86_push_reg (code, X86_EAX);
2234 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2235 x86_push_reg (code, X86_ECX);
2238 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2239 x86_push_reg (code, X86_EDI);
2243 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2244 if (sreg != X86_ECX)
2245 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2246 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2248 if (cfg->param_area)
2249 x86_lea_membase (code, X86_EDI, X86_ESP, offset + ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
2251 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2253 x86_prefix (code, X86_REP_PREFIX);
2256 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2257 x86_pop_reg (code, X86_EDI);
2258 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2259 x86_pop_reg (code, X86_ECX);
2260 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2261 x86_pop_reg (code, X86_EAX);
2268 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2270 /* Move return value to the target register */
2271 switch (ins->opcode) {
2274 case OP_CALL_MEMBASE:
2275 if (ins->dreg != X86_EAX)
2276 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2286 static int tls_gs_offset;
2290 mono_x86_have_tls_get (void)
2293 static gboolean have_tls_get = FALSE;
2294 static gboolean inited = FALSE;
2298 return have_tls_get;
2300 ins = (guint32*)pthread_getspecific;
2302 * We're looking for these two instructions:
2304 * mov 0x4(%esp),%eax
2305 * mov %gs:[offset](,%eax,4),%eax
2307 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2308 tls_gs_offset = ins [2];
2312 return have_tls_get;
2313 #elif defined(TARGET_ANDROID)
2321 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2323 #if defined(__APPLE__)
2324 x86_prefix (code, X86_GS_PREFIX);
2325 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2326 #elif defined(TARGET_WIN32)
2327 g_assert_not_reached ();
2329 x86_prefix (code, X86_GS_PREFIX);
2330 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2336 * mono_x86_emit_tls_get:
2337 * @code: buffer to store code to
2338 * @dreg: hard register where to place the result
2339 * @tls_offset: offset info
2341 * mono_x86_emit_tls_get emits in @code the native code that puts in
2342 * the dreg register the item in the thread local storage identified
2345 * Returns: a pointer to the end of the stored code
2348 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2350 #if defined(__APPLE__)
2351 x86_prefix (code, X86_GS_PREFIX);
2352 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2353 #elif defined(TARGET_WIN32)
2355 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2356 * Journal and/or a disassembly of the TlsGet () function.
2358 x86_prefix (code, X86_FS_PREFIX);
2359 x86_mov_reg_mem (code, dreg, 0x18, 4);
2360 if (tls_offset < 64) {
2361 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2365 g_assert (tls_offset < 0x440);
2366 /* Load TEB->TlsExpansionSlots */
2367 x86_mov_reg_membase (code, dreg, dreg, 0xf94, 4);
2368 x86_test_reg_reg (code, dreg, dreg);
2370 x86_branch (code, X86_CC_EQ, code, TRUE);
2371 x86_mov_reg_membase (code, dreg, dreg, (tls_offset * 4) - 0x100, 4);
2372 x86_patch (buf [0], code);
2375 if (optimize_for_xen) {
2376 x86_prefix (code, X86_GS_PREFIX);
2377 x86_mov_reg_mem (code, dreg, 0, 4);
2378 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2380 x86_prefix (code, X86_GS_PREFIX);
2381 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2388 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2390 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2391 #if defined(__APPLE__) || defined(__linux__)
2392 if (dreg != offset_reg)
2393 x86_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
2394 x86_prefix (code, X86_GS_PREFIX);
2395 x86_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
2397 g_assert_not_reached ();
2403 mono_x86_emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
2405 return emit_tls_get_reg (code, dreg, offset_reg);
2409 emit_tls_set_reg (guint8* code, int sreg, int offset_reg)
2411 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
2413 g_assert_not_reached ();
2414 #elif defined(__APPLE__) || defined(__linux__)
2415 x86_prefix (code, X86_GS_PREFIX);
2416 x86_mov_membase_reg (code, offset_reg, 0, sreg, sizeof (mgreg_t));
2418 g_assert_not_reached ();
2424 * mono_arch_translate_tls_offset:
2426 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
2429 mono_arch_translate_tls_offset (int offset)
2432 return tls_gs_offset + (offset * 4);
2441 * Emit code to initialize an LMF structure at LMF_OFFSET.
2444 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
2446 /* save all caller saved regs */
2447 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), X86_EBX, sizeof (mgreg_t));
2448 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx));
2449 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), X86_EDI, sizeof (mgreg_t));
2450 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi));
2451 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), X86_ESI, sizeof (mgreg_t));
2452 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi));
2453 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), X86_EBP, sizeof (mgreg_t));
2455 /* save the current IP */
2456 if (cfg->compile_aot) {
2457 /* This pushes the current ip */
2458 x86_call_imm (code, 0);
2459 x86_pop_reg (code, X86_EAX);
2461 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
2462 x86_mov_reg_imm (code, X86_EAX, 0);
2464 x86_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), X86_EAX, sizeof (mgreg_t));
2466 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, eip), SLOT_NOREF);
2467 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebp), SLOT_NOREF);
2468 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), SLOT_NOREF);
2469 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), SLOT_NOREF);
2470 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), SLOT_NOREF);
2471 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esp), SLOT_NOREF);
2472 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
2473 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
2474 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
2479 #define REAL_PRINT_REG(text,reg) \
2480 mono_assert (reg >= 0); \
2481 x86_push_reg (code, X86_EAX); \
2482 x86_push_reg (code, X86_EDX); \
2483 x86_push_reg (code, X86_ECX); \
2484 x86_push_reg (code, reg); \
2485 x86_push_imm (code, reg); \
2486 x86_push_imm (code, text " %d %p\n"); \
2487 x86_mov_reg_imm (code, X86_EAX, printf); \
2488 x86_call_reg (code, X86_EAX); \
2489 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2490 x86_pop_reg (code, X86_ECX); \
2491 x86_pop_reg (code, X86_EDX); \
2492 x86_pop_reg (code, X86_EAX);
2494 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2495 #ifdef __native__client_codegen__
2496 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2499 /* benchmark and set based on cpu */
2500 #define LOOP_ALIGNMENT 8
2501 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2505 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2510 guint8 *code = cfg->native_code + cfg->code_len;
2513 if (cfg->opt & MONO_OPT_LOOP) {
2514 int pad, align = LOOP_ALIGNMENT;
2515 /* set alignment depending on cpu */
2516 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2518 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2519 x86_padding (code, pad);
2520 cfg->code_len += pad;
2521 bb->native_offset = cfg->code_len;
2524 #ifdef __native_client_codegen__
2526 /* For Native Client, all indirect call/jump targets must be */
2527 /* 32-byte aligned. Exception handler blocks are jumped to */
2528 /* indirectly as well. */
2529 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2530 (bb->flags & BB_EXCEPTION_HANDLER);
2532 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2533 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2534 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2535 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2536 cfg->code_len += pad;
2537 bb->native_offset = cfg->code_len;
2540 #endif /* __native_client_codegen__ */
2541 if (cfg->verbose_level > 2)
2542 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2544 cpos = bb->max_offset;
2546 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2547 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2548 g_assert (!cfg->compile_aot);
2551 cov->data [bb->dfn].cil_code = bb->cil_code;
2552 /* this is not thread save, but good enough */
2553 x86_inc_mem (code, &cov->data [bb->dfn].count);
2556 offset = code - cfg->native_code;
2558 mono_debug_open_block (cfg, bb, offset);
2560 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2561 x86_breakpoint (code);
2563 MONO_BB_FOR_EACH_INS (bb, ins) {
2564 offset = code - cfg->native_code;
2566 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2568 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2570 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2571 cfg->code_size *= 2;
2572 cfg->native_code = mono_realloc_native_code(cfg);
2573 code = cfg->native_code + offset;
2574 cfg->stat_code_reallocs++;
2577 if (cfg->debug_info)
2578 mono_debug_record_line_number (cfg, ins, offset);
2580 switch (ins->opcode) {
2582 x86_mul_reg (code, ins->sreg2, TRUE);
2585 x86_mul_reg (code, ins->sreg2, FALSE);
2587 case OP_X86_SETEQ_MEMBASE:
2588 case OP_X86_SETNE_MEMBASE:
2589 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2590 ins->inst_basereg, ins->inst_offset, TRUE);
2592 case OP_STOREI1_MEMBASE_IMM:
2593 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2595 case OP_STOREI2_MEMBASE_IMM:
2596 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2598 case OP_STORE_MEMBASE_IMM:
2599 case OP_STOREI4_MEMBASE_IMM:
2600 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2602 case OP_STOREI1_MEMBASE_REG:
2603 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2605 case OP_STOREI2_MEMBASE_REG:
2606 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2608 case OP_STORE_MEMBASE_REG:
2609 case OP_STOREI4_MEMBASE_REG:
2610 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2612 case OP_STORE_MEM_IMM:
2613 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2616 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2620 /* These are created by the cprop pass so they use inst_imm as the source */
2621 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2624 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2627 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2629 case OP_LOAD_MEMBASE:
2630 case OP_LOADI4_MEMBASE:
2631 case OP_LOADU4_MEMBASE:
2632 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2634 case OP_LOADU1_MEMBASE:
2635 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2637 case OP_LOADI1_MEMBASE:
2638 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2640 case OP_LOADU2_MEMBASE:
2641 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2643 case OP_LOADI2_MEMBASE:
2644 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2646 case OP_ICONV_TO_I1:
2648 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2650 case OP_ICONV_TO_I2:
2652 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2654 case OP_ICONV_TO_U1:
2655 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2657 case OP_ICONV_TO_U2:
2658 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2662 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2664 case OP_COMPARE_IMM:
2665 case OP_ICOMPARE_IMM:
2666 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2668 case OP_X86_COMPARE_MEMBASE_REG:
2669 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2671 case OP_X86_COMPARE_MEMBASE_IMM:
2672 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2674 case OP_X86_COMPARE_MEMBASE8_IMM:
2675 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2677 case OP_X86_COMPARE_REG_MEMBASE:
2678 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2680 case OP_X86_COMPARE_MEM_IMM:
2681 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2683 case OP_X86_TEST_NULL:
2684 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2686 case OP_X86_ADD_MEMBASE_IMM:
2687 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2689 case OP_X86_ADD_REG_MEMBASE:
2690 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2692 case OP_X86_SUB_MEMBASE_IMM:
2693 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2695 case OP_X86_SUB_REG_MEMBASE:
2696 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2698 case OP_X86_AND_MEMBASE_IMM:
2699 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2701 case OP_X86_OR_MEMBASE_IMM:
2702 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2704 case OP_X86_XOR_MEMBASE_IMM:
2705 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2707 case OP_X86_ADD_MEMBASE_REG:
2708 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2710 case OP_X86_SUB_MEMBASE_REG:
2711 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2713 case OP_X86_AND_MEMBASE_REG:
2714 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2716 case OP_X86_OR_MEMBASE_REG:
2717 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2719 case OP_X86_XOR_MEMBASE_REG:
2720 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2722 case OP_X86_INC_MEMBASE:
2723 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2725 case OP_X86_INC_REG:
2726 x86_inc_reg (code, ins->dreg);
2728 case OP_X86_DEC_MEMBASE:
2729 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2731 case OP_X86_DEC_REG:
2732 x86_dec_reg (code, ins->dreg);
2734 case OP_X86_MUL_REG_MEMBASE:
2735 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2737 case OP_X86_AND_REG_MEMBASE:
2738 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2740 case OP_X86_OR_REG_MEMBASE:
2741 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2743 case OP_X86_XOR_REG_MEMBASE:
2744 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2747 x86_breakpoint (code);
2749 case OP_RELAXED_NOP:
2750 x86_prefix (code, X86_REP_PREFIX);
2758 case OP_DUMMY_STORE:
2759 case OP_DUMMY_ICONST:
2760 case OP_DUMMY_R8CONST:
2761 case OP_NOT_REACHED:
2764 case OP_IL_SEQ_POINT:
2765 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2767 case OP_SEQ_POINT: {
2770 if (cfg->compile_aot)
2774 * Read from the single stepping trigger page. This will cause a
2775 * SIGSEGV when single stepping is enabled.
2776 * We do this _before_ the breakpoint, so single stepping after
2777 * a breakpoint is hit will step to the next IL offset.
2779 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2780 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2782 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2785 * A placeholder for a possible breakpoint inserted by
2786 * mono_arch_set_breakpoint ().
2788 for (i = 0; i < 6; ++i)
2791 * Add an additional nop so skipping the bp doesn't cause the ip to point
2792 * to another IL offset.
2800 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2804 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2809 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2813 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2818 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2822 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2827 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2831 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2834 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2838 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2842 #if defined( __native_client_codegen__ )
2843 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2844 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2847 * The code is the same for div/rem, the allocator will allocate dreg
2848 * to RAX/RDX as appropriate.
2850 if (ins->sreg2 == X86_EDX) {
2851 /* cdq clobbers this */
2852 x86_push_reg (code, ins->sreg2);
2854 x86_div_membase (code, X86_ESP, 0, TRUE);
2855 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2858 x86_div_reg (code, ins->sreg2, TRUE);
2863 #if defined( __native_client_codegen__ )
2864 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2865 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2867 if (ins->sreg2 == X86_EDX) {
2868 x86_push_reg (code, ins->sreg2);
2869 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2870 x86_div_membase (code, X86_ESP, 0, FALSE);
2871 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2873 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2874 x86_div_reg (code, ins->sreg2, FALSE);
2878 #if defined( __native_client_codegen__ )
2879 if (ins->inst_imm == 0) {
2880 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2881 x86_jump32 (code, 0);
2885 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2887 x86_div_reg (code, ins->sreg2, TRUE);
2890 int power = mono_is_power_of_two (ins->inst_imm);
2892 g_assert (ins->sreg1 == X86_EAX);
2893 g_assert (ins->dreg == X86_EAX);
2894 g_assert (power >= 0);
2897 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2899 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2901 * If the divident is >= 0, this does not nothing. If it is positive, it
2902 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2904 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2905 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2906 } else if (power == 0) {
2907 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2909 /* Based on gcc code */
2911 /* Add compensation for negative dividents */
2913 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2914 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2915 /* Compute remainder */
2916 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2917 /* Remove compensation */
2918 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2923 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2927 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2930 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2934 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2937 g_assert (ins->sreg2 == X86_ECX);
2938 x86_shift_reg (code, X86_SHL, ins->dreg);
2941 g_assert (ins->sreg2 == X86_ECX);
2942 x86_shift_reg (code, X86_SAR, ins->dreg);
2946 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2949 case OP_ISHR_UN_IMM:
2950 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2953 g_assert (ins->sreg2 == X86_ECX);
2954 x86_shift_reg (code, X86_SHR, ins->dreg);
2958 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2961 guint8 *jump_to_end;
2963 /* handle shifts below 32 bits */
2964 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2965 x86_shift_reg (code, X86_SHL, ins->sreg1);
2967 x86_test_reg_imm (code, X86_ECX, 32);
2968 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2970 /* handle shift over 32 bit */
2971 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2972 x86_clear_reg (code, ins->sreg1);
2974 x86_patch (jump_to_end, code);
2978 guint8 *jump_to_end;
2980 /* handle shifts below 32 bits */
2981 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2982 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2984 x86_test_reg_imm (code, X86_ECX, 32);
2985 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
2987 /* handle shifts over 31 bits */
2988 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
2989 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
2991 x86_patch (jump_to_end, code);
2995 guint8 *jump_to_end;
2997 /* handle shifts below 32 bits */
2998 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2999 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3001 x86_test_reg_imm (code, X86_ECX, 32);
3002 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3004 /* handle shifts over 31 bits */
3005 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3006 x86_clear_reg (code, ins->backend.reg3);
3008 x86_patch (jump_to_end, code);
3012 if (ins->inst_imm >= 32) {
3013 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3014 x86_clear_reg (code, ins->sreg1);
3015 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3017 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3018 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3022 if (ins->inst_imm >= 32) {
3023 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3024 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3025 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3027 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3028 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3031 case OP_LSHR_UN_IMM:
3032 if (ins->inst_imm >= 32) {
3033 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3034 x86_clear_reg (code, ins->backend.reg3);
3035 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3037 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3038 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3042 x86_not_reg (code, ins->sreg1);
3045 x86_neg_reg (code, ins->sreg1);
3049 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3053 switch (ins->inst_imm) {
3057 if (ins->dreg != ins->sreg1)
3058 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3059 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3062 /* LEA r1, [r2 + r2*2] */
3063 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3066 /* LEA r1, [r2 + r2*4] */
3067 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3070 /* LEA r1, [r2 + r2*2] */
3072 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3073 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3076 /* LEA r1, [r2 + r2*8] */
3077 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3080 /* LEA r1, [r2 + r2*4] */
3082 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3083 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3086 /* LEA r1, [r2 + r2*2] */
3088 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3089 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3092 /* LEA r1, [r2 + r2*4] */
3093 /* LEA r1, [r1 + r1*4] */
3094 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3095 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3098 /* LEA r1, [r2 + r2*4] */
3100 /* LEA r1, [r1 + r1*4] */
3101 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3102 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3103 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3106 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3111 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3112 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3114 case OP_IMUL_OVF_UN: {
3115 /* the mul operation and the exception check should most likely be split */
3116 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3117 /*g_assert (ins->sreg2 == X86_EAX);
3118 g_assert (ins->dreg == X86_EAX);*/
3119 if (ins->sreg2 == X86_EAX) {
3120 non_eax_reg = ins->sreg1;
3121 } else if (ins->sreg1 == X86_EAX) {
3122 non_eax_reg = ins->sreg2;
3124 /* no need to save since we're going to store to it anyway */
3125 if (ins->dreg != X86_EAX) {
3127 x86_push_reg (code, X86_EAX);
3129 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3130 non_eax_reg = ins->sreg2;
3132 if (ins->dreg == X86_EDX) {
3135 x86_push_reg (code, X86_EAX);
3137 } else if (ins->dreg != X86_EAX) {
3139 x86_push_reg (code, X86_EDX);
3141 x86_mul_reg (code, non_eax_reg, FALSE);
3142 /* save before the check since pop and mov don't change the flags */
3143 if (ins->dreg != X86_EAX)
3144 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3146 x86_pop_reg (code, X86_EDX);
3148 x86_pop_reg (code, X86_EAX);
3149 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3153 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3156 g_assert_not_reached ();
3157 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3158 x86_mov_reg_imm (code, ins->dreg, 0);
3161 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3162 x86_mov_reg_imm (code, ins->dreg, 0);
3164 case OP_LOAD_GOTADDR:
3165 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3166 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3169 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3170 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3172 case OP_X86_PUSH_GOT_ENTRY:
3173 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3174 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3177 if (ins->dreg != ins->sreg1)
3178 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3181 MonoCallInst *call = (MonoCallInst*)ins;
3184 ins->flags |= MONO_INST_GC_CALLSITE;
3185 ins->backend.pc_offset = code - cfg->native_code;
3187 /* reset offset to make max_len work */
3188 offset = code - cfg->native_code;
3190 g_assert (!cfg->method->save_lmf);
3192 /* restore callee saved registers */
3193 for (i = 0; i < X86_NREG; ++i)
3194 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3196 if (cfg->used_int_regs & (1 << X86_ESI)) {
3197 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3200 if (cfg->used_int_regs & (1 << X86_EDI)) {
3201 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3204 if (cfg->used_int_regs & (1 << X86_EBX)) {
3205 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3209 /* Copy arguments on the stack to our argument area */
3210 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3211 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3212 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3215 /* restore ESP/EBP */
3217 offset = code - cfg->native_code;
3218 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, call->method);
3219 x86_jump32 (code, 0);
3221 ins->flags |= MONO_INST_GC_CALLSITE;
3222 cfg->disable_aot = TRUE;
3226 /* ensure ins->sreg1 is not NULL
3227 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3228 * cmp DWORD PTR [eax], 0
3230 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3233 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3234 x86_push_reg (code, hreg);
3235 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3236 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3237 x86_pop_reg (code, hreg);
3250 case OP_VOIDCALL_REG:
3252 case OP_FCALL_MEMBASE:
3253 case OP_LCALL_MEMBASE:
3254 case OP_VCALL_MEMBASE:
3255 case OP_VCALL2_MEMBASE:
3256 case OP_VOIDCALL_MEMBASE:
3257 case OP_CALL_MEMBASE: {
3260 call = (MonoCallInst*)ins;
3261 cinfo = (CallInfo*)call->call_info;
3263 switch (ins->opcode) {
3270 if (ins->flags & MONO_INST_HAS_METHOD)
3271 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3273 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3279 case OP_VOIDCALL_REG:
3281 x86_call_reg (code, ins->sreg1);
3283 case OP_FCALL_MEMBASE:
3284 case OP_LCALL_MEMBASE:
3285 case OP_VCALL_MEMBASE:
3286 case OP_VCALL2_MEMBASE:
3287 case OP_VOIDCALL_MEMBASE:
3288 case OP_CALL_MEMBASE:
3289 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3292 g_assert_not_reached ();
3295 ins->flags |= MONO_INST_GC_CALLSITE;
3296 ins->backend.pc_offset = code - cfg->native_code;
3297 if (cinfo->callee_stack_pop) {
3298 /* Have to compensate for the stack space popped by the callee */
3299 x86_alu_reg_imm (code, X86_SUB, X86_ESP, cinfo->callee_stack_pop);
3301 code = emit_move_return_value (cfg, ins, code);
3305 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3307 case OP_X86_LEA_MEMBASE:
3308 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3311 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3314 /* keep alignment */
3315 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3316 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3317 code = mono_emit_stack_alloc (cfg, code, ins);
3318 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3319 if (cfg->param_area)
3320 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3322 case OP_LOCALLOC_IMM: {
3323 guint32 size = ins->inst_imm;
3324 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3326 if (ins->flags & MONO_INST_INIT) {
3327 /* FIXME: Optimize this */
3328 x86_mov_reg_imm (code, ins->dreg, size);
3329 ins->sreg1 = ins->dreg;
3331 code = mono_emit_stack_alloc (cfg, code, ins);
3332 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3334 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3335 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3337 if (cfg->param_area)
3338 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3342 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3343 x86_push_reg (code, ins->sreg1);
3344 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3345 (gpointer)"mono_arch_throw_exception");
3346 ins->flags |= MONO_INST_GC_CALLSITE;
3347 ins->backend.pc_offset = code - cfg->native_code;
3351 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3352 x86_push_reg (code, ins->sreg1);
3353 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3354 (gpointer)"mono_arch_rethrow_exception");
3355 ins->flags |= MONO_INST_GC_CALLSITE;
3356 ins->backend.pc_offset = code - cfg->native_code;
3359 case OP_CALL_HANDLER:
3360 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3361 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3362 x86_call_imm (code, 0);
3363 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3364 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3366 case OP_START_HANDLER: {
3367 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3368 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3369 if (cfg->param_area)
3370 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3373 case OP_ENDFINALLY: {
3374 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3375 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3379 case OP_ENDFILTER: {
3380 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3381 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3382 /* The local allocator will put the result into EAX */
3388 ins->inst_c0 = code - cfg->native_code;
3391 if (ins->inst_target_bb->native_offset) {
3392 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3394 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3395 if ((cfg->opt & MONO_OPT_BRANCH) &&
3396 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3397 x86_jump8 (code, 0);
3399 x86_jump32 (code, 0);
3403 x86_jump_reg (code, ins->sreg1);
3422 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3423 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3425 case OP_COND_EXC_EQ:
3426 case OP_COND_EXC_NE_UN:
3427 case OP_COND_EXC_LT:
3428 case OP_COND_EXC_LT_UN:
3429 case OP_COND_EXC_GT:
3430 case OP_COND_EXC_GT_UN:
3431 case OP_COND_EXC_GE:
3432 case OP_COND_EXC_GE_UN:
3433 case OP_COND_EXC_LE:
3434 case OP_COND_EXC_LE_UN:
3435 case OP_COND_EXC_IEQ:
3436 case OP_COND_EXC_INE_UN:
3437 case OP_COND_EXC_ILT:
3438 case OP_COND_EXC_ILT_UN:
3439 case OP_COND_EXC_IGT:
3440 case OP_COND_EXC_IGT_UN:
3441 case OP_COND_EXC_IGE:
3442 case OP_COND_EXC_IGE_UN:
3443 case OP_COND_EXC_ILE:
3444 case OP_COND_EXC_ILE_UN:
3445 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3447 case OP_COND_EXC_OV:
3448 case OP_COND_EXC_NO:
3450 case OP_COND_EXC_NC:
3451 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3453 case OP_COND_EXC_IOV:
3454 case OP_COND_EXC_INO:
3455 case OP_COND_EXC_IC:
3456 case OP_COND_EXC_INC:
3457 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3469 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3477 case OP_CMOV_INE_UN:
3478 case OP_CMOV_IGE_UN:
3479 case OP_CMOV_IGT_UN:
3480 case OP_CMOV_ILE_UN:
3481 case OP_CMOV_ILT_UN:
3482 g_assert (ins->dreg == ins->sreg1);
3483 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3486 /* floating point opcodes */
3488 double d = *(double *)ins->inst_p0;
3490 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3492 } else if (d == 1.0) {
3495 if (cfg->compile_aot) {
3496 guint32 *val = (guint32*)&d;
3497 x86_push_imm (code, val [1]);
3498 x86_push_imm (code, val [0]);
3499 x86_fld_membase (code, X86_ESP, 0, TRUE);
3500 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3503 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3504 x86_fld (code, NULL, TRUE);
3510 float f = *(float *)ins->inst_p0;
3512 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3514 } else if (f == 1.0) {
3517 if (cfg->compile_aot) {
3518 guint32 val = *(guint32*)&f;
3519 x86_push_imm (code, val);
3520 x86_fld_membase (code, X86_ESP, 0, FALSE);
3521 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3524 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3525 x86_fld (code, NULL, FALSE);
3530 case OP_STORER8_MEMBASE_REG:
3531 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3533 case OP_LOADR8_MEMBASE:
3534 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3536 case OP_STORER4_MEMBASE_REG:
3537 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3539 case OP_LOADR4_MEMBASE:
3540 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3542 case OP_ICONV_TO_R4:
3543 x86_push_reg (code, ins->sreg1);
3544 x86_fild_membase (code, X86_ESP, 0, FALSE);
3545 /* Change precision */
3546 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3547 x86_fld_membase (code, X86_ESP, 0, FALSE);
3548 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3550 case OP_ICONV_TO_R8:
3551 x86_push_reg (code, ins->sreg1);
3552 x86_fild_membase (code, X86_ESP, 0, FALSE);
3553 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3555 case OP_ICONV_TO_R_UN:
3556 x86_push_imm (code, 0);
3557 x86_push_reg (code, ins->sreg1);
3558 x86_fild_membase (code, X86_ESP, 0, TRUE);
3559 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3561 case OP_X86_FP_LOAD_I8:
3562 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3564 case OP_X86_FP_LOAD_I4:
3565 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3567 case OP_FCONV_TO_R4:
3568 /* Change precision */
3569 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3570 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3571 x86_fld_membase (code, X86_ESP, 0, FALSE);
3572 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3574 case OP_FCONV_TO_I1:
3575 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3577 case OP_FCONV_TO_U1:
3578 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3580 case OP_FCONV_TO_I2:
3581 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3583 case OP_FCONV_TO_U2:
3584 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3586 case OP_FCONV_TO_I4:
3588 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3590 case OP_FCONV_TO_I8:
3591 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3592 x86_fnstcw_membase(code, X86_ESP, 0);
3593 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3594 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3595 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3596 x86_fldcw_membase (code, X86_ESP, 2);
3597 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3598 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3599 x86_pop_reg (code, ins->dreg);
3600 x86_pop_reg (code, ins->backend.reg3);
3601 x86_fldcw_membase (code, X86_ESP, 0);
3602 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3604 case OP_LCONV_TO_R8_2:
3605 x86_push_reg (code, ins->sreg2);
3606 x86_push_reg (code, ins->sreg1);
3607 x86_fild_membase (code, X86_ESP, 0, TRUE);
3608 /* Change precision */
3609 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3610 x86_fld_membase (code, X86_ESP, 0, TRUE);
3611 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3613 case OP_LCONV_TO_R4_2:
3614 x86_push_reg (code, ins->sreg2);
3615 x86_push_reg (code, ins->sreg1);
3616 x86_fild_membase (code, X86_ESP, 0, TRUE);
3617 /* Change precision */
3618 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3619 x86_fld_membase (code, X86_ESP, 0, FALSE);
3620 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3622 case OP_LCONV_TO_R_UN_2: {
3623 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3626 /* load 64bit integer to FP stack */
3627 x86_push_reg (code, ins->sreg2);
3628 x86_push_reg (code, ins->sreg1);
3629 x86_fild_membase (code, X86_ESP, 0, TRUE);
3631 /* test if lreg is negative */
3632 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3633 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3635 /* add correction constant mn */
3636 if (cfg->compile_aot) {
3637 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3638 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3639 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3640 x86_fld80_membase (code, X86_ESP, 2);
3641 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3643 x86_fld80_mem (code, mn);
3645 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3647 x86_patch (br, code);
3649 /* Change precision */
3650 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3651 x86_fld_membase (code, X86_ESP, 0, TRUE);
3653 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3657 case OP_LCONV_TO_OVF_I:
3658 case OP_LCONV_TO_OVF_I4_2: {
3659 guint8 *br [3], *label [1];
3663 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3665 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3667 /* If the low word top bit is set, see if we are negative */
3668 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3669 /* We are not negative (no top bit set, check for our top word to be zero */
3670 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3671 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3674 /* throw exception */
3675 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3677 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3678 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3679 x86_jump8 (code, 0);
3681 x86_jump32 (code, 0);
3683 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3684 x86_jump32 (code, 0);
3688 x86_patch (br [0], code);
3689 /* our top bit is set, check that top word is 0xfffffff */
3690 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3692 x86_patch (br [1], code);
3693 /* nope, emit exception */
3694 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3695 x86_patch (br [2], label [0]);
3697 if (ins->dreg != ins->sreg1)
3698 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3702 /* Not needed on the fp stack */
3704 case OP_MOVE_F_TO_I4:
3705 x86_push_reg (code, X86_EAX);
3706 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3707 x86_pop_reg (code, ins->dreg);
3709 case OP_MOVE_I4_TO_F:
3710 x86_push_reg (code, ins->sreg1);
3711 x86_fld_membase (code, X86_ESP, 0, FALSE);
3712 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3715 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3718 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3721 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3724 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3732 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3737 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3744 * it really doesn't make sense to inline all this code,
3745 * it's here just to show that things may not be as simple
3748 guchar *check_pos, *end_tan, *pop_jump;
3749 x86_push_reg (code, X86_EAX);
3752 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3754 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3755 x86_fstp (code, 0); /* pop the 1.0 */
3757 x86_jump8 (code, 0);
3759 x86_fp_op (code, X86_FADD, 0);
3763 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3765 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3768 x86_patch (pop_jump, code);
3769 x86_fstp (code, 0); /* pop the 1.0 */
3770 x86_patch (check_pos, code);
3771 x86_patch (end_tan, code);
3773 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3774 x86_pop_reg (code, X86_EAX);
3781 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3790 g_assert (cfg->opt & MONO_OPT_CMOV);
3791 g_assert (ins->dreg == ins->sreg1);
3792 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3793 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3796 g_assert (cfg->opt & MONO_OPT_CMOV);
3797 g_assert (ins->dreg == ins->sreg1);
3798 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3799 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3802 g_assert (cfg->opt & MONO_OPT_CMOV);
3803 g_assert (ins->dreg == ins->sreg1);
3804 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3805 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3808 g_assert (cfg->opt & MONO_OPT_CMOV);
3809 g_assert (ins->dreg == ins->sreg1);
3810 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3811 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3817 x86_fxch (code, ins->inst_imm);
3822 x86_push_reg (code, X86_EAX);
3823 /* we need to exchange ST(0) with ST(1) */
3826 /* this requires a loop, because fprem somtimes
3827 * returns a partial remainder */
3829 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3830 /* x86_fprem1 (code); */
3833 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3835 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3841 x86_pop_reg (code, X86_EAX);
3845 if (cfg->opt & MONO_OPT_FCMOV) {
3846 x86_fcomip (code, 1);
3850 /* this overwrites EAX */
3851 EMIT_FPCOMPARE(code);
3852 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3856 if (cfg->opt & MONO_OPT_FCMOV) {
3857 /* zeroing the register at the start results in
3858 * shorter and faster code (we can also remove the widening op)
3860 guchar *unordered_check;
3861 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3862 x86_fcomip (code, 1);
3864 unordered_check = code;
3865 x86_branch8 (code, X86_CC_P, 0, FALSE);
3866 if (ins->opcode == OP_FCEQ) {
3867 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3868 x86_patch (unordered_check, code);
3870 guchar *jump_to_end;
3871 x86_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
3873 x86_jump8 (code, 0);
3874 x86_patch (unordered_check, code);
3875 x86_inc_reg (code, ins->dreg);
3876 x86_patch (jump_to_end, code);
3881 if (ins->dreg != X86_EAX)
3882 x86_push_reg (code, X86_EAX);
3884 EMIT_FPCOMPARE(code);
3885 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3886 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3887 x86_set_reg (code, ins->opcode == OP_FCEQ ? X86_CC_EQ : X86_CC_NE, ins->dreg, TRUE);
3888 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3890 if (ins->dreg != X86_EAX)
3891 x86_pop_reg (code, X86_EAX);
3895 if (cfg->opt & MONO_OPT_FCMOV) {
3896 /* zeroing the register at the start results in
3897 * shorter and faster code (we can also remove the widening op)
3899 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3900 x86_fcomip (code, 1);
3902 if (ins->opcode == OP_FCLT_UN) {
3903 guchar *unordered_check = code;
3904 guchar *jump_to_end;
3905 x86_branch8 (code, X86_CC_P, 0, FALSE);
3906 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3908 x86_jump8 (code, 0);
3909 x86_patch (unordered_check, code);
3910 x86_inc_reg (code, ins->dreg);
3911 x86_patch (jump_to_end, code);
3913 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3917 if (ins->dreg != X86_EAX)
3918 x86_push_reg (code, X86_EAX);
3920 EMIT_FPCOMPARE(code);
3921 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3922 if (ins->opcode == OP_FCLT_UN) {
3923 guchar *is_not_zero_check, *end_jump;
3924 is_not_zero_check = code;
3925 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3927 x86_jump8 (code, 0);
3928 x86_patch (is_not_zero_check, code);
3929 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3931 x86_patch (end_jump, code);
3933 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3934 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3936 if (ins->dreg != X86_EAX)
3937 x86_pop_reg (code, X86_EAX);
3940 guchar *unordered_check;
3941 guchar *jump_to_end;
3942 if (cfg->opt & MONO_OPT_FCMOV) {
3943 /* zeroing the register at the start results in
3944 * shorter and faster code (we can also remove the widening op)
3946 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3947 x86_fcomip (code, 1);
3949 unordered_check = code;
3950 x86_branch8 (code, X86_CC_P, 0, FALSE);
3951 x86_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
3952 x86_patch (unordered_check, code);
3955 if (ins->dreg != X86_EAX)
3956 x86_push_reg (code, X86_EAX);
3958 EMIT_FPCOMPARE(code);
3959 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3960 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
3961 unordered_check = code;
3962 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3964 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
3965 x86_set_reg (code, X86_CC_NE, ins->dreg, TRUE);
3966 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3968 x86_jump8 (code, 0);
3969 x86_patch (unordered_check, code);
3970 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3971 x86_patch (jump_to_end, code);
3973 if (ins->dreg != X86_EAX)
3974 x86_pop_reg (code, X86_EAX);
3979 if (cfg->opt & MONO_OPT_FCMOV) {
3980 /* zeroing the register at the start results in
3981 * shorter and faster code (we can also remove the widening op)
3983 guchar *unordered_check;
3984 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3985 x86_fcomip (code, 1);
3987 if (ins->opcode == OP_FCGT) {
3988 unordered_check = code;
3989 x86_branch8 (code, X86_CC_P, 0, FALSE);
3990 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3991 x86_patch (unordered_check, code);
3993 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3997 if (ins->dreg != X86_EAX)
3998 x86_push_reg (code, X86_EAX);
4000 EMIT_FPCOMPARE(code);
4001 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4002 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4003 if (ins->opcode == OP_FCGT_UN) {
4004 guchar *is_not_zero_check, *end_jump;
4005 is_not_zero_check = code;
4006 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4008 x86_jump8 (code, 0);
4009 x86_patch (is_not_zero_check, code);
4010 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4012 x86_patch (end_jump, code);
4014 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4015 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4017 if (ins->dreg != X86_EAX)
4018 x86_pop_reg (code, X86_EAX);
4021 guchar *unordered_check;
4022 guchar *jump_to_end;
4023 if (cfg->opt & MONO_OPT_FCMOV) {
4024 /* zeroing the register at the start results in
4025 * shorter and faster code (we can also remove the widening op)
4027 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4028 x86_fcomip (code, 1);
4030 unordered_check = code;
4031 x86_branch8 (code, X86_CC_P, 0, FALSE);
4032 x86_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
4033 x86_patch (unordered_check, code);
4036 if (ins->dreg != X86_EAX)
4037 x86_push_reg (code, X86_EAX);
4039 EMIT_FPCOMPARE(code);
4040 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4041 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
4042 unordered_check = code;
4043 x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4045 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4046 x86_set_reg (code, X86_CC_GE, ins->dreg, TRUE);
4047 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4049 x86_jump8 (code, 0);
4050 x86_patch (unordered_check, code);
4051 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4052 x86_patch (jump_to_end, code);
4054 if (ins->dreg != X86_EAX)
4055 x86_pop_reg (code, X86_EAX);
4059 if (cfg->opt & MONO_OPT_FCMOV) {
4060 guchar *jump = code;
4061 x86_branch8 (code, X86_CC_P, 0, TRUE);
4062 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4063 x86_patch (jump, code);
4066 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4067 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4070 /* Branch if C013 != 100 */
4071 if (cfg->opt & MONO_OPT_FCMOV) {
4072 /* branch if !ZF or (PF|CF) */
4073 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4074 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4075 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4078 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4079 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4082 if (cfg->opt & MONO_OPT_FCMOV) {
4083 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4086 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4089 if (cfg->opt & MONO_OPT_FCMOV) {
4090 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4091 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4094 if (ins->opcode == OP_FBLT_UN) {
4095 guchar *is_not_zero_check, *end_jump;
4096 is_not_zero_check = code;
4097 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4099 x86_jump8 (code, 0);
4100 x86_patch (is_not_zero_check, code);
4101 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4103 x86_patch (end_jump, code);
4105 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4109 if (cfg->opt & MONO_OPT_FCMOV) {
4110 if (ins->opcode == OP_FBGT) {
4113 /* skip branch if C1=1 */
4115 x86_branch8 (code, X86_CC_P, 0, FALSE);
4116 /* branch if (C0 | C3) = 1 */
4117 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4118 x86_patch (br1, code);
4120 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4124 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4125 if (ins->opcode == OP_FBGT_UN) {
4126 guchar *is_not_zero_check, *end_jump;
4127 is_not_zero_check = code;
4128 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4130 x86_jump8 (code, 0);
4131 x86_patch (is_not_zero_check, code);
4132 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4134 x86_patch (end_jump, code);
4136 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4139 /* Branch if C013 == 100 or 001 */
4140 if (cfg->opt & MONO_OPT_FCMOV) {
4143 /* skip branch if C1=1 */
4145 x86_branch8 (code, X86_CC_P, 0, FALSE);
4146 /* branch if (C0 | C3) = 1 */
4147 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4148 x86_patch (br1, code);
4151 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4152 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4153 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4154 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4157 /* Branch if C013 == 000 */
4158 if (cfg->opt & MONO_OPT_FCMOV) {
4159 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4162 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4165 /* Branch if C013=000 or 100 */
4166 if (cfg->opt & MONO_OPT_FCMOV) {
4169 /* skip branch if C1=1 */
4171 x86_branch8 (code, X86_CC_P, 0, FALSE);
4172 /* branch if C0=0 */
4173 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4174 x86_patch (br1, code);
4177 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4178 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4179 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4182 /* Branch if C013 != 001 */
4183 if (cfg->opt & MONO_OPT_FCMOV) {
4184 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4185 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4188 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4189 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4193 x86_push_reg (code, X86_EAX);
4196 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4197 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4198 x86_pop_reg (code, X86_EAX);
4200 /* Have to clean up the fp stack before throwing the exception */
4202 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4205 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4207 x86_patch (br1, code);
4211 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4214 case OP_TLS_GET_REG: {
4215 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
4219 code = mono_x86_emit_tls_set (code, ins->sreg1, ins->inst_offset);
4222 case OP_TLS_SET_REG: {
4223 code = emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
4226 case OP_MEMORY_BARRIER: {
4227 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ) {
4228 x86_prefix (code, X86_LOCK_PREFIX);
4229 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4233 case OP_ATOMIC_ADD_I4: {
4234 int dreg = ins->dreg;
4236 g_assert (cfg->has_atomic_add_i4);
4238 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4239 if (ins->sreg2 == dreg) {
4240 if (dreg == X86_EBX) {
4242 if (ins->inst_basereg == X86_EDI)
4246 if (ins->inst_basereg == X86_EBX)
4249 } else if (ins->inst_basereg == dreg) {
4250 if (dreg == X86_EBX) {
4252 if (ins->sreg2 == X86_EDI)
4256 if (ins->sreg2 == X86_EBX)
4261 if (dreg != ins->dreg) {
4262 x86_push_reg (code, dreg);
4265 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4266 x86_prefix (code, X86_LOCK_PREFIX);
4267 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4268 /* dreg contains the old value, add with sreg2 value */
4269 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4271 if (ins->dreg != dreg) {
4272 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4273 x86_pop_reg (code, dreg);
4278 case OP_ATOMIC_EXCHANGE_I4: {
4279 /* LOCK prefix is implied. */
4280 x86_xchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2, 4);
4281 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4284 case OP_ATOMIC_CAS_I4: {
4285 g_assert (ins->dreg == X86_EAX);
4286 g_assert (ins->sreg3 == X86_EAX);
4287 g_assert (ins->sreg1 != X86_EAX);
4288 g_assert (ins->sreg1 != ins->sreg2);
4290 x86_prefix (code, X86_LOCK_PREFIX);
4291 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4294 case OP_ATOMIC_LOAD_I1: {
4295 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4298 case OP_ATOMIC_LOAD_U1: {
4299 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
4302 case OP_ATOMIC_LOAD_I2: {
4303 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4306 case OP_ATOMIC_LOAD_U2: {
4307 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
4310 case OP_ATOMIC_LOAD_I4:
4311 case OP_ATOMIC_LOAD_U4: {
4312 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4315 case OP_ATOMIC_LOAD_R4:
4316 case OP_ATOMIC_LOAD_R8: {
4317 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_R8);
4320 case OP_ATOMIC_STORE_I1:
4321 case OP_ATOMIC_STORE_U1:
4322 case OP_ATOMIC_STORE_I2:
4323 case OP_ATOMIC_STORE_U2:
4324 case OP_ATOMIC_STORE_I4:
4325 case OP_ATOMIC_STORE_U4: {
4328 switch (ins->opcode) {
4329 case OP_ATOMIC_STORE_I1:
4330 case OP_ATOMIC_STORE_U1:
4333 case OP_ATOMIC_STORE_I2:
4334 case OP_ATOMIC_STORE_U2:
4337 case OP_ATOMIC_STORE_I4:
4338 case OP_ATOMIC_STORE_U4:
4343 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
4345 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4349 case OP_ATOMIC_STORE_R4:
4350 case OP_ATOMIC_STORE_R8: {
4351 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, ins->opcode == OP_ATOMIC_STORE_R8, TRUE);
4353 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
4357 case OP_CARD_TABLE_WBARRIER: {
4358 int ptr = ins->sreg1;
4359 int value = ins->sreg2;
4361 int nursery_shift, card_table_shift;
4362 gpointer card_table_mask;
4363 size_t nursery_size;
4364 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4365 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4366 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4369 * We need one register we can clobber, we choose EDX and make sreg1
4370 * fixed EAX to work around limitations in the local register allocator.
4371 * sreg2 might get allocated to EDX, but that is not a problem since
4372 * we use it before clobbering EDX.
4374 g_assert (ins->sreg1 == X86_EAX);
4377 * This is the code we produce:
4380 * edx >>= nursery_shift
4381 * cmp edx, (nursery_start >> nursery_shift)
4384 * edx >>= card_table_shift
4385 * card_table[edx] = 1
4389 if (card_table_nursery_check) {
4390 if (value != X86_EDX)
4391 x86_mov_reg_reg (code, X86_EDX, value, 4);
4392 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4393 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4394 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4396 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4397 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4398 if (card_table_mask)
4399 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4400 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4401 if (card_table_nursery_check)
4402 x86_patch (br, code);
4405 #ifdef MONO_ARCH_SIMD_INTRINSICS
4407 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4413 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4416 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4419 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4425 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4426 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4429 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4432 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4435 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4438 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4441 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4444 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4447 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4450 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4453 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4456 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4462 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4465 case OP_PSHUFLEW_HIGH:
4466 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4467 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4469 case OP_PSHUFLEW_LOW:
4470 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4471 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4474 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4475 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4478 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4479 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4482 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4483 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4487 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4502 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4505 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4506 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4509 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4512 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4515 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4518 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4521 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4524 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4527 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4530 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4536 case OP_EXTRACT_MASK:
4537 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4541 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4544 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4547 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4551 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4554 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4557 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4560 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4564 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4567 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4570 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4577 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4580 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4587 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4590 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4593 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4597 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4600 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4604 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4607 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4610 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4614 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4617 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4620 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4624 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4627 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4630 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4633 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4637 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4640 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4643 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4646 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4649 case OP_PSUM_ABS_DIFF:
4650 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4653 case OP_UNPACK_LOWB:
4654 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4656 case OP_UNPACK_LOWW:
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4659 case OP_UNPACK_LOWD:
4660 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4662 case OP_UNPACK_LOWQ:
4663 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4665 case OP_UNPACK_LOWPS:
4666 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4668 case OP_UNPACK_LOWPD:
4669 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4672 case OP_UNPACK_HIGHB:
4673 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4675 case OP_UNPACK_HIGHW:
4676 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4678 case OP_UNPACK_HIGHD:
4679 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4681 case OP_UNPACK_HIGHQ:
4682 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4684 case OP_UNPACK_HIGHPS:
4685 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4687 case OP_UNPACK_HIGHPD:
4688 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4692 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4695 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4698 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4701 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4704 case OP_PADDB_SAT_UN:
4705 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4707 case OP_PSUBB_SAT_UN:
4708 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4710 case OP_PADDW_SAT_UN:
4711 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4713 case OP_PSUBW_SAT_UN:
4714 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4718 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4721 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4724 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4727 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4731 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4734 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4737 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4739 case OP_PMULW_HIGH_UN:
4740 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4743 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4747 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4750 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4754 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4757 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4761 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4764 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4768 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4771 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4775 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4778 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4782 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4785 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4789 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4792 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4796 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4799 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4803 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4806 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4810 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4812 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4813 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4817 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4819 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4820 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4824 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4826 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4827 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4831 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4833 case OP_EXTRACTX_U2:
4834 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4836 case OP_INSERTX_U1_SLOW:
4837 /*sreg1 is the extracted ireg (scratch)
4838 /sreg2 is the to be inserted ireg (scratch)
4839 /dreg is the xreg to receive the value*/
4841 /*clear the bits from the extracted word*/
4842 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4843 /*shift the value to insert if needed*/
4844 if (ins->inst_c0 & 1)
4845 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4846 /*join them together*/
4847 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4848 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4850 case OP_INSERTX_I4_SLOW:
4851 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4852 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4853 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4856 case OP_INSERTX_R4_SLOW:
4857 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4858 /*TODO if inst_c0 == 0 use movss*/
4859 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4860 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4862 case OP_INSERTX_R8_SLOW:
4863 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4864 if (cfg->verbose_level)
4865 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4867 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4869 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4872 case OP_STOREX_MEMBASE_REG:
4873 case OP_STOREX_MEMBASE:
4874 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4876 case OP_LOADX_MEMBASE:
4877 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4879 case OP_LOADX_ALIGNED_MEMBASE:
4880 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4882 case OP_STOREX_ALIGNED_MEMBASE_REG:
4883 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4885 case OP_STOREX_NTA_MEMBASE_REG:
4886 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4888 case OP_PREFETCH_MEMBASE:
4889 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4893 /*FIXME the peephole pass should have killed this*/
4894 if (ins->dreg != ins->sreg1)
4895 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4898 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4900 case OP_ICONV_TO_R8_RAW:
4901 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4902 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4905 case OP_FCONV_TO_R8_X:
4906 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4907 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4910 case OP_XCONV_R8_TO_I4:
4911 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4912 switch (ins->backend.source_opcode) {
4913 case OP_FCONV_TO_I1:
4914 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4916 case OP_FCONV_TO_U1:
4917 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4919 case OP_FCONV_TO_I2:
4920 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4922 case OP_FCONV_TO_U2:
4923 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4929 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4930 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4931 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4932 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4933 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4934 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4937 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4938 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4939 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4942 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4943 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4946 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4947 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4948 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4951 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4952 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4953 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4957 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4960 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4963 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4966 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4969 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4972 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4975 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4978 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4982 case OP_LIVERANGE_START: {
4983 if (cfg->verbose_level > 1)
4984 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4985 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4988 case OP_LIVERANGE_END: {
4989 if (cfg->verbose_level > 1)
4990 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4991 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4994 case OP_NACL_GC_SAFE_POINT: {
4995 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4996 if (cfg->compile_aot)
4997 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5001 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
5002 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
5003 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
5004 x86_patch (br[0], code);
5009 case OP_GC_LIVENESS_DEF:
5010 case OP_GC_LIVENESS_USE:
5011 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
5012 ins->backend.pc_offset = code - cfg->native_code;
5014 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5015 ins->backend.pc_offset = code - cfg->native_code;
5016 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5019 x86_mov_reg_reg (code, ins->dreg, X86_ESP, sizeof (mgreg_t));
5022 x86_mov_reg_reg (code, X86_ESP, ins->sreg1, sizeof (mgreg_t));
5025 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
5026 g_assert_not_reached ();
5029 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
5030 #ifndef __native_client_codegen__
5031 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
5032 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5033 g_assert_not_reached ();
5034 #endif /* __native_client_codegen__ */
5040 cfg->code_len = code - cfg->native_code;
5043 #endif /* DISABLE_JIT */
5046 mono_arch_register_lowlevel_calls (void)
5051 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5053 MonoJumpInfo *patch_info;
5054 gboolean compile_aot = !run_cctors;
5056 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5057 unsigned char *ip = patch_info->ip.i + code;
5058 const unsigned char *target;
5061 switch (patch_info->type) {
5062 case MONO_PATCH_INFO_BB:
5063 case MONO_PATCH_INFO_LABEL:
5066 /* No need to patch these */
5071 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5073 switch (patch_info->type) {
5074 case MONO_PATCH_INFO_IP:
5075 *((gconstpointer *)(ip)) = target;
5077 case MONO_PATCH_INFO_CLASS_INIT: {
5079 /* Might already been changed to a nop */
5080 x86_call_code (code, 0);
5081 x86_patch (ip, target);
5084 case MONO_PATCH_INFO_ABS:
5085 case MONO_PATCH_INFO_METHOD:
5086 case MONO_PATCH_INFO_METHOD_JUMP:
5087 case MONO_PATCH_INFO_INTERNAL_METHOD:
5088 case MONO_PATCH_INFO_BB:
5089 case MONO_PATCH_INFO_LABEL:
5090 case MONO_PATCH_INFO_RGCTX_FETCH:
5091 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5092 case MONO_PATCH_INFO_MONITOR_ENTER:
5093 case MONO_PATCH_INFO_MONITOR_ENTER_V4:
5094 case MONO_PATCH_INFO_MONITOR_EXIT:
5095 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5096 #if defined(__native_client_codegen__) && defined(__native_client__)
5097 if (nacl_is_code_address (code)) {
5098 /* For tail calls, code is patched after being installed */
5099 /* but not through the normal "patch callsite" method. */
5100 unsigned char buf[kNaClAlignment];
5101 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5102 unsigned char *_target = target;
5104 /* All patch targets modified in x86_patch */
5105 /* are IP relative. */
5106 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5107 memcpy (buf, aligned_code, kNaClAlignment);
5108 /* Patch a temp buffer of bundle size, */
5109 /* then install to actual location. */
5110 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5111 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5112 g_assert (ret == 0);
5115 x86_patch (ip, target);
5118 x86_patch (ip, target);
5121 case MONO_PATCH_INFO_NONE:
5123 case MONO_PATCH_INFO_R4:
5124 case MONO_PATCH_INFO_R8: {
5125 guint32 offset = mono_arch_get_patch_offset (ip);
5126 *((gconstpointer *)(ip + offset)) = target;
5130 guint32 offset = mono_arch_get_patch_offset (ip);
5131 #if !defined(__native_client__)
5132 *((gconstpointer *)(ip + offset)) = target;
5134 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5142 static G_GNUC_UNUSED void
5143 stack_unaligned (MonoMethod *m, gpointer caller)
5145 printf ("%s\n", mono_method_full_name (m, TRUE));
5146 g_assert_not_reached ();
5150 mono_arch_emit_prolog (MonoCompile *cfg)
5152 MonoMethod *method = cfg->method;
5154 MonoMethodSignature *sig;
5156 int alloc_size, pos, max_offset, i, cfa_offset;
5158 gboolean need_stack_frame;
5159 #ifdef __native_client_codegen__
5160 guint alignment_check;
5163 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5165 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5166 cfg->code_size += 512;
5168 #if defined(__default_codegen__)
5169 code = cfg->native_code = g_malloc (cfg->code_size);
5170 #elif defined(__native_client_codegen__)
5171 /* native_code_alloc is not 32-byte aligned, native_code is. */
5172 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5173 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5175 /* Align native_code to next nearest kNaclAlignment byte. */
5176 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5177 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5179 code = cfg->native_code;
5181 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5182 g_assert(alignment_check == 0);
5189 /* Check that the stack is aligned on osx */
5190 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5191 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5192 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5194 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5195 x86_push_membase (code, X86_ESP, 0);
5196 x86_push_imm (code, cfg->method);
5197 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5198 x86_call_reg (code, X86_EAX);
5199 x86_patch (br [0], code);
5203 /* Offset between RSP and the CFA */
5207 cfa_offset = sizeof (gpointer);
5208 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5209 // IP saved at CFA - 4
5210 /* There is no IP reg on x86 */
5211 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5212 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5214 need_stack_frame = needs_stack_frame (cfg);
5216 if (need_stack_frame) {
5217 x86_push_reg (code, X86_EBP);
5218 cfa_offset += sizeof (gpointer);
5219 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5220 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5221 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5222 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5223 /* These are handled automatically by the stack marking code */
5224 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5226 cfg->frame_reg = X86_ESP;
5229 cfg->stack_offset += cfg->param_area;
5230 cfg->stack_offset = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5232 alloc_size = cfg->stack_offset;
5235 if (!method->save_lmf) {
5236 if (cfg->used_int_regs & (1 << X86_EBX)) {
5237 x86_push_reg (code, X86_EBX);
5239 cfa_offset += sizeof (gpointer);
5240 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5241 /* These are handled automatically by the stack marking code */
5242 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5245 if (cfg->used_int_regs & (1 << X86_EDI)) {
5246 x86_push_reg (code, X86_EDI);
5248 cfa_offset += sizeof (gpointer);
5249 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5250 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5253 if (cfg->used_int_regs & (1 << X86_ESI)) {
5254 x86_push_reg (code, X86_ESI);
5256 cfa_offset += sizeof (gpointer);
5257 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5258 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5264 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5265 if (mono_do_x86_stack_align && need_stack_frame) {
5266 int tot = alloc_size + pos + 4; /* ret ip */
5267 if (need_stack_frame)
5269 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5271 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5272 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5273 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5277 cfg->arch.sp_fp_offset = alloc_size + pos;
5280 /* See mono_emit_stack_alloc */
5281 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5282 guint32 remaining_size = alloc_size;
5283 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5284 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5285 guint32 offset = code - cfg->native_code;
5286 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5287 while (required_code_size >= (cfg->code_size - offset))
5288 cfg->code_size *= 2;
5289 cfg->native_code = mono_realloc_native_code(cfg);
5290 code = cfg->native_code + offset;
5291 cfg->stat_code_reallocs++;
5293 while (remaining_size >= 0x1000) {
5294 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5295 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5296 remaining_size -= 0x1000;
5299 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5301 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5304 g_assert (need_stack_frame);
5307 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5308 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5309 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5312 #if DEBUG_STACK_ALIGNMENT
5313 /* check the stack is aligned */
5314 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5315 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5316 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5317 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5318 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5319 x86_breakpoint (code);
5323 /* compute max_offset in order to use short forward jumps */
5325 if (cfg->opt & MONO_OPT_BRANCH) {
5326 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5328 bb->max_offset = max_offset;
5330 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5332 /* max alignment for loops */
5333 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5334 max_offset += LOOP_ALIGNMENT;
5335 #ifdef __native_client_codegen__
5336 /* max alignment for native client */
5337 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5338 max_offset += kNaClAlignment;
5340 MONO_BB_FOR_EACH_INS (bb, ins) {
5341 if (ins->opcode == OP_LABEL)
5342 ins->inst_c1 = max_offset;
5343 #ifdef __native_client_codegen__
5344 switch (ins->opcode)
5356 case OP_VOIDCALL_REG:
5358 case OP_FCALL_MEMBASE:
5359 case OP_LCALL_MEMBASE:
5360 case OP_VCALL_MEMBASE:
5361 case OP_VCALL2_MEMBASE:
5362 case OP_VOIDCALL_MEMBASE:
5363 case OP_CALL_MEMBASE:
5364 max_offset += kNaClAlignment;
5367 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5370 #endif /* __native_client_codegen__ */
5371 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5376 /* store runtime generic context */
5377 if (cfg->rgctx_var) {
5378 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5380 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5383 if (method->save_lmf)
5384 code = emit_setup_lmf (cfg, code, cfg->lmf_var->inst_offset, cfa_offset);
5386 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5387 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5389 /* load arguments allocated to register from the stack */
5390 sig = mono_method_signature (method);
5393 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5394 inst = cfg->args [pos];
5395 if (inst->opcode == OP_REGVAR) {
5396 g_assert (need_stack_frame);
5397 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5398 if (cfg->verbose_level > 2)
5399 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5404 cfg->code_len = code - cfg->native_code;
5406 g_assert (cfg->code_len < cfg->code_size);
5412 mono_arch_emit_epilog (MonoCompile *cfg)
5414 MonoMethod *method = cfg->method;
5415 MonoMethodSignature *sig = mono_method_signature (method);
5417 guint32 stack_to_pop;
5419 int max_epilog_size = 16;
5421 gboolean need_stack_frame = needs_stack_frame (cfg);
5423 if (cfg->method->save_lmf)
5424 max_epilog_size += 128;
5426 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5427 cfg->code_size *= 2;
5428 cfg->native_code = mono_realloc_native_code(cfg);
5429 cfg->stat_code_reallocs++;
5432 code = cfg->native_code + cfg->code_len;
5434 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5435 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5437 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
5440 if (method->save_lmf) {
5441 gint32 lmf_offset = cfg->lmf_var->inst_offset;
5443 gboolean supported = FALSE;
5445 if (cfg->compile_aot) {
5446 #if defined(__APPLE__) || defined(__linux__)
5449 } else if (mono_get_jit_tls_offset () != -1) {
5453 /* check if we need to restore protection of the stack after a stack overflow */
5455 if (cfg->compile_aot) {
5456 code = emit_load_aotconst (NULL, code, cfg, NULL, X86_ECX, MONO_PATCH_INFO_TLS_OFFSET, GINT_TO_POINTER (TLS_KEY_JIT_TLS));
5458 code = emit_tls_get_reg (code, X86_ECX, X86_ECX);
5460 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5463 /* we load the value in a separate instruction: this mechanism may be
5464 * used later as a safer way to do thread interruption
5466 x86_mov_reg_membase (code, X86_ECX, X86_ECX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5467 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5469 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5470 /* note that the call trampoline will preserve eax/edx */
5471 x86_call_reg (code, X86_ECX);
5472 x86_patch (patch, code);
5474 /* FIXME: maybe save the jit tls in the prolog */
5477 /* restore caller saved regs */
5478 if (cfg->used_int_regs & (1 << X86_EBX)) {
5479 x86_mov_reg_membase (code, X86_EBX, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, ebx), 4);
5482 if (cfg->used_int_regs & (1 << X86_EDI)) {
5483 x86_mov_reg_membase (code, X86_EDI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, edi), 4);
5485 if (cfg->used_int_regs & (1 << X86_ESI)) {
5486 x86_mov_reg_membase (code, X86_ESI, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, esi), 4);
5489 /* EBP is restored by LEAVE */
5491 for (i = 0; i < X86_NREG; ++i) {
5492 if ((cfg->used_int_regs & X86_CALLER_REGS & (1 << i)) && (i != X86_EBP)) {
5498 g_assert (need_stack_frame);
5499 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5503 g_assert (need_stack_frame);
5504 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5507 if (cfg->used_int_regs & (1 << X86_ESI)) {
5508 x86_pop_reg (code, X86_ESI);
5510 if (cfg->used_int_regs & (1 << X86_EDI)) {
5511 x86_pop_reg (code, X86_EDI);
5513 if (cfg->used_int_regs & (1 << X86_EBX)) {
5514 x86_pop_reg (code, X86_EBX);
5518 /* Load returned vtypes into registers if needed */
5519 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5520 if (cinfo->ret.storage == ArgValuetypeInReg) {
5521 for (quad = 0; quad < 2; quad ++) {
5522 switch (cinfo->ret.pair_storage [quad]) {
5524 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5526 case ArgOnFloatFpStack:
5527 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5529 case ArgOnDoubleFpStack:
5530 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5535 g_assert_not_reached ();
5540 if (need_stack_frame)
5543 if (CALLCONV_IS_STDCALL (sig)) {
5544 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5546 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5547 } else if (cinfo->callee_stack_pop)
5548 stack_to_pop = cinfo->callee_stack_pop;
5553 g_assert (need_stack_frame);
5554 x86_ret_imm (code, stack_to_pop);
5559 cfg->code_len = code - cfg->native_code;
5561 g_assert (cfg->code_len < cfg->code_size);
5565 mono_arch_emit_exceptions (MonoCompile *cfg)
5567 MonoJumpInfo *patch_info;
5570 MonoClass *exc_classes [16];
5571 guint8 *exc_throw_start [16], *exc_throw_end [16];
5575 /* Compute needed space */
5576 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5577 if (patch_info->type == MONO_PATCH_INFO_EXC)
5582 * make sure we have enough space for exceptions
5583 * 16 is the size of two push_imm instructions and a call
5585 if (cfg->compile_aot)
5586 code_size = exc_count * 32;
5588 code_size = exc_count * 16;
5590 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5591 cfg->code_size *= 2;
5592 cfg->native_code = mono_realloc_native_code(cfg);
5593 cfg->stat_code_reallocs++;
5596 code = cfg->native_code + cfg->code_len;
5599 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5600 switch (patch_info->type) {
5601 case MONO_PATCH_INFO_EXC: {
5602 MonoClass *exc_class;
5606 x86_patch (patch_info->ip.i + cfg->native_code, code);
5608 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5609 g_assert (exc_class);
5610 throw_ip = patch_info->ip.i;
5612 /* Find a throw sequence for the same exception class */
5613 for (i = 0; i < nthrows; ++i)
5614 if (exc_classes [i] == exc_class)
5617 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5618 x86_jump_code (code, exc_throw_start [i]);
5619 patch_info->type = MONO_PATCH_INFO_NONE;
5624 /* Compute size of code following the push <OFFSET> */
5625 #if defined(__default_codegen__)
5627 #elif defined(__native_client_codegen__)
5628 code = mono_nacl_align (code);
5629 size = kNaClAlignment;
5631 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5633 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5634 /* Use the shorter form */
5636 x86_push_imm (code, 0);
5640 x86_push_imm (code, 0xf0f0f0f0);
5645 exc_classes [nthrows] = exc_class;
5646 exc_throw_start [nthrows] = code;
5649 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5650 patch_info->data.name = "mono_arch_throw_corlib_exception";
5651 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5652 patch_info->ip.i = code - cfg->native_code;
5653 x86_call_code (code, 0);
5654 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5659 exc_throw_end [nthrows] = code;
5671 cfg->code_len = code - cfg->native_code;
5673 g_assert (cfg->code_len < cfg->code_size);
5677 mono_arch_flush_icache (guint8 *code, gint size)
5683 mono_arch_flush_register_windows (void)
5688 mono_arch_is_inst_imm (gint64 imm)
5694 mono_arch_finish_init (void)
5696 if (!g_getenv ("MONO_NO_TLS")) {
5697 #ifndef TARGET_WIN32
5699 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5706 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5710 // Linear handler, the bsearch head compare is shorter
5711 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5712 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5713 // x86_patch(ins,target)
5714 //[1 + 5] x86_jump_mem(inst,mem)
5717 #if defined(__default_codegen__)
5718 #define BR_SMALL_SIZE 2
5719 #define BR_LARGE_SIZE 5
5720 #elif defined(__native_client_codegen__)
5721 /* I suspect the size calculation below is actually incorrect. */
5722 /* TODO: fix the calculation that uses these sizes. */
5723 #define BR_SMALL_SIZE 16
5724 #define BR_LARGE_SIZE 12
5725 #endif /*__native_client_codegen__*/
5726 #define JUMP_IMM_SIZE 6
5727 #define ENABLE_WRONG_METHOD_CHECK 0
5731 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5733 int i, distance = 0;
5734 for (i = start; i < target; ++i)
5735 distance += imt_entries [i]->chunk_size;
5740 * LOCKING: called with the domain lock held
5743 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5744 gpointer fail_tramp)
5748 guint8 *code, *start;
5750 for (i = 0; i < count; ++i) {
5751 MonoIMTCheckItem *item = imt_entries [i];
5752 if (item->is_equals) {
5753 if (item->check_target_idx) {
5754 if (!item->compare_done)
5755 item->chunk_size += CMP_SIZE;
5756 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5759 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5761 item->chunk_size += JUMP_IMM_SIZE;
5762 #if ENABLE_WRONG_METHOD_CHECK
5763 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5768 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5769 imt_entries [item->check_target_idx]->compare_done = TRUE;
5771 size += item->chunk_size;
5773 #if defined(__native_client__) && defined(__native_client_codegen__)
5774 /* In Native Client, we don't re-use thunks, allocate from the */
5775 /* normal code manager paths. */
5776 size = NACL_BUNDLE_ALIGN_UP (size);
5777 code = mono_domain_code_reserve (domain, size);
5780 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5782 code = mono_domain_code_reserve (domain, size);
5785 for (i = 0; i < count; ++i) {
5786 MonoIMTCheckItem *item = imt_entries [i];
5787 item->code_target = code;
5788 if (item->is_equals) {
5789 if (item->check_target_idx) {
5790 if (!item->compare_done)
5791 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5792 item->jmp_code = code;
5793 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5794 if (item->has_target_code)
5795 x86_jump_code (code, item->value.target_code);
5797 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5800 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5801 item->jmp_code = code;
5802 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5803 if (item->has_target_code)
5804 x86_jump_code (code, item->value.target_code);
5806 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5807 x86_patch (item->jmp_code, code);
5808 x86_jump_code (code, fail_tramp);
5809 item->jmp_code = NULL;
5811 /* enable the commented code to assert on wrong method */
5812 #if ENABLE_WRONG_METHOD_CHECK
5813 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5814 item->jmp_code = code;
5815 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5817 if (item->has_target_code)
5818 x86_jump_code (code, item->value.target_code);
5820 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5821 #if ENABLE_WRONG_METHOD_CHECK
5822 x86_patch (item->jmp_code, code);
5823 x86_breakpoint (code);
5824 item->jmp_code = NULL;
5829 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5830 item->jmp_code = code;
5831 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5832 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5834 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5837 /* patch the branches to get to the target items */
5838 for (i = 0; i < count; ++i) {
5839 MonoIMTCheckItem *item = imt_entries [i];
5840 if (item->jmp_code) {
5841 if (item->check_target_idx) {
5842 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5848 mono_stats.imt_thunks_size += code - start;
5849 g_assert (code - start <= size);
5853 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5854 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5858 if (mono_jit_map_is_enabled ()) {
5861 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5863 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5864 mono_emit_jit_tramp (start, code - start, buff);
5868 nacl_domain_code_validate (domain, &start, size, &code);
5869 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
5875 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5877 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5881 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5883 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5887 mono_arch_get_cie_program (void)
5891 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5892 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5898 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5900 MonoInst *ins = NULL;
5903 if (cmethod->klass == mono_defaults.math_class) {
5904 if (strcmp (cmethod->name, "Sin") == 0) {
5906 } else if (strcmp (cmethod->name, "Cos") == 0) {
5908 } else if (strcmp (cmethod->name, "Tan") == 0) {
5910 } else if (strcmp (cmethod->name, "Atan") == 0) {
5912 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5914 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5916 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5920 if (opcode && fsig->param_count == 1) {
5921 MONO_INST_NEW (cfg, ins, opcode);
5922 ins->type = STACK_R8;
5923 ins->dreg = mono_alloc_freg (cfg);
5924 ins->sreg1 = args [0]->dreg;
5925 MONO_ADD_INS (cfg->cbb, ins);
5928 if (cfg->opt & MONO_OPT_CMOV) {
5931 if (strcmp (cmethod->name, "Min") == 0) {
5932 if (fsig->params [0]->type == MONO_TYPE_I4)
5934 } else if (strcmp (cmethod->name, "Max") == 0) {
5935 if (fsig->params [0]->type == MONO_TYPE_I4)
5939 if (opcode && fsig->param_count == 2) {
5940 MONO_INST_NEW (cfg, ins, opcode);
5941 ins->type = STACK_I4;
5942 ins->dreg = mono_alloc_ireg (cfg);
5943 ins->sreg1 = args [0]->dreg;
5944 ins->sreg2 = args [1]->dreg;
5945 MONO_ADD_INS (cfg->cbb, ins);
5950 /* OP_FREM is not IEEE compatible */
5951 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
5952 MONO_INST_NEW (cfg, ins, OP_FREM);
5953 ins->inst_i0 = args [0];
5954 ins->inst_i1 = args [1];
5963 mono_arch_print_tree (MonoInst *tree, int arity)
5969 mono_arch_get_patch_offset (guint8 *code)
5971 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
5973 else if (code [0] == 0xba)
5975 else if (code [0] == 0x68)
5978 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
5979 /* push <OFFSET>(<REG>) */
5981 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
5982 /* call *<OFFSET>(<REG>) */
5984 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
5987 else if ((code [0] == 0x58) && (code [1] == 0x05))
5988 /* pop %eax; add <OFFSET>, %eax */
5990 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
5991 /* pop <REG>; add <OFFSET>, <REG> */
5993 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
5994 /* mov <REG>, imm */
5997 g_assert_not_reached ();
6003 * mono_breakpoint_clean_code:
6005 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6006 * breakpoints in the original code, they are removed in the copy.
6008 * Returns TRUE if no sw breakpoint was present.
6011 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6014 gboolean can_write = TRUE;
6016 * If method_start is non-NULL we need to perform bound checks, since we access memory
6017 * at code - offset we could go before the start of the method and end up in a different
6018 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6021 if (!method_start || code - offset >= method_start) {
6022 memcpy (buf, code - offset, size);
6024 int diff = code - method_start;
6025 memset (buf, 0, size);
6026 memcpy (buf + offset - diff, method_start, diff + size - offset);
6029 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6030 int idx = mono_breakpoint_info_index [i];
6034 ptr = mono_breakpoint_info [idx].address;
6035 if (ptr >= code && ptr < code + size) {
6036 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6038 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6039 buf [ptr - code] = saved_byte;
6046 * mono_x86_get_this_arg_offset:
6048 * Return the offset of the stack location where this is passed during a virtual
6052 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6058 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6060 guint32 esp = regs [X86_ESP];
6067 * The stack looks like:
6071 res = ((MonoObject**)esp) [0];
6075 #define MAX_ARCH_DELEGATE_PARAMS 10
6078 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6080 guint8 *code, *start;
6081 int code_reserve = 64;
6084 * The stack contains:
6090 start = code = mono_global_codeman_reserve (code_reserve);
6092 /* Replace the this argument with the target */
6093 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6094 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6095 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6096 x86_jump_membase (code, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6098 g_assert ((code - start) < code_reserve);
6101 /* 8 for mov_reg and jump, plus 8 for each parameter */
6102 #ifdef __native_client_codegen__
6103 /* TODO: calculate this size correctly */
6104 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6106 code_reserve = 8 + (param_count * 8);
6107 #endif /* __native_client_codegen__ */
6109 * The stack contains:
6110 * <args in reverse order>
6115 * <args in reverse order>
6118 * without unbalancing the stack.
6119 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6120 * and leaving original spot of first arg as placeholder in stack so
6121 * when callee pops stack everything works.
6124 start = code = mono_global_codeman_reserve (code_reserve);
6126 /* store delegate for access to method_ptr */
6127 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6130 for (i = 0; i < param_count; ++i) {
6131 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6132 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6135 x86_jump_membase (code, X86_ECX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
6137 g_assert ((code - start) < code_reserve);
6140 nacl_global_codeman_validate (&start, code_reserve, &code);
6143 *code_len = code - start;
6145 if (mono_jit_map_is_enabled ()) {
6148 buff = (char*)"delegate_invoke_has_target";
6150 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6151 mono_emit_jit_tramp (start, code - start, buff);
6155 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6161 mono_arch_get_delegate_invoke_impls (void)
6169 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6170 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
6172 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6173 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6174 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
6175 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
6176 g_free (tramp_name);
6183 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6185 guint8 *code, *start;
6187 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6190 /* FIXME: Support more cases */
6191 if (MONO_TYPE_ISSTRUCT (sig->ret))
6195 * The stack contains:
6201 static guint8* cached = NULL;
6206 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6208 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6210 mono_memory_barrier ();
6214 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6217 for (i = 0; i < sig->param_count; ++i)
6218 if (!mono_is_regsize_var (sig->params [i]))
6221 code = cache [sig->param_count];
6225 if (mono_aot_only) {
6226 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6227 start = mono_aot_get_trampoline (name);
6230 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6233 mono_memory_barrier ();
6235 cache [sig->param_count] = start;
6242 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
6244 guint8 *code, *start;
6248 * The stack contains:
6252 start = code = mono_global_codeman_reserve (size);
6254 /* Replace the this argument with the target */
6255 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6256 x86_mov_reg_membase (code, X86_ECX, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 4);
6257 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6260 /* Load the IMT reg */
6261 x86_mov_reg_membase (code, MONO_ARCH_IMT_REG, X86_EAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 4);
6264 /* Load the vtable */
6265 x86_mov_reg_membase (code, X86_EAX, X86_ECX, MONO_STRUCT_OFFSET (MonoObject, vtable), 4);
6266 x86_jump_membase (code, X86_EAX, offset);
6267 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
6273 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6276 case X86_EAX: return ctx->eax;
6277 case X86_EBX: return ctx->ebx;
6278 case X86_ECX: return ctx->ecx;
6279 case X86_EDX: return ctx->edx;
6280 case X86_ESP: return ctx->esp;
6281 case X86_EBP: return ctx->ebp;
6282 case X86_ESI: return ctx->esi;
6283 case X86_EDI: return ctx->edi;
6285 g_assert_not_reached ();
6291 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6319 g_assert_not_reached ();
6323 #ifdef MONO_ARCH_SIMD_INTRINSICS
6326 get_float_to_x_spill_area (MonoCompile *cfg)
6328 if (!cfg->fconv_to_r8_x_var) {
6329 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6330 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6332 return cfg->fconv_to_r8_x_var;
6336 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6339 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6342 int dreg, src_opcode;
6344 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6347 switch (src_opcode = ins->opcode) {
6348 case OP_FCONV_TO_I1:
6349 case OP_FCONV_TO_U1:
6350 case OP_FCONV_TO_I2:
6351 case OP_FCONV_TO_U2:
6352 case OP_FCONV_TO_I4:
6359 /* dreg is the IREG and sreg1 is the FREG */
6360 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6361 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6362 fconv->sreg1 = ins->sreg1;
6363 fconv->dreg = mono_alloc_ireg (cfg);
6364 fconv->type = STACK_VTYPE;
6365 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6367 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6371 ins->opcode = OP_XCONV_R8_TO_I4;
6373 ins->klass = mono_defaults.int32_class;
6374 ins->sreg1 = fconv->dreg;
6376 ins->type = STACK_I4;
6377 ins->backend.source_opcode = src_opcode;
6380 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6383 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6388 if (long_ins->opcode == OP_LNEG) {
6390 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6391 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6392 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6397 #ifdef MONO_ARCH_SIMD_INTRINSICS
6399 if (!(cfg->opt & MONO_OPT_SIMD))
6402 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6403 switch (long_ins->opcode) {
6405 vreg = long_ins->sreg1;
6407 if (long_ins->inst_c0) {
6408 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6409 ins->klass = long_ins->klass;
6410 ins->sreg1 = long_ins->sreg1;
6412 ins->type = STACK_VTYPE;
6413 ins->dreg = vreg = alloc_ireg (cfg);
6414 MONO_ADD_INS (cfg->cbb, ins);
6417 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6418 ins->klass = mono_defaults.int32_class;
6420 ins->type = STACK_I4;
6421 ins->dreg = long_ins->dreg + 1;
6422 MONO_ADD_INS (cfg->cbb, ins);
6424 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6425 ins->klass = long_ins->klass;
6426 ins->sreg1 = long_ins->sreg1;
6427 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6428 ins->type = STACK_VTYPE;
6429 ins->dreg = vreg = alloc_ireg (cfg);
6430 MONO_ADD_INS (cfg->cbb, ins);
6432 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6433 ins->klass = mono_defaults.int32_class;
6435 ins->type = STACK_I4;
6436 ins->dreg = long_ins->dreg + 2;
6437 MONO_ADD_INS (cfg->cbb, ins);
6439 long_ins->opcode = OP_NOP;
6441 case OP_INSERTX_I8_SLOW:
6442 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6443 ins->dreg = long_ins->dreg;
6444 ins->sreg1 = long_ins->dreg;
6445 ins->sreg2 = long_ins->sreg2 + 1;
6446 ins->inst_c0 = long_ins->inst_c0 * 2;
6447 MONO_ADD_INS (cfg->cbb, ins);
6449 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6450 ins->dreg = long_ins->dreg;
6451 ins->sreg1 = long_ins->dreg;
6452 ins->sreg2 = long_ins->sreg2 + 2;
6453 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6454 MONO_ADD_INS (cfg->cbb, ins);
6456 long_ins->opcode = OP_NOP;
6459 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6460 ins->dreg = long_ins->dreg;
6461 ins->sreg1 = long_ins->sreg1 + 1;
6462 ins->klass = long_ins->klass;
6463 ins->type = STACK_VTYPE;
6464 MONO_ADD_INS (cfg->cbb, ins);
6466 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6467 ins->dreg = long_ins->dreg;
6468 ins->sreg1 = long_ins->dreg;
6469 ins->sreg2 = long_ins->sreg1 + 2;
6471 ins->klass = long_ins->klass;
6472 ins->type = STACK_VTYPE;
6473 MONO_ADD_INS (cfg->cbb, ins);
6475 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6476 ins->dreg = long_ins->dreg;
6477 ins->sreg1 = long_ins->dreg;;
6478 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6479 ins->klass = long_ins->klass;
6480 ins->type = STACK_VTYPE;
6481 MONO_ADD_INS (cfg->cbb, ins);
6483 long_ins->opcode = OP_NOP;
6486 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6489 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6491 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6494 gpointer *sp, old_value;
6497 offset = clause->exvar_offset;
6500 bp = MONO_CONTEXT_GET_BP (ctx);
6501 sp = *(gpointer*)(bp + offset);
6504 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6513 * mono_aot_emit_load_got_addr:
6515 * Emit code to load the got address.
6516 * On x86, the result is placed into EBX.
6519 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6521 x86_call_imm (code, 0);
6523 * The patch needs to point to the pop, since the GOT offset needs
6524 * to be added to that address.
6527 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6529 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6530 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6531 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6537 emit_load_aotconst (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji, int dreg, int tramp_type, gconstpointer target)
6540 mono_add_patch_info (cfg, code - cfg->native_code, tramp_type, target);
6542 g_assert_not_reached ();
6543 x86_mov_reg_membase (code, dreg, MONO_ARCH_GOT_REG, 0xf0f0f0f0, 4);
6548 * mono_arch_emit_load_aotconst:
6550 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6551 * TARGET from the mscorlib GOT in full-aot code.
6552 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6556 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6558 /* Load the mscorlib got address */
6559 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6560 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6561 /* arch_emit_got_access () patches this */
6562 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6567 /* Can't put this into mini-x86.h */
6569 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6572 mono_arch_get_trampolines (gboolean aot)
6574 MonoTrampInfo *info;
6575 GSList *tramps = NULL;
6577 mono_x86_get_signal_exception_trampoline (&info, aot);
6579 tramps = g_slist_append (tramps, info);
6586 #define DBG_SIGNAL SIGBUS
6588 #define DBG_SIGNAL SIGSEGV
6591 /* Soft Debug support */
6592 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6595 * mono_arch_set_breakpoint:
6597 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6598 * The location should contain code emitted by OP_SEQ_POINT.
6601 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6606 * In production, we will use int3 (has to fix the size in the md
6607 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6610 g_assert (code [0] == 0x90);
6611 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6615 * mono_arch_clear_breakpoint:
6617 * Clear the breakpoint at IP.
6620 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6625 for (i = 0; i < 6; ++i)
6630 * mono_arch_start_single_stepping:
6632 * Start single stepping.
6635 mono_arch_start_single_stepping (void)
6637 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6641 * mono_arch_stop_single_stepping:
6643 * Stop single stepping.
6646 mono_arch_stop_single_stepping (void)
6648 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6652 * mono_arch_is_single_step_event:
6654 * Return whenever the machine state in SIGCTX corresponds to a single
6658 mono_arch_is_single_step_event (void *info, void *sigctx)
6661 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6663 if (((gpointer)einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6668 siginfo_t* sinfo = (siginfo_t*) info;
6669 /* Sometimes the address is off by 4 */
6670 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6678 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6681 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6682 if (((gpointer)einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6687 siginfo_t* sinfo = (siginfo_t*)info;
6688 /* Sometimes the address is off by 4 */
6689 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6696 #define BREAKPOINT_SIZE 6
6699 * mono_arch_skip_breakpoint:
6701 * See mini-amd64.c for docs.
6704 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6706 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6710 * mono_arch_skip_single_step:
6712 * See mini-amd64.c for docs.
6715 mono_arch_skip_single_step (MonoContext *ctx)
6717 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6721 * mono_arch_get_seq_point_info:
6723 * See mini-amd64.c for docs.
6726 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6733 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
6735 ext->lmf.previous_lmf = (gsize)prev_lmf;
6736 /* Mark that this is a MonoLMFExt */
6737 ext->lmf.previous_lmf = (gsize)(gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
6738 ext->lmf.ebp = (gssize)ext;
6744 mono_arch_opcode_supported (int opcode)
6747 case OP_ATOMIC_ADD_I4:
6748 case OP_ATOMIC_EXCHANGE_I4:
6749 case OP_ATOMIC_CAS_I4:
6750 case OP_ATOMIC_LOAD_I1:
6751 case OP_ATOMIC_LOAD_I2:
6752 case OP_ATOMIC_LOAD_I4:
6753 case OP_ATOMIC_LOAD_U1:
6754 case OP_ATOMIC_LOAD_U2:
6755 case OP_ATOMIC_LOAD_U4:
6756 case OP_ATOMIC_LOAD_R4:
6757 case OP_ATOMIC_LOAD_R8:
6758 case OP_ATOMIC_STORE_I1:
6759 case OP_ATOMIC_STORE_I2:
6760 case OP_ATOMIC_STORE_I4:
6761 case OP_ATOMIC_STORE_U1:
6762 case OP_ATOMIC_STORE_U2:
6763 case OP_ATOMIC_STORE_U4:
6764 case OP_ATOMIC_STORE_R4:
6765 case OP_ATOMIC_STORE_R8:
6772 #if defined(ENABLE_GSHAREDVT)
6774 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6776 #endif /* !MONOTOUCH */