2 * mini-x86.c: x86 backend for the Mono code generator
5 * Paolo Molaro (lupus@ximian.com)
6 * Dietmar Maurer (dietmar@ximian.com)
9 * Copyright 2003 Ximian, Inc.
10 * Copyright 2003-2011 Novell Inc.
11 * Copyright 2011 Xamarin Inc.
20 #include <mono/metadata/appdomain.h>
21 #include <mono/metadata/debug-helpers.h>
22 #include <mono/metadata/threads.h>
23 #include <mono/metadata/profiler-private.h>
24 #include <mono/metadata/mono-debug.h>
25 #include <mono/metadata/gc-internal.h>
26 #include <mono/utils/mono-math.h>
27 #include <mono/utils/mono-counters.h>
28 #include <mono/utils/mono-mmap.h>
29 #include <mono/utils/mono-memory-model.h>
37 /* On windows, these hold the key returned by TlsAlloc () */
38 static gint lmf_tls_offset = -1;
39 static gint lmf_addr_tls_offset = -1;
40 static gint appdomain_tls_offset = -1;
43 static gboolean optimize_for_xen = TRUE;
45 #define optimize_for_xen 0
49 static gboolean is_win32 = TRUE;
51 static gboolean is_win32 = FALSE;
54 /* This mutex protects architecture specific caches */
55 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
56 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
57 static CRITICAL_SECTION mini_arch_mutex;
59 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
64 /* Under windows, the default pinvoke calling convention is stdcall */
65 #define CALLCONV_IS_STDCALL(sig) ((((sig)->call_convention) == MONO_CALL_STDCALL) || ((sig)->pinvoke && ((sig)->call_convention) == MONO_CALL_DEFAULT))
67 #define CALLCONV_IS_STDCALL(sig) (((sig)->call_convention) == MONO_CALL_STDCALL)
70 #define X86_IS_CALLEE_SAVED_REG(reg) (((reg) == X86_EBX) || ((reg) == X86_EDI) || ((reg) == X86_ESI))
73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
76 #ifdef __native_client_codegen__
78 /* Default alignment for Native Client is 32-byte. */
79 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
81 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
82 /* Check that alignment doesn't cross an alignment boundary. */
84 mono_arch_nacl_pad (guint8 *code, int pad)
86 const int kMaxPadding = 7; /* see x86-codegen.h: x86_padding() */
88 if (pad == 0) return code;
89 /* assertion: alignment cannot cross a block boundary */
90 g_assert(((uintptr_t)code & (~kNaClAlignmentMask)) ==
91 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
92 while (pad >= kMaxPadding) {
93 x86_padding (code, kMaxPadding);
96 if (pad != 0) x86_padding (code, pad);
101 mono_arch_nacl_skip_nops (guint8 *code)
103 x86_skip_nops (code);
107 #endif /* __native_client_codegen__ */
110 * The code generated for sequence points reads from this location, which is
111 * made read-only when single stepping is enabled.
113 static gpointer ss_trigger_page;
115 /* Enabled breakpoints read from this trigger page */
116 static gpointer bp_trigger_page;
119 mono_arch_regname (int reg)
122 case X86_EAX: return "%eax";
123 case X86_EBX: return "%ebx";
124 case X86_ECX: return "%ecx";
125 case X86_EDX: return "%edx";
126 case X86_ESP: return "%esp";
127 case X86_EBP: return "%ebp";
128 case X86_EDI: return "%edi";
129 case X86_ESI: return "%esi";
135 mono_arch_fregname (int reg)
160 mono_arch_xregname (int reg)
185 mono_x86_patch (unsigned char* code, gpointer target)
187 x86_patch (code, (unsigned char*)target);
198 /* gsharedvt argument passed by addr */
210 /* Only if storage == ArgValuetypeInReg */
211 ArgStorage pair_storage [2];
220 gboolean need_stack_align;
221 guint32 stack_align_amount;
222 gboolean vtype_retaddr;
223 /* The index of the vret arg in the argument list */
233 #define FLOAT_PARAM_REGS 0
235 static X86_Reg_No param_regs [] = { 0 };
237 #if defined(TARGET_WIN32) || defined(__APPLE__) || defined(__FreeBSD__)
238 #define SMALL_STRUCTS_IN_REGS
239 static X86_Reg_No return_regs [] = { X86_EAX, X86_EDX };
243 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
245 ainfo->offset = *stack_size;
247 if (*gr >= PARAM_REGS) {
248 ainfo->storage = ArgOnStack;
250 (*stack_size) += sizeof (gpointer);
253 ainfo->storage = ArgInIReg;
254 ainfo->reg = param_regs [*gr];
260 add_general_pair (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
262 ainfo->offset = *stack_size;
264 g_assert (PARAM_REGS == 0);
266 ainfo->storage = ArgOnStack;
267 (*stack_size) += sizeof (gpointer) * 2;
272 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
274 ainfo->offset = *stack_size;
276 if (*gr >= FLOAT_PARAM_REGS) {
277 ainfo->storage = ArgOnStack;
278 (*stack_size) += is_double ? 8 : 4;
279 ainfo->nslots = is_double ? 2 : 1;
282 /* A double register */
284 ainfo->storage = ArgInDoubleSSEReg;
286 ainfo->storage = ArgInFloatSSEReg;
294 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
296 guint32 *gr, guint32 *fr, guint32 *stack_size)
301 klass = mono_class_from_mono_type (type);
302 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
304 #ifdef SMALL_STRUCTS_IN_REGS
305 if (sig->pinvoke && is_return) {
306 MonoMarshalType *info;
309 * the exact rules are not very well documented, the code below seems to work with the
310 * code generated by gcc 3.3.3 -mno-cygwin.
312 info = mono_marshal_load_type_info (klass);
315 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
317 /* Special case structs with only a float member */
318 if ((info->native_size == 8) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R8)) {
319 ainfo->storage = ArgValuetypeInReg;
320 ainfo->pair_storage [0] = ArgOnDoubleFpStack;
323 if ((info->native_size == 4) && (info->num_fields == 1) && (info->fields [0].field->type->type == MONO_TYPE_R4)) {
324 ainfo->storage = ArgValuetypeInReg;
325 ainfo->pair_storage [0] = ArgOnFloatFpStack;
328 if ((info->native_size == 1) || (info->native_size == 2) || (info->native_size == 4) || (info->native_size == 8)) {
329 ainfo->storage = ArgValuetypeInReg;
330 ainfo->pair_storage [0] = ArgInIReg;
331 ainfo->pair_regs [0] = return_regs [0];
332 if (info->native_size > 4) {
333 ainfo->pair_storage [1] = ArgInIReg;
334 ainfo->pair_regs [1] = return_regs [1];
341 ainfo->offset = *stack_size;
342 ainfo->storage = ArgOnStack;
343 *stack_size += ALIGN_TO (size, sizeof (gpointer));
344 ainfo->nslots = ALIGN_TO (size, sizeof (gpointer)) / sizeof (gpointer);
350 * Obtain information about a call according to the calling convention.
351 * For x86 ELF, see the "System V Application Binary Interface Intel386
352 * Architecture Processor Supplment, Fourth Edition" document for more
354 * For x86 win32, see ???.
357 get_call_info_internal (MonoGenericSharingContext *gsctx, CallInfo *cinfo, MonoMethodSignature *sig)
359 guint32 i, gr, fr, pstart;
361 int n = sig->hasthis + sig->param_count;
362 guint32 stack_size = 0;
363 gboolean is_pinvoke = sig->pinvoke;
371 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
372 switch (ret_type->type) {
373 case MONO_TYPE_BOOLEAN:
384 case MONO_TYPE_FNPTR:
385 case MONO_TYPE_CLASS:
386 case MONO_TYPE_OBJECT:
387 case MONO_TYPE_SZARRAY:
388 case MONO_TYPE_ARRAY:
389 case MONO_TYPE_STRING:
390 cinfo->ret.storage = ArgInIReg;
391 cinfo->ret.reg = X86_EAX;
395 cinfo->ret.storage = ArgInIReg;
396 cinfo->ret.reg = X86_EAX;
397 cinfo->ret.is_pair = TRUE;
400 cinfo->ret.storage = ArgOnFloatFpStack;
403 cinfo->ret.storage = ArgOnDoubleFpStack;
405 case MONO_TYPE_GENERICINST:
406 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
407 cinfo->ret.storage = ArgInIReg;
408 cinfo->ret.reg = X86_EAX;
411 if (mini_is_gsharedvt_type_gsctx (gsctx, ret_type)) {
412 cinfo->ret.storage = ArgOnStack;
413 cinfo->vtype_retaddr = TRUE;
417 case MONO_TYPE_VALUETYPE:
418 case MONO_TYPE_TYPEDBYREF: {
419 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
421 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
422 if (cinfo->ret.storage == ArgOnStack) {
423 cinfo->vtype_retaddr = TRUE;
424 /* The caller passes the address where the value is stored */
430 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ret_type));
431 cinfo->ret.storage = ArgOnStack;
432 cinfo->vtype_retaddr = TRUE;
435 cinfo->ret.storage = ArgNone;
438 g_error ("Can't handle as return value 0x%x", sig->ret->type);
444 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
445 * the first argument, allowing 'this' to be always passed in the first arg reg.
446 * Also do this if the first argument is a reference type, since virtual calls
447 * are sometimes made using calli without sig->hasthis set, like in the delegate
450 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
452 add_general (&gr, &stack_size, cinfo->args + 0);
454 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
457 cinfo->vret_arg_offset = stack_size;
458 add_general (&gr, &stack_size, &cinfo->ret);
459 cinfo->vret_arg_index = 1;
463 add_general (&gr, &stack_size, cinfo->args + 0);
465 if (cinfo->vtype_retaddr)
466 add_general (&gr, &stack_size, &cinfo->ret);
469 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
471 fr = FLOAT_PARAM_REGS;
473 /* Emit the signature cookie just before the implicit arguments */
474 add_general (&gr, &stack_size, &cinfo->sig_cookie);
477 for (i = pstart; i < sig->param_count; ++i) {
478 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
481 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
482 /* We allways pass the sig cookie on the stack for simplicity */
484 * Prevent implicit arguments + the sig cookie from being passed
488 fr = FLOAT_PARAM_REGS;
490 /* Emit the signature cookie just before the implicit arguments */
491 add_general (&gr, &stack_size, &cinfo->sig_cookie);
494 if (sig->params [i]->byref) {
495 add_general (&gr, &stack_size, ainfo);
498 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
499 switch (ptype->type) {
500 case MONO_TYPE_BOOLEAN:
503 add_general (&gr, &stack_size, ainfo);
508 add_general (&gr, &stack_size, ainfo);
512 add_general (&gr, &stack_size, ainfo);
517 case MONO_TYPE_FNPTR:
518 case MONO_TYPE_CLASS:
519 case MONO_TYPE_OBJECT:
520 case MONO_TYPE_STRING:
521 case MONO_TYPE_SZARRAY:
522 case MONO_TYPE_ARRAY:
523 add_general (&gr, &stack_size, ainfo);
525 case MONO_TYPE_GENERICINST:
526 if (!mono_type_generic_inst_is_valuetype (ptype)) {
527 add_general (&gr, &stack_size, ainfo);
530 if (mini_is_gsharedvt_type_gsctx (gsctx, ptype)) {
531 /* gsharedvt arguments are passed by ref */
532 add_general (&gr, &stack_size, ainfo);
533 g_assert (ainfo->storage == ArgOnStack);
534 ainfo->storage = ArgGSharedVt;
538 case MONO_TYPE_VALUETYPE:
539 case MONO_TYPE_TYPEDBYREF:
540 add_valuetype (gsctx, sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
544 add_general_pair (&gr, &stack_size, ainfo);
547 add_float (&fr, &stack_size, ainfo, FALSE);
550 add_float (&fr, &stack_size, ainfo, TRUE);
554 /* gsharedvt arguments are passed by ref */
555 g_assert (mini_is_gsharedvt_type_gsctx (gsctx, ptype));
556 add_general (&gr, &stack_size, ainfo);
557 g_assert (ainfo->storage == ArgOnStack);
558 ainfo->storage = ArgGSharedVt;
561 g_error ("unexpected type 0x%x", ptype->type);
562 g_assert_not_reached ();
566 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
568 fr = FLOAT_PARAM_REGS;
570 /* Emit the signature cookie just before the implicit arguments */
571 add_general (&gr, &stack_size, &cinfo->sig_cookie);
574 if (mono_do_x86_stack_align && (stack_size % MONO_ARCH_FRAME_ALIGNMENT) != 0) {
575 cinfo->need_stack_align = TRUE;
576 cinfo->stack_align_amount = MONO_ARCH_FRAME_ALIGNMENT - (stack_size % MONO_ARCH_FRAME_ALIGNMENT);
577 stack_size += cinfo->stack_align_amount;
580 cinfo->stack_usage = stack_size;
581 cinfo->reg_usage = gr;
582 cinfo->freg_usage = fr;
587 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
589 int n = sig->hasthis + sig->param_count;
593 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
595 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
597 return get_call_info_internal (gsctx, cinfo, sig);
601 * mono_arch_get_argument_info:
602 * @csig: a method signature
603 * @param_count: the number of parameters to consider
604 * @arg_info: an array to store the result infos
606 * Gathers information on parameters such as size, alignment and
607 * padding. arg_info should be large enought to hold param_count + 1 entries.
609 * Returns the size of the argument area on the stack.
610 * This should be signal safe, since it is called from
611 * mono_arch_find_jit_info ().
612 * FIXME: The metadata calls might not be signal safe.
615 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
617 int len, k, args_size = 0;
623 /* Avoid g_malloc as it is not signal safe */
624 len = sizeof (CallInfo) + (sizeof (ArgInfo) * (csig->param_count + 1));
625 cinfo = (CallInfo*)g_newa (guint8*, len);
626 memset (cinfo, 0, len);
628 cinfo = get_call_info_internal (gsctx, cinfo, csig);
630 arg_info [0].offset = offset;
632 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
633 args_size += sizeof (gpointer);
638 args_size += sizeof (gpointer);
642 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && csig->hasthis) {
643 /* Emitted after this */
644 args_size += sizeof (gpointer);
648 arg_info [0].size = args_size;
650 for (k = 0; k < param_count; k++) {
651 size = mini_type_stack_size_full (NULL, csig->params [k], &align, csig->pinvoke);
653 /* ignore alignment for now */
656 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
657 arg_info [k].pad = pad;
659 arg_info [k + 1].pad = 0;
660 arg_info [k + 1].size = size;
662 arg_info [k + 1].offset = offset;
665 if (k == 0 && cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && !csig->hasthis) {
666 /* Emitted after the first arg */
667 args_size += sizeof (gpointer);
672 if (mono_do_x86_stack_align && !CALLCONV_IS_STDCALL (csig))
673 align = MONO_ARCH_FRAME_ALIGNMENT;
676 args_size += pad = (align - (args_size & (align - 1))) & (align - 1);
677 arg_info [k].pad = pad;
683 mono_x86_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
688 c1 = get_call_info (NULL, NULL, caller_sig);
689 c2 = get_call_info (NULL, NULL, callee_sig);
690 res = c1->stack_usage >= c2->stack_usage;
691 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
692 /* An address on the callee's stack is passed as the first argument */
701 #if !defined(__native_client__)
702 static const guchar cpuid_impl [] = {
703 0x55, /* push %ebp */
704 0x89, 0xe5, /* mov %esp,%ebp */
705 0x53, /* push %ebx */
706 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
707 0x0f, 0xa2, /* cpuid */
708 0x50, /* push %eax */
709 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
710 0x89, 0x18, /* mov %ebx,(%eax) */
711 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
712 0x89, 0x08, /* mov %ecx,(%eax) */
713 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
714 0x89, 0x10, /* mov %edx,(%eax) */
716 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
717 0x89, 0x02, /* mov %eax,(%edx) */
723 static const guchar cpuid_impl [] = {
724 0x55, /* push %ebp */
725 0x89, 0xe5, /* mov %esp,%ebp */
726 0x53, /* push %ebx */
727 0x8b, 0x45, 0x08, /* mov 0x8(%ebp),%eax */
728 0x0f, 0xa2, /* cpuid */
729 0x50, /* push %eax */
730 0x8b, 0x45, 0x10, /* mov 0x10(%ebp),%eax */
731 0x89, 0x18, /* mov %ebx,(%eax) */
732 0x8b, 0x45, 0x14, /* mov 0x14(%ebp),%eax */
733 0x89, 0x08, /* mov %ecx,(%eax) */
734 0x8b, 0x45, 0x18, /* mov 0x18(%ebp),%eax */
735 0x89, 0x10, /* mov %edx,(%eax) */
737 0x8b, 0x55, 0x0c, /* mov 0xc(%ebp),%edx */
738 0x89, 0x02, /* mov %eax,(%edx) */
741 0x59, 0x83, 0xe1, 0xe0, 0xff, 0xe1, /* naclret */
742 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, /* padding, to provide bundle aligned version */
743 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, 0xf4,
744 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, 0xf4,
745 0xf4, 0xf4, 0xf4, 0xf4, 0xf4, 0xf4,
750 typedef void (*CpuidFunc) (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx);
753 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
755 #if defined(__native_client__)
756 static CpuidFunc func = NULL;
759 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
760 memcpy(ptr, cpuid_impl, sizeof(cpuid_impl));
761 end_ptr = ptr + sizeof(cpuid_impl);
762 nacl_global_codeman_validate (&ptr, sizeof(cpuid_impl), &end_ptr);
763 func = (CpuidFunc)ptr;
765 func (id, p_eax, p_ebx, p_ecx, p_edx);
769 __asm__ __volatile__ (
772 "movl %%eax, %%edx\n"
773 "xorl $0x200000, %%eax\n"
778 "xorl %%edx, %%eax\n"
779 "andl $0x200000, %%eax\n"
801 /* Have to use the code manager to get around WinXP DEP */
802 static CpuidFunc func = NULL;
805 ptr = mono_global_codeman_reserve (sizeof (cpuid_impl));
806 memcpy (ptr, cpuid_impl, sizeof (cpuid_impl));
807 func = (CpuidFunc)ptr;
809 func (id, p_eax, p_ebx, p_ecx, p_edx);
812 * We use this approach because of issues with gcc and pic code, see:
813 * http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=7329
814 __asm__ __volatile__ ("cpuid"
815 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
825 * Initialize the cpu to execute managed code.
828 mono_arch_cpu_init (void)
830 /* spec compliance requires running with double precision */
834 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
835 fpcw &= ~X86_FPCW_PRECC_MASK;
836 fpcw |= X86_FPCW_PREC_DOUBLE;
837 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
838 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
840 _control87 (_PC_53, MCW_PC);
845 * Initialize architecture specific code.
848 mono_arch_init (void)
850 InitializeCriticalSection (&mini_arch_mutex);
852 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ);
853 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
854 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
856 mono_aot_register_jit_icall ("mono_x86_throw_exception", mono_x86_throw_exception);
857 mono_aot_register_jit_icall ("mono_x86_throw_corlib_exception", mono_x86_throw_corlib_exception);
858 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
859 mono_aot_register_jit_icall ("mono_x86_start_gsharedvt_call", mono_x86_start_gsharedvt_call);
864 * Cleanup architecture specific code.
867 mono_arch_cleanup (void)
870 mono_vfree (ss_trigger_page, mono_pagesize ());
872 mono_vfree (bp_trigger_page, mono_pagesize ());
873 DeleteCriticalSection (&mini_arch_mutex);
877 * This function returns the optimizations supported on this cpu.
880 mono_arch_cpu_optimizations (guint32 *exclude_mask)
882 #if !defined(__native_client__)
883 int eax, ebx, ecx, edx;
889 /* The cpuid function allocates from the global codeman */
892 /* Feature Flags function, flags returned in EDX. */
893 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
894 if (edx & (1 << 15)) {
895 opts |= MONO_OPT_CMOV;
897 opts |= MONO_OPT_FCMOV;
899 *exclude_mask |= MONO_OPT_FCMOV;
901 *exclude_mask |= MONO_OPT_CMOV;
903 opts |= MONO_OPT_SSE2;
905 *exclude_mask |= MONO_OPT_SSE2;
907 #ifdef MONO_ARCH_SIMD_INTRINSICS
908 /*SIMD intrinsics require at least SSE2.*/
909 if (!(opts & MONO_OPT_SSE2))
910 *exclude_mask |= MONO_OPT_SIMD;
915 return MONO_OPT_CMOV | MONO_OPT_FCMOV | MONO_OPT_SSE2;
920 * This function test for all SSE functions supported.
922 * Returns a bitmask corresponding to all supported versions.
926 mono_arch_cpu_enumerate_simd_versions (void)
928 int eax, ebx, ecx, edx;
929 guint32 sse_opts = 0;
932 /* The cpuid function allocates from the global codeman */
935 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
937 sse_opts |= SIMD_VERSION_SSE1;
939 sse_opts |= SIMD_VERSION_SSE2;
941 sse_opts |= SIMD_VERSION_SSE3;
943 sse_opts |= SIMD_VERSION_SSSE3;
945 sse_opts |= SIMD_VERSION_SSE41;
947 sse_opts |= SIMD_VERSION_SSE42;
950 /* Yes, all this needs to be done to check for sse4a.
951 See: "Amd: CPUID Specification"
953 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
954 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
955 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
956 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
958 sse_opts |= SIMD_VERSION_SSE4a;
967 * Determine whenever the trap whose info is in SIGINFO is caused by
971 mono_arch_is_int_overflow (void *sigctx, void *info)
976 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
978 ip = (guint8*)ctx.eip;
980 if ((ip [0] == 0xf7) && (x86_modrm_mod (ip [1]) == 0x3) && (x86_modrm_reg (ip [1]) == 0x7)) {
984 switch (x86_modrm_rm (ip [1])) {
1004 g_assert_not_reached ();
1016 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1021 for (i = 0; i < cfg->num_varinfo; i++) {
1022 MonoInst *ins = cfg->varinfo [i];
1023 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1026 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1029 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1030 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1033 /* we dont allocate I1 to registers because there is no simply way to sign extend
1034 * 8bit quantities in caller saved registers on x86 */
1035 if (mono_is_regsize_var (ins->inst_vtype) && (ins->inst_vtype->type != MONO_TYPE_I1)) {
1036 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1037 g_assert (i == vmv->idx);
1038 vars = g_list_prepend (vars, vmv);
1042 vars = mono_varlist_sort (cfg, vars, 0);
1048 mono_arch_get_global_int_regs (MonoCompile *cfg)
1052 /* we can use 3 registers for global allocation */
1053 regs = g_list_prepend (regs, (gpointer)X86_EBX);
1054 regs = g_list_prepend (regs, (gpointer)X86_ESI);
1055 regs = g_list_prepend (regs, (gpointer)X86_EDI);
1061 * mono_arch_regalloc_cost:
1063 * Return the cost, in number of memory references, of the action of
1064 * allocating the variable VMV into a register during global register
1068 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1070 MonoInst *ins = cfg->varinfo [vmv->idx];
1072 if (cfg->method->save_lmf)
1073 /* The register is already saved */
1074 return (ins->opcode == OP_ARG) ? 1 : 0;
1076 /* push+pop+possible load if it is an argument */
1077 return (ins->opcode == OP_ARG) ? 3 : 2;
1081 set_needs_stack_frame (MonoCompile *cfg, gboolean flag)
1083 static int inited = FALSE;
1084 static int count = 0;
1086 if (cfg->arch.need_stack_frame_inited) {
1087 g_assert (cfg->arch.need_stack_frame == flag);
1091 cfg->arch.need_stack_frame = flag;
1092 cfg->arch.need_stack_frame_inited = TRUE;
1098 mono_counters_register ("Could eliminate stack frame", MONO_COUNTER_INT|MONO_COUNTER_JIT, &count);
1103 //g_print ("will eliminate %s.%s.%s\n", cfg->method->klass->name_space, cfg->method->klass->name, cfg->method->name);
1107 needs_stack_frame (MonoCompile *cfg)
1109 MonoMethodSignature *sig;
1110 MonoMethodHeader *header;
1111 gboolean result = FALSE;
1113 #if defined(__APPLE__)
1114 /*OSX requires stack frame code to have the correct alignment. */
1118 if (cfg->arch.need_stack_frame_inited)
1119 return cfg->arch.need_stack_frame;
1121 header = cfg->header;
1122 sig = mono_method_signature (cfg->method);
1124 if (cfg->disable_omit_fp)
1126 else if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1128 else if (cfg->method->save_lmf)
1130 else if (cfg->stack_offset)
1132 else if (cfg->param_area)
1134 else if (cfg->flags & (MONO_CFG_HAS_CALLS | MONO_CFG_HAS_ALLOCA | MONO_CFG_HAS_TAIL))
1136 else if (header->num_clauses)
1138 else if (sig->param_count + sig->hasthis)
1140 else if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1142 else if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1143 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1146 set_needs_stack_frame (cfg, result);
1148 return cfg->arch.need_stack_frame;
1152 * Set var information according to the calling convention. X86 version.
1153 * The locals var stuff should most likely be split in another method.
1156 mono_arch_allocate_vars (MonoCompile *cfg)
1158 MonoMethodSignature *sig;
1159 MonoMethodHeader *header;
1161 guint32 locals_stack_size, locals_stack_align;
1166 header = cfg->header;
1167 sig = mono_method_signature (cfg->method);
1169 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1171 cfg->frame_reg = X86_EBP;
1174 /* Reserve space to save LMF and caller saved registers */
1176 if (cfg->method->save_lmf) {
1177 offset += sizeof (MonoLMF);
1179 if (cfg->used_int_regs & (1 << X86_EBX)) {
1183 if (cfg->used_int_regs & (1 << X86_EDI)) {
1187 if (cfg->used_int_regs & (1 << X86_ESI)) {
1192 switch (cinfo->ret.storage) {
1193 case ArgValuetypeInReg:
1194 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1196 cfg->ret->opcode = OP_REGOFFSET;
1197 cfg->ret->inst_basereg = X86_EBP;
1198 cfg->ret->inst_offset = - offset;
1204 /* Allocate locals */
1205 offsets = mono_allocate_stack_slots (cfg, TRUE, &locals_stack_size, &locals_stack_align);
1206 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1207 char *mname = mono_method_full_name (cfg->method, TRUE);
1208 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1209 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1213 if (locals_stack_align) {
1214 int prev_offset = offset;
1216 offset += (locals_stack_align - 1);
1217 offset &= ~(locals_stack_align - 1);
1219 while (prev_offset < offset) {
1221 mini_gc_set_slot_type_from_fp (cfg, - prev_offset, SLOT_NOREF);
1224 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1225 cfg->locals_max_stack_offset = - offset;
1227 * EBP is at alignment 8 % MONO_ARCH_FRAME_ALIGNMENT, so if we
1228 * have locals larger than 8 bytes we need to make sure that
1229 * they have the appropriate offset.
1231 if (MONO_ARCH_FRAME_ALIGNMENT > 8 && locals_stack_align > 8)
1232 offset += MONO_ARCH_FRAME_ALIGNMENT - sizeof (gpointer) * 2;
1233 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1234 if (offsets [i] != -1) {
1235 MonoInst *inst = cfg->varinfo [i];
1236 inst->opcode = OP_REGOFFSET;
1237 inst->inst_basereg = X86_EBP;
1238 inst->inst_offset = - (offset + offsets [i]);
1239 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1242 offset += locals_stack_size;
1246 * Allocate arguments+return value
1249 switch (cinfo->ret.storage) {
1251 if (cfg->vret_addr) {
1253 * In the new IR, the cfg->vret_addr variable represents the
1254 * vtype return value.
1256 cfg->vret_addr->opcode = OP_REGOFFSET;
1257 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1258 cfg->vret_addr->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1259 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1260 printf ("vret_addr =");
1261 mono_print_ins (cfg->vret_addr);
1264 cfg->ret->opcode = OP_REGOFFSET;
1265 cfg->ret->inst_basereg = X86_EBP;
1266 cfg->ret->inst_offset = cinfo->ret.offset + ARGS_OFFSET;
1269 case ArgValuetypeInReg:
1272 cfg->ret->opcode = OP_REGVAR;
1273 cfg->ret->inst_c0 = cinfo->ret.reg;
1274 cfg->ret->dreg = cinfo->ret.reg;
1277 case ArgOnFloatFpStack:
1278 case ArgOnDoubleFpStack:
1281 g_assert_not_reached ();
1284 if (sig->call_convention == MONO_CALL_VARARG) {
1285 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1286 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1289 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1290 ArgInfo *ainfo = &cinfo->args [i];
1291 inst = cfg->args [i];
1292 if (inst->opcode != OP_REGVAR) {
1293 inst->opcode = OP_REGOFFSET;
1294 inst->inst_basereg = X86_EBP;
1296 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1299 cfg->stack_offset = offset;
1303 mono_arch_create_vars (MonoCompile *cfg)
1305 MonoMethodSignature *sig;
1308 sig = mono_method_signature (cfg->method);
1310 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1312 if (cinfo->ret.storage == ArgValuetypeInReg)
1313 cfg->ret_var_is_local = TRUE;
1314 if ((cinfo->ret.storage != ArgValuetypeInReg) && (MONO_TYPE_ISSTRUCT (sig->ret) || mini_is_gsharedvt_variable_type (cfg, sig->ret))) {
1315 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1318 cfg->arch_eh_jit_info = 1;
1322 * It is expensive to adjust esp for each individual fp argument pushed on the stack
1323 * so we try to do it just once when we have multiple fp arguments in a row.
1324 * We don't use this mechanism generally because for int arguments the generated code
1325 * is slightly bigger and new generation cpus optimize away the dependency chains
1326 * created by push instructions on the esp value.
1327 * fp_arg_setup is the first argument in the execution sequence where the esp register
1330 static G_GNUC_UNUSED int
1331 collect_fp_stack_space (MonoMethodSignature *sig, int start_arg, int *fp_arg_setup)
1336 for (; start_arg < sig->param_count; ++start_arg) {
1337 t = mini_type_get_underlying_type (NULL, sig->params [start_arg]);
1338 if (!t->byref && t->type == MONO_TYPE_R8) {
1339 fp_space += sizeof (double);
1340 *fp_arg_setup = start_arg;
1349 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1351 MonoMethodSignature *tmp_sig;
1355 * mono_ArgIterator_Setup assumes the signature cookie is
1356 * passed first and all the arguments which were before it are
1357 * passed on the stack after the signature. So compensate by
1358 * passing a different signature.
1360 tmp_sig = mono_metadata_signature_dup (call->signature);
1361 tmp_sig->param_count -= call->signature->sentinelpos;
1362 tmp_sig->sentinelpos = 0;
1363 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1365 if (cfg->compile_aot) {
1366 sig_reg = mono_alloc_ireg (cfg);
1367 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1368 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, sig_reg);
1370 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_X86_PUSH_IMM, -1, -1, tmp_sig);
1376 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1381 LLVMCallInfo *linfo;
1384 n = sig->param_count + sig->hasthis;
1386 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1388 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1391 * LLVM always uses the native ABI while we use our own ABI, the
1392 * only difference is the handling of vtypes:
1393 * - we only pass/receive them in registers in some cases, and only
1394 * in 1 or 2 integer registers.
1396 if (cinfo->ret.storage == ArgValuetypeInReg) {
1398 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1399 cfg->disable_llvm = TRUE;
1403 cfg->exception_message = g_strdup ("vtype ret in call");
1404 cfg->disable_llvm = TRUE;
1406 linfo->ret.storage = LLVMArgVtypeInReg;
1407 for (j = 0; j < 2; ++j)
1408 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1412 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage == ArgInIReg) {
1413 /* Vtype returned using a hidden argument */
1414 linfo->ret.storage = LLVMArgVtypeRetAddr;
1415 linfo->vret_arg_index = cinfo->vret_arg_index;
1418 if (mini_type_is_vtype (cfg, sig->ret) && cinfo->ret.storage != ArgInIReg) {
1420 cfg->exception_message = g_strdup ("vtype ret in call");
1421 cfg->disable_llvm = TRUE;
1424 for (i = 0; i < n; ++i) {
1425 ainfo = cinfo->args + i;
1427 if (i >= sig->hasthis)
1428 t = sig->params [i - sig->hasthis];
1430 t = &mono_defaults.int_class->byval_arg;
1432 linfo->args [i].storage = LLVMArgNone;
1434 switch (ainfo->storage) {
1436 linfo->args [i].storage = LLVMArgInIReg;
1438 case ArgInDoubleSSEReg:
1439 case ArgInFloatSSEReg:
1440 linfo->args [i].storage = LLVMArgInFPReg;
1443 if (mini_type_is_vtype (cfg, t)) {
1444 if (mono_class_value_size (mono_class_from_mono_type (t), NULL) == 0)
1445 /* LLVM seems to allocate argument space for empty structures too */
1446 linfo->args [i].storage = LLVMArgNone;
1448 linfo->args [i].storage = LLVMArgVtypeByVal;
1450 linfo->args [i].storage = LLVMArgInIReg;
1452 if (t->type == MONO_TYPE_R4)
1453 linfo->args [i].storage = LLVMArgInFPReg;
1454 else if (t->type == MONO_TYPE_R8)
1455 linfo->args [i].storage = LLVMArgInFPReg;
1459 case ArgValuetypeInReg:
1461 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1462 cfg->disable_llvm = TRUE;
1466 cfg->exception_message = g_strdup ("vtype arg");
1467 cfg->disable_llvm = TRUE;
1469 linfo->args [i].storage = LLVMArgVtypeInReg;
1470 for (j = 0; j < 2; ++j)
1471 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1475 cfg->exception_message = g_strdup ("ainfo->storage");
1476 cfg->disable_llvm = TRUE;
1486 emit_gc_param_slot_def (MonoCompile *cfg, int sp_offset, MonoType *t)
1488 if (cfg->compute_gc_maps) {
1491 /* On x86, the offsets are from the sp value before the start of the call sequence */
1493 t = &mono_defaults.int_class->byval_arg;
1494 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, sp_offset, t);
1499 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1502 MonoMethodSignature *sig;
1505 int sentinelpos = 0, sp_offset = 0;
1507 sig = call->signature;
1508 n = sig->param_count + sig->hasthis;
1510 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1512 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1513 sentinelpos = sig->sentinelpos + (sig->hasthis ? 1 : 0);
1515 if (cinfo->need_stack_align) {
1516 MONO_INST_NEW (cfg, arg, OP_SUB_IMM);
1517 arg->dreg = X86_ESP;
1518 arg->sreg1 = X86_ESP;
1519 arg->inst_imm = cinfo->stack_align_amount;
1520 MONO_ADD_INS (cfg->cbb, arg);
1521 for (i = 0; i < cinfo->stack_align_amount; i += sizeof (mgreg_t)) {
1524 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1528 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1529 if (cinfo->ret.storage == ArgValuetypeInReg) {
1531 * Tell the JIT to use a more efficient calling convention: call using
1532 * OP_CALL, compute the result location after the call, and save the
1535 call->vret_in_reg = TRUE;
1537 NULLIFY_INS (call->vret_var);
1541 // FIXME: Emit EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF everywhere
1543 /* Handle the case where there are no implicit arguments */
1544 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sentinelpos)) {
1545 emit_sig_cookie (cfg, call, cinfo);
1547 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1550 /* Arguments are pushed in the reverse order */
1551 for (i = n - 1; i >= 0; i --) {
1552 ArgInfo *ainfo = cinfo->args + i;
1553 MonoType *orig_type, *t;
1556 if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 1 && i == 0) {
1557 /* Push the vret arg before the first argument */
1559 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1560 vtarg->type = STACK_MP;
1561 vtarg->sreg1 = call->vret_var->dreg;
1562 MONO_ADD_INS (cfg->cbb, vtarg);
1564 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1567 if (i >= sig->hasthis)
1568 t = sig->params [i - sig->hasthis];
1570 t = &mono_defaults.int_class->byval_arg;
1572 t = mini_type_get_underlying_type (cfg->generic_sharing_context, t);
1574 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1576 in = call->args [i];
1577 arg->cil_code = in->cil_code;
1578 arg->sreg1 = in->dreg;
1579 arg->type = in->type;
1581 g_assert (in->dreg != -1);
1583 if (ainfo->storage == ArgGSharedVt) {
1584 arg->opcode = OP_OUTARG_VT;
1585 arg->sreg1 = in->dreg;
1586 arg->klass = in->klass;
1588 MONO_ADD_INS (cfg->cbb, arg);
1589 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
1593 g_assert (in->klass);
1595 if (t->type == MONO_TYPE_TYPEDBYREF) {
1596 size = sizeof (MonoTypedRef);
1597 align = sizeof (gpointer);
1600 size = mini_type_stack_size_full (cfg->generic_sharing_context, &in->klass->byval_arg, &align, sig->pinvoke);
1604 arg->opcode = OP_OUTARG_VT;
1605 arg->sreg1 = in->dreg;
1606 arg->klass = in->klass;
1607 arg->backend.size = size;
1609 MONO_ADD_INS (cfg->cbb, arg);
1611 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1616 switch (ainfo->storage) {
1618 arg->opcode = OP_X86_PUSH;
1620 if (t->type == MONO_TYPE_R4) {
1621 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 4);
1622 arg->opcode = OP_STORER4_MEMBASE_REG;
1623 arg->inst_destbasereg = X86_ESP;
1624 arg->inst_offset = 0;
1626 } else if (t->type == MONO_TYPE_R8) {
1627 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1628 arg->opcode = OP_STORER8_MEMBASE_REG;
1629 arg->inst_destbasereg = X86_ESP;
1630 arg->inst_offset = 0;
1632 } else if (t->type == MONO_TYPE_I8 || t->type == MONO_TYPE_U8) {
1634 MONO_EMIT_NEW_UNALU (cfg, OP_X86_PUSH, -1, in->dreg + 2);
1640 g_assert_not_reached ();
1643 MONO_ADD_INS (cfg->cbb, arg);
1645 sp_offset += argsize;
1647 if (cfg->compute_gc_maps) {
1649 /* FIXME: The == STACK_OBJ check might be fragile ? */
1650 if (sig->hasthis && i == 0 && call->args [i]->type == STACK_OBJ) {
1652 if (call->need_unbox_trampoline)
1653 /* The unbox trampoline transforms this into a managed pointer */
1654 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.int_class->this_arg);
1656 emit_gc_param_slot_def (cfg, sp_offset, &mono_defaults.object_class->byval_arg);
1658 emit_gc_param_slot_def (cfg, sp_offset, orig_type);
1662 for (j = 0; j < argsize; j += 4)
1663 emit_gc_param_slot_def (cfg, sp_offset - j, NULL);
1668 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sentinelpos)) {
1669 /* Emit the signature cookie just before the implicit arguments */
1670 emit_sig_cookie (cfg, call, cinfo);
1672 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1676 if (sig->ret && (MONO_TYPE_ISSTRUCT (sig->ret) || cinfo->vtype_retaddr)) {
1679 if (cinfo->ret.storage == ArgValuetypeInReg) {
1682 else if (cinfo->ret.storage == ArgInIReg) {
1684 /* The return address is passed in a register */
1685 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1686 vtarg->sreg1 = call->inst.dreg;
1687 vtarg->dreg = mono_alloc_ireg (cfg);
1688 MONO_ADD_INS (cfg->cbb, vtarg);
1690 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1691 } else if (cinfo->vtype_retaddr && cinfo->vret_arg_index == 0) {
1693 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
1694 vtarg->type = STACK_MP;
1695 vtarg->sreg1 = call->vret_var->dreg;
1696 MONO_ADD_INS (cfg->cbb, vtarg);
1698 emit_gc_param_slot_def (cfg, sp_offset, NULL);
1701 /* if the function returns a struct on stack, the called method already does a ret $0x4 */
1702 if (cinfo->ret.storage != ArgValuetypeInReg)
1703 cinfo->stack_usage -= 4;
1706 call->stack_usage = cinfo->stack_usage;
1707 call->stack_align_amount = cinfo->stack_align_amount;
1708 cfg->arch.param_area_size = MAX (cfg->arch.param_area_size, sp_offset);
1712 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
1715 int size = ins->backend.size;
1717 if (cfg->gsharedvt && mini_is_gsharedvt_klass (cfg, ins->klass)) {
1719 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1720 arg->sreg1 = src->dreg;
1721 MONO_ADD_INS (cfg->cbb, arg);
1722 } else if (size <= 4) {
1723 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
1724 arg->sreg1 = src->dreg;
1726 MONO_ADD_INS (cfg->cbb, arg);
1727 } else if (size <= 20) {
1728 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 4));
1729 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
1731 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
1732 arg->inst_basereg = src->dreg;
1733 arg->inst_offset = 0;
1734 arg->inst_imm = size;
1736 MONO_ADD_INS (cfg->cbb, arg);
1741 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
1743 MonoType *ret = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1746 if (ret->type == MONO_TYPE_R4) {
1747 if (COMPILE_LLVM (cfg))
1748 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1751 } else if (ret->type == MONO_TYPE_R8) {
1752 if (COMPILE_LLVM (cfg))
1753 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
1756 } else if (ret->type == MONO_TYPE_I8 || ret->type == MONO_TYPE_U8) {
1757 if (COMPILE_LLVM (cfg))
1758 MONO_EMIT_NEW_UNALU (cfg, OP_LMOVE, cfg->ret->dreg, val->dreg);
1760 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EAX, val->dreg + 1);
1761 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, X86_EDX, val->dreg + 2);
1767 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
1771 * Allow tracing to work with this interface (with an optional argument)
1774 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
1778 g_assert (MONO_ARCH_FRAME_ALIGNMENT >= 8);
1779 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 8);
1781 /* if some args are passed in registers, we need to save them here */
1782 x86_push_reg (code, X86_EBP);
1784 if (cfg->compile_aot) {
1785 x86_push_imm (code, cfg->method);
1786 x86_mov_reg_imm (code, X86_EAX, func);
1787 x86_call_reg (code, X86_EAX);
1789 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
1790 x86_push_imm (code, cfg->method);
1791 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1792 x86_call_code (code, 0);
1794 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT);
1808 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
1811 int arg_size = 0, stack_usage = 0, save_mode = SAVE_NONE;
1812 MonoMethod *method = cfg->method;
1813 MonoType *ret_type = mini_type_get_underlying_type (cfg->generic_sharing_context, mono_method_signature (method)->ret);
1815 switch (ret_type->type) {
1816 case MONO_TYPE_VOID:
1817 /* special case string .ctor icall */
1818 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class) {
1819 save_mode = SAVE_EAX;
1820 stack_usage = enable_arguments ? 8 : 4;
1822 save_mode = SAVE_NONE;
1826 save_mode = SAVE_EAX_EDX;
1827 stack_usage = enable_arguments ? 16 : 8;
1831 save_mode = SAVE_FP;
1832 stack_usage = enable_arguments ? 16 : 8;
1834 case MONO_TYPE_GENERICINST:
1835 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1836 save_mode = SAVE_EAX;
1837 stack_usage = enable_arguments ? 8 : 4;
1841 case MONO_TYPE_VALUETYPE:
1842 // FIXME: Handle SMALL_STRUCT_IN_REG here for proper alignment on darwin-x86
1843 save_mode = SAVE_STRUCT;
1844 stack_usage = enable_arguments ? 4 : 0;
1847 save_mode = SAVE_EAX;
1848 stack_usage = enable_arguments ? 8 : 4;
1852 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage - 4);
1854 switch (save_mode) {
1856 x86_push_reg (code, X86_EDX);
1857 x86_push_reg (code, X86_EAX);
1858 if (enable_arguments) {
1859 x86_push_reg (code, X86_EDX);
1860 x86_push_reg (code, X86_EAX);
1865 x86_push_reg (code, X86_EAX);
1866 if (enable_arguments) {
1867 x86_push_reg (code, X86_EAX);
1872 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1873 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1874 if (enable_arguments) {
1875 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
1876 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
1881 if (enable_arguments) {
1882 x86_push_membase (code, X86_EBP, 8);
1891 if (cfg->compile_aot) {
1892 x86_push_imm (code, method);
1893 x86_mov_reg_imm (code, X86_EAX, func);
1894 x86_call_reg (code, X86_EAX);
1896 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
1897 x86_push_imm (code, method);
1898 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_ABS, func);
1899 x86_call_code (code, 0);
1902 x86_alu_reg_imm (code, X86_ADD, X86_ESP, arg_size + 4);
1904 switch (save_mode) {
1906 x86_pop_reg (code, X86_EAX);
1907 x86_pop_reg (code, X86_EDX);
1910 x86_pop_reg (code, X86_EAX);
1913 x86_fld_membase (code, X86_ESP, 0, TRUE);
1914 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
1921 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - stack_usage);
1926 #define EMIT_COND_BRANCH(ins,cond,sign) \
1927 if (ins->inst_true_bb->native_offset) { \
1928 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1930 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1931 if ((cfg->opt & MONO_OPT_BRANCH) && \
1932 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1933 x86_branch8 (code, cond, 0, sign); \
1935 x86_branch32 (code, cond, 0, sign); \
1939 * Emit an exception if condition is fail and
1940 * if possible do a directly branch to target
1942 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1944 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1945 if (tins == NULL) { \
1946 mono_add_patch_info (cfg, code - cfg->native_code, \
1947 MONO_PATCH_INFO_EXC, exc_name); \
1948 x86_branch32 (code, cond, 0, signed); \
1950 EMIT_COND_BRANCH (tins, cond, signed); \
1954 #define EMIT_FPCOMPARE(code) do { \
1955 x86_fcompp (code); \
1956 x86_fnstsw (code); \
1961 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1963 gboolean needs_paddings = TRUE;
1965 MonoJumpInfo *jinfo = NULL;
1967 if (cfg->abs_patches) {
1968 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
1969 if (jinfo && jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR)
1970 needs_paddings = FALSE;
1973 if (cfg->compile_aot)
1974 needs_paddings = FALSE;
1975 /*The address must be 4 bytes aligned to avoid spanning multiple cache lines.
1976 This is required for code patching to be safe on SMP machines.
1978 pad_size = (guint32)(code + 1 - cfg->native_code) & 0x3;
1979 #ifndef __native_client_codegen__
1980 if (needs_paddings && pad_size)
1981 x86_padding (code, 4 - pad_size);
1984 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1985 x86_call_code (code, 0);
1990 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_IADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_ISBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB_IMM)))
1993 * mono_peephole_pass_1:
1995 * Perform peephole opts which should/can be performed before local regalloc
1998 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2002 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2003 MonoInst *last_ins = ins->prev;
2005 switch (ins->opcode) {
2008 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2010 * X86_LEA is like ADD, but doesn't have the
2011 * sreg1==dreg restriction.
2013 ins->opcode = OP_X86_LEA_MEMBASE;
2014 ins->inst_basereg = ins->sreg1;
2015 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2016 ins->opcode = OP_X86_INC_REG;
2020 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS)) {
2021 ins->opcode = OP_X86_LEA_MEMBASE;
2022 ins->inst_basereg = ins->sreg1;
2023 ins->inst_imm = -ins->inst_imm;
2024 } else if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2025 ins->opcode = OP_X86_DEC_REG;
2027 case OP_COMPARE_IMM:
2028 case OP_ICOMPARE_IMM:
2029 /* OP_COMPARE_IMM (reg, 0)
2031 * OP_X86_TEST_NULL (reg)
2034 ins->opcode = OP_X86_TEST_NULL;
2036 case OP_X86_COMPARE_MEMBASE_IMM:
2038 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2039 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2041 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2042 * OP_COMPARE_IMM reg, imm
2044 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2046 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2047 ins->inst_basereg == last_ins->inst_destbasereg &&
2048 ins->inst_offset == last_ins->inst_offset) {
2049 ins->opcode = OP_COMPARE_IMM;
2050 ins->sreg1 = last_ins->sreg1;
2052 /* check if we can remove cmp reg,0 with test null */
2054 ins->opcode = OP_X86_TEST_NULL;
2058 case OP_X86_PUSH_MEMBASE:
2059 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG ||
2060 last_ins->opcode == OP_STORE_MEMBASE_REG) &&
2061 ins->inst_basereg == last_ins->inst_destbasereg &&
2062 ins->inst_offset == last_ins->inst_offset) {
2063 ins->opcode = OP_X86_PUSH;
2064 ins->sreg1 = last_ins->sreg1;
2069 mono_peephole_ins (bb, ins);
2074 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2078 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2079 switch (ins->opcode) {
2081 /* reg = 0 -> XOR (reg, reg) */
2082 /* XOR sets cflags on x86, so we cant do it always */
2083 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2086 ins->opcode = OP_IXOR;
2087 ins->sreg1 = ins->dreg;
2088 ins->sreg2 = ins->dreg;
2091 * Convert succeeding STORE_MEMBASE_IMM 0 ins to STORE_MEMBASE_REG
2092 * since it takes 3 bytes instead of 7.
2094 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2095 if ((ins2->opcode == OP_STORE_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2096 ins2->opcode = OP_STORE_MEMBASE_REG;
2097 ins2->sreg1 = ins->dreg;
2099 else if ((ins2->opcode == OP_STOREI4_MEMBASE_IMM) && (ins2->inst_imm == 0)) {
2100 ins2->opcode = OP_STOREI4_MEMBASE_REG;
2101 ins2->sreg1 = ins->dreg;
2103 else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM)) {
2104 /* Continue iteration */
2113 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2114 ins->opcode = OP_X86_INC_REG;
2118 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2119 ins->opcode = OP_X86_DEC_REG;
2123 mono_peephole_ins (bb, ins);
2128 * mono_arch_lowering_pass:
2130 * Converts complex opcodes into simpler ones so that each IR instruction
2131 * corresponds to one machine instruction.
2134 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2136 MonoInst *ins, *next;
2139 * FIXME: Need to add more instructions, but the current machine
2140 * description can't model some parts of the composite instructions like
2143 MONO_BB_FOR_EACH_INS_SAFE (bb, next, ins) {
2144 switch (ins->opcode) {
2147 case OP_IDIV_UN_IMM:
2148 case OP_IREM_UN_IMM:
2150 * Keep the cases where we could generated optimized code, otherwise convert
2151 * to the non-imm variant.
2153 if ((ins->opcode == OP_IREM_IMM) && mono_is_power_of_two (ins->inst_imm) >= 0)
2155 mono_decompose_op_imm (cfg, bb, ins);
2162 bb->max_vreg = cfg->next_vreg;
2166 branch_cc_table [] = {
2167 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2168 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2169 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2172 /* Maps CMP_... constants to X86_CC_... constants */
2175 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2176 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2180 cc_signed_table [] = {
2181 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2182 FALSE, FALSE, FALSE, FALSE
2185 static unsigned char*
2186 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int size, gboolean is_signed)
2188 #define XMM_TEMP_REG 0
2189 /*This SSE2 optimization must not be done which OPT_SIMD in place as it clobbers xmm0.*/
2190 /*The xmm pass decomposes OP_FCONV_ ops anyway anyway.*/
2191 if (cfg->opt & MONO_OPT_SSE2 && size < 8 && !(cfg->opt & MONO_OPT_SIMD)) {
2192 /* optimize by assigning a local var for this use so we avoid
2193 * the stack manipulations */
2194 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2195 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
2196 x86_movsd_reg_membase (code, XMM_TEMP_REG, X86_ESP, 0);
2197 x86_cvttsd2si (code, dreg, XMM_TEMP_REG);
2198 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
2200 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2202 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2205 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
2206 x86_fnstcw_membase(code, X86_ESP, 0);
2207 x86_mov_reg_membase (code, dreg, X86_ESP, 0, 2);
2208 x86_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2209 x86_mov_membase_reg (code, X86_ESP, 2, dreg, 2);
2210 x86_fldcw_membase (code, X86_ESP, 2);
2212 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
2213 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
2214 x86_pop_reg (code, dreg);
2215 /* FIXME: need the high register
2216 * x86_pop_reg (code, dreg_high);
2219 x86_push_reg (code, X86_EAX); // SP = SP - 4
2220 x86_fist_pop_membase (code, X86_ESP, 0, FALSE);
2221 x86_pop_reg (code, dreg);
2223 x86_fldcw_membase (code, X86_ESP, 0);
2224 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2227 x86_widen_reg (code, dreg, dreg, is_signed, FALSE);
2229 x86_widen_reg (code, dreg, dreg, is_signed, TRUE);
2233 static unsigned char*
2234 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2236 int sreg = tree->sreg1;
2237 int need_touch = FALSE;
2239 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2248 * If requested stack size is larger than one page,
2249 * perform stack-touch operation
2252 * Generate stack probe code.
2253 * Under Windows, it is necessary to allocate one page at a time,
2254 * "touching" stack after each successful sub-allocation. This is
2255 * because of the way stack growth is implemented - there is a
2256 * guard page before the lowest stack page that is currently commited.
2257 * Stack normally grows sequentially so OS traps access to the
2258 * guard page and commits more pages when needed.
2260 x86_test_reg_imm (code, sreg, ~0xFFF);
2261 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2263 br[2] = code; /* loop */
2264 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
2265 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
2268 * By the end of the loop, sreg2 is smaller than 0x1000, so the init routine
2269 * that follows only initializes the last part of the area.
2271 /* Same as the init code below with size==0x1000 */
2272 if (tree->flags & MONO_INST_INIT) {
2273 x86_push_reg (code, X86_EAX);
2274 x86_push_reg (code, X86_ECX);
2275 x86_push_reg (code, X86_EDI);
2276 x86_mov_reg_imm (code, X86_ECX, (0x1000 >> 2));
2277 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2278 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
2280 x86_prefix (code, X86_REP_PREFIX);
2282 x86_pop_reg (code, X86_EDI);
2283 x86_pop_reg (code, X86_ECX);
2284 x86_pop_reg (code, X86_EAX);
2287 x86_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2288 x86_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2289 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2290 x86_patch (br[3], br[2]);
2291 x86_test_reg_reg (code, sreg, sreg);
2292 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2293 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2295 br[1] = code; x86_jump8 (code, 0);
2297 x86_patch (br[0], code);
2298 x86_alu_reg_reg (code, X86_SUB, X86_ESP, sreg);
2299 x86_patch (br[1], code);
2300 x86_patch (br[4], code);
2303 x86_alu_reg_reg (code, X86_SUB, X86_ESP, tree->sreg1);
2305 if (tree->flags & MONO_INST_INIT) {
2307 if (tree->dreg != X86_EAX && sreg != X86_EAX) {
2308 x86_push_reg (code, X86_EAX);
2311 if (tree->dreg != X86_ECX && sreg != X86_ECX) {
2312 x86_push_reg (code, X86_ECX);
2315 if (tree->dreg != X86_EDI && sreg != X86_EDI) {
2316 x86_push_reg (code, X86_EDI);
2320 x86_shift_reg_imm (code, X86_SHR, sreg, 2);
2321 if (sreg != X86_ECX)
2322 x86_mov_reg_reg (code, X86_ECX, sreg, 4);
2323 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EAX);
2325 x86_lea_membase (code, X86_EDI, X86_ESP, offset);
2327 x86_prefix (code, X86_REP_PREFIX);
2330 if (tree->dreg != X86_EDI && sreg != X86_EDI)
2331 x86_pop_reg (code, X86_EDI);
2332 if (tree->dreg != X86_ECX && sreg != X86_ECX)
2333 x86_pop_reg (code, X86_ECX);
2334 if (tree->dreg != X86_EAX && sreg != X86_EAX)
2335 x86_pop_reg (code, X86_EAX);
2342 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2344 /* Move return value to the target register */
2345 switch (ins->opcode) {
2348 case OP_CALL_MEMBASE:
2349 if (ins->dreg != X86_EAX)
2350 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
2360 static int tls_gs_offset;
2364 mono_x86_have_tls_get (void)
2367 static gboolean have_tls_get = FALSE;
2368 static gboolean inited = FALSE;
2372 return have_tls_get;
2374 ins = (guint32*)pthread_getspecific;
2376 * We're looking for these two instructions:
2378 * mov 0x4(%esp),%eax
2379 * mov %gs:[offset](,%eax,4),%eax
2381 have_tls_get = ins [0] == 0x0424448b && ins [1] == 0x85048b65;
2382 tls_gs_offset = ins [2];
2386 return have_tls_get;
2387 #elif defined(TARGET_ANDROID)
2395 mono_x86_emit_tls_set (guint8* code, int sreg, int tls_offset)
2397 #if defined(__APPLE__)
2398 x86_prefix (code, X86_GS_PREFIX);
2399 x86_mov_mem_reg (code, tls_gs_offset + (tls_offset * 4), sreg, 4);
2400 #elif defined(TARGET_WIN32)
2401 g_assert_not_reached ();
2403 x86_prefix (code, X86_GS_PREFIX);
2404 x86_mov_mem_reg (code, tls_offset, sreg, 4);
2410 * mono_x86_emit_tls_get:
2411 * @code: buffer to store code to
2412 * @dreg: hard register where to place the result
2413 * @tls_offset: offset info
2415 * mono_x86_emit_tls_get emits in @code the native code that puts in
2416 * the dreg register the item in the thread local storage identified
2419 * Returns: a pointer to the end of the stored code
2422 mono_x86_emit_tls_get (guint8* code, int dreg, int tls_offset)
2424 #if defined(__APPLE__)
2425 x86_prefix (code, X86_GS_PREFIX);
2426 x86_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 4), 4);
2427 #elif defined(TARGET_WIN32)
2429 * See the Under the Hood article in the May 1996 issue of Microsoft Systems
2430 * Journal and/or a disassembly of the TlsGet () function.
2432 g_assert (tls_offset < 64);
2433 x86_prefix (code, X86_FS_PREFIX);
2434 x86_mov_reg_mem (code, dreg, 0x18, 4);
2435 /* Dunno what this does but TlsGetValue () contains it */
2436 x86_alu_membase_imm (code, X86_AND, dreg, 0x34, 0);
2437 x86_mov_reg_membase (code, dreg, dreg, 3600 + (tls_offset * 4), 4);
2439 if (optimize_for_xen) {
2440 x86_prefix (code, X86_GS_PREFIX);
2441 x86_mov_reg_mem (code, dreg, 0, 4);
2442 x86_mov_reg_membase (code, dreg, dreg, tls_offset, 4);
2444 x86_prefix (code, X86_GS_PREFIX);
2445 x86_mov_reg_mem (code, dreg, tls_offset, 4);
2452 * emit_load_volatile_arguments:
2454 * Load volatile arguments from the stack to the original input registers.
2455 * Required before a tail call.
2458 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2460 MonoMethod *method = cfg->method;
2461 MonoMethodSignature *sig;
2466 /* FIXME: Generate intermediate code instead */
2468 sig = mono_method_signature (method);
2470 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2472 /* This is the opposite of the code in emit_prolog */
2474 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2475 ArgInfo *ainfo = cinfo->args + i;
2477 inst = cfg->args [i];
2479 if (sig->hasthis && (i == 0))
2480 arg_type = &mono_defaults.object_class->byval_arg;
2482 arg_type = sig->params [i - sig->hasthis];
2485 * On x86, the arguments are either in their original stack locations, or in
2488 if (inst->opcode == OP_REGVAR) {
2489 g_assert (ainfo->storage == ArgOnStack);
2491 x86_mov_membase_reg (code, X86_EBP, inst->inst_offset, inst->dreg, 4);
2498 #define REAL_PRINT_REG(text,reg) \
2499 mono_assert (reg >= 0); \
2500 x86_push_reg (code, X86_EAX); \
2501 x86_push_reg (code, X86_EDX); \
2502 x86_push_reg (code, X86_ECX); \
2503 x86_push_reg (code, reg); \
2504 x86_push_imm (code, reg); \
2505 x86_push_imm (code, text " %d %p\n"); \
2506 x86_mov_reg_imm (code, X86_EAX, printf); \
2507 x86_call_reg (code, X86_EAX); \
2508 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 3*4); \
2509 x86_pop_reg (code, X86_ECX); \
2510 x86_pop_reg (code, X86_EDX); \
2511 x86_pop_reg (code, X86_EAX);
2513 /* REAL_PRINT_REG does not appear to be used, and was not adapted to work with Native Client. */
2514 #ifdef __native__client_codegen__
2515 #define REAL_PRINT_REG(text, reg) g_assert_not_reached()
2518 /* benchmark and set based on cpu */
2519 #define LOOP_ALIGNMENT 8
2520 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2524 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2529 guint8 *code = cfg->native_code + cfg->code_len;
2532 if (cfg->opt & MONO_OPT_LOOP) {
2533 int pad, align = LOOP_ALIGNMENT;
2534 /* set alignment depending on cpu */
2535 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2537 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2538 x86_padding (code, pad);
2539 cfg->code_len += pad;
2540 bb->native_offset = cfg->code_len;
2543 #ifdef __native_client_codegen__
2545 /* For Native Client, all indirect call/jump targets must be */
2546 /* 32-byte aligned. Exception handler blocks are jumped to */
2547 /* indirectly as well. */
2548 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
2549 (bb->flags & BB_EXCEPTION_HANDLER);
2551 /* if ((cfg->code_len & kNaClAlignmentMask) != 0) { */
2552 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
2553 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
2554 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
2555 cfg->code_len += pad;
2556 bb->native_offset = cfg->code_len;
2559 #endif /* __native_client_codegen__ */
2560 if (cfg->verbose_level > 2)
2561 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2563 cpos = bb->max_offset;
2565 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2566 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2567 g_assert (!cfg->compile_aot);
2570 cov->data [bb->dfn].cil_code = bb->cil_code;
2571 /* this is not thread save, but good enough */
2572 x86_inc_mem (code, &cov->data [bb->dfn].count);
2575 offset = code - cfg->native_code;
2577 mono_debug_open_block (cfg, bb, offset);
2579 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2580 x86_breakpoint (code);
2582 MONO_BB_FOR_EACH_INS (bb, ins) {
2583 offset = code - cfg->native_code;
2585 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2587 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
2589 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
2590 cfg->code_size *= 2;
2591 cfg->native_code = mono_realloc_native_code(cfg);
2592 code = cfg->native_code + offset;
2593 cfg->stat_code_reallocs++;
2596 if (cfg->debug_info)
2597 mono_debug_record_line_number (cfg, ins, offset);
2599 switch (ins->opcode) {
2601 x86_mul_reg (code, ins->sreg2, TRUE);
2604 x86_mul_reg (code, ins->sreg2, FALSE);
2606 case OP_X86_SETEQ_MEMBASE:
2607 case OP_X86_SETNE_MEMBASE:
2608 x86_set_membase (code, ins->opcode == OP_X86_SETEQ_MEMBASE ? X86_CC_EQ : X86_CC_NE,
2609 ins->inst_basereg, ins->inst_offset, TRUE);
2611 case OP_STOREI1_MEMBASE_IMM:
2612 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2614 case OP_STOREI2_MEMBASE_IMM:
2615 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2617 case OP_STORE_MEMBASE_IMM:
2618 case OP_STOREI4_MEMBASE_IMM:
2619 x86_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2621 case OP_STOREI1_MEMBASE_REG:
2622 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2624 case OP_STOREI2_MEMBASE_REG:
2625 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2627 case OP_STORE_MEMBASE_REG:
2628 case OP_STOREI4_MEMBASE_REG:
2629 x86_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2631 case OP_STORE_MEM_IMM:
2632 x86_mov_mem_imm (code, ins->inst_p0, ins->inst_c0, 4);
2635 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2639 /* These are created by the cprop pass so they use inst_imm as the source */
2640 x86_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2643 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, FALSE);
2646 x86_widen_mem (code, ins->dreg, ins->inst_imm, FALSE, TRUE);
2648 case OP_LOAD_MEMBASE:
2649 case OP_LOADI4_MEMBASE:
2650 case OP_LOADU4_MEMBASE:
2651 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2653 case OP_LOADU1_MEMBASE:
2654 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2656 case OP_LOADI1_MEMBASE:
2657 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2659 case OP_LOADU2_MEMBASE:
2660 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2662 case OP_LOADI2_MEMBASE:
2663 x86_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2665 case OP_ICONV_TO_I1:
2667 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2669 case OP_ICONV_TO_I2:
2671 x86_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2673 case OP_ICONV_TO_U1:
2674 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2676 case OP_ICONV_TO_U2:
2677 x86_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2681 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2683 case OP_COMPARE_IMM:
2684 case OP_ICOMPARE_IMM:
2685 x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2687 case OP_X86_COMPARE_MEMBASE_REG:
2688 x86_alu_membase_reg (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2690 case OP_X86_COMPARE_MEMBASE_IMM:
2691 x86_alu_membase_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2693 case OP_X86_COMPARE_MEMBASE8_IMM:
2694 x86_alu_membase8_imm (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2696 case OP_X86_COMPARE_REG_MEMBASE:
2697 x86_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2699 case OP_X86_COMPARE_MEM_IMM:
2700 x86_alu_mem_imm (code, X86_CMP, ins->inst_offset, ins->inst_imm);
2702 case OP_X86_TEST_NULL:
2703 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
2705 case OP_X86_ADD_MEMBASE_IMM:
2706 x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2708 case OP_X86_ADD_REG_MEMBASE:
2709 x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
2711 case OP_X86_SUB_MEMBASE_IMM:
2712 x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2714 case OP_X86_SUB_REG_MEMBASE:
2715 x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
2717 case OP_X86_AND_MEMBASE_IMM:
2718 x86_alu_membase_imm (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2720 case OP_X86_OR_MEMBASE_IMM:
2721 x86_alu_membase_imm (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2723 case OP_X86_XOR_MEMBASE_IMM:
2724 x86_alu_membase_imm (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
2726 case OP_X86_ADD_MEMBASE_REG:
2727 x86_alu_membase_reg (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2729 case OP_X86_SUB_MEMBASE_REG:
2730 x86_alu_membase_reg (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2732 case OP_X86_AND_MEMBASE_REG:
2733 x86_alu_membase_reg (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2735 case OP_X86_OR_MEMBASE_REG:
2736 x86_alu_membase_reg (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2738 case OP_X86_XOR_MEMBASE_REG:
2739 x86_alu_membase_reg (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2);
2741 case OP_X86_INC_MEMBASE:
2742 x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
2744 case OP_X86_INC_REG:
2745 x86_inc_reg (code, ins->dreg);
2747 case OP_X86_DEC_MEMBASE:
2748 x86_dec_membase (code, ins->inst_basereg, ins->inst_offset);
2750 case OP_X86_DEC_REG:
2751 x86_dec_reg (code, ins->dreg);
2753 case OP_X86_MUL_REG_MEMBASE:
2754 x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
2756 case OP_X86_AND_REG_MEMBASE:
2757 x86_alu_reg_membase (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset);
2759 case OP_X86_OR_REG_MEMBASE:
2760 x86_alu_reg_membase (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset);
2762 case OP_X86_XOR_REG_MEMBASE:
2763 x86_alu_reg_membase (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset);
2766 x86_breakpoint (code);
2768 case OP_RELAXED_NOP:
2769 x86_prefix (code, X86_REP_PREFIX);
2777 case OP_DUMMY_STORE:
2778 case OP_NOT_REACHED:
2781 case OP_SEQ_POINT: {
2784 if (cfg->compile_aot)
2788 * Read from the single stepping trigger page. This will cause a
2789 * SIGSEGV when single stepping is enabled.
2790 * We do this _before_ the breakpoint, so single stepping after
2791 * a breakpoint is hit will step to the next IL offset.
2793 if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
2794 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)ss_trigger_page);
2796 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
2799 * A placeholder for a possible breakpoint inserted by
2800 * mono_arch_set_breakpoint ().
2802 for (i = 0; i < 6; ++i)
2805 * Add an additional nop so skipping the bp doesn't cause the ip to point
2806 * to another IL offset.
2814 x86_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2818 x86_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2823 x86_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2827 x86_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2832 x86_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2836 x86_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2841 x86_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2845 x86_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2848 x86_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2852 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2856 #if defined( __native_client_codegen__ )
2857 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2858 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2861 * The code is the same for div/rem, the allocator will allocate dreg
2862 * to RAX/RDX as appropriate.
2864 if (ins->sreg2 == X86_EDX) {
2865 /* cdq clobbers this */
2866 x86_push_reg (code, ins->sreg2);
2868 x86_div_membase (code, X86_ESP, 0, TRUE);
2869 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2872 x86_div_reg (code, ins->sreg2, TRUE);
2877 #if defined( __native_client_codegen__ )
2878 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
2879 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
2881 if (ins->sreg2 == X86_EDX) {
2882 x86_push_reg (code, ins->sreg2);
2883 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2884 x86_div_membase (code, X86_ESP, 0, FALSE);
2885 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
2887 x86_alu_reg_reg (code, X86_XOR, X86_EDX, X86_EDX);
2888 x86_div_reg (code, ins->sreg2, FALSE);
2892 #if defined( __native_client_codegen__ )
2893 if (ins->inst_imm == 0) {
2894 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "DivideByZeroException");
2895 x86_jump32 (code, 0);
2899 x86_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
2901 x86_div_reg (code, ins->sreg2, TRUE);
2904 int power = mono_is_power_of_two (ins->inst_imm);
2906 g_assert (ins->sreg1 == X86_EAX);
2907 g_assert (ins->dreg == X86_EAX);
2908 g_assert (power >= 0);
2911 /* Based on http://compilers.iecc.com/comparch/article/93-04-079 */
2913 x86_alu_reg_imm (code, X86_AND, X86_EAX, 1);
2915 * If the divident is >= 0, this does not nothing. If it is positive, it
2916 * it transforms %eax=0 into %eax=0, and %eax=1 into %eax=-1.
2918 x86_alu_reg_reg (code, X86_XOR, X86_EAX, X86_EDX);
2919 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2920 } else if (power == 0) {
2921 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
2923 /* Based on gcc code */
2925 /* Add compensation for negative dividents */
2927 x86_shift_reg_imm (code, X86_SHR, X86_EDX, 32 - power);
2928 x86_alu_reg_reg (code, X86_ADD, X86_EAX, X86_EDX);
2929 /* Compute remainder */
2930 x86_alu_reg_imm (code, X86_AND, X86_EAX, (1 << power) - 1);
2931 /* Remove compensation */
2932 x86_alu_reg_reg (code, X86_SUB, X86_EAX, X86_EDX);
2937 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2941 x86_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2944 x86_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2948 x86_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2951 g_assert (ins->sreg2 == X86_ECX);
2952 x86_shift_reg (code, X86_SHL, ins->dreg);
2955 g_assert (ins->sreg2 == X86_ECX);
2956 x86_shift_reg (code, X86_SAR, ins->dreg);
2960 x86_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2963 case OP_ISHR_UN_IMM:
2964 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2967 g_assert (ins->sreg2 == X86_ECX);
2968 x86_shift_reg (code, X86_SHR, ins->dreg);
2972 x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2975 guint8 *jump_to_end;
2977 /* handle shifts below 32 bits */
2978 x86_shld_reg (code, ins->backend.reg3, ins->sreg1);
2979 x86_shift_reg (code, X86_SHL, ins->sreg1);
2981 x86_test_reg_imm (code, X86_ECX, 32);
2982 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
2984 /* handle shift over 32 bit */
2985 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
2986 x86_clear_reg (code, ins->sreg1);
2988 x86_patch (jump_to_end, code);
2992 guint8 *jump_to_end;
2994 /* handle shifts below 32 bits */
2995 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
2996 x86_shift_reg (code, X86_SAR, ins->backend.reg3);
2998 x86_test_reg_imm (code, X86_ECX, 32);
2999 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3001 /* handle shifts over 31 bits */
3002 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3003 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 31);
3005 x86_patch (jump_to_end, code);
3009 guint8 *jump_to_end;
3011 /* handle shifts below 32 bits */
3012 x86_shrd_reg (code, ins->sreg1, ins->backend.reg3);
3013 x86_shift_reg (code, X86_SHR, ins->backend.reg3);
3015 x86_test_reg_imm (code, X86_ECX, 32);
3016 jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
3018 /* handle shifts over 31 bits */
3019 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3020 x86_clear_reg (code, ins->backend.reg3);
3022 x86_patch (jump_to_end, code);
3026 if (ins->inst_imm >= 32) {
3027 x86_mov_reg_reg (code, ins->backend.reg3, ins->sreg1, 4);
3028 x86_clear_reg (code, ins->sreg1);
3029 x86_shift_reg_imm (code, X86_SHL, ins->backend.reg3, ins->inst_imm - 32);
3031 x86_shld_reg_imm (code, ins->backend.reg3, ins->sreg1, ins->inst_imm);
3032 x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
3036 if (ins->inst_imm >= 32) {
3037 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3038 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, 0x1f);
3039 x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
3041 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3042 x86_shift_reg_imm (code, X86_SAR, ins->backend.reg3, ins->inst_imm);
3045 case OP_LSHR_UN_IMM:
3046 if (ins->inst_imm >= 32) {
3047 x86_mov_reg_reg (code, ins->sreg1, ins->backend.reg3, 4);
3048 x86_clear_reg (code, ins->backend.reg3);
3049 x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
3051 x86_shrd_reg_imm (code, ins->sreg1, ins->backend.reg3, ins->inst_imm);
3052 x86_shift_reg_imm (code, X86_SHR, ins->backend.reg3, ins->inst_imm);
3056 x86_not_reg (code, ins->sreg1);
3059 x86_neg_reg (code, ins->sreg1);
3063 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3067 switch (ins->inst_imm) {
3071 if (ins->dreg != ins->sreg1)
3072 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3073 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3076 /* LEA r1, [r2 + r2*2] */
3077 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3080 /* LEA r1, [r2 + r2*4] */
3081 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3084 /* LEA r1, [r2 + r2*2] */
3086 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3087 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3090 /* LEA r1, [r2 + r2*8] */
3091 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3094 /* LEA r1, [r2 + r2*4] */
3096 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3097 x86_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3100 /* LEA r1, [r2 + r2*2] */
3102 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3103 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3106 /* LEA r1, [r2 + r2*4] */
3107 /* LEA r1, [r1 + r1*4] */
3108 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3109 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3112 /* LEA r1, [r2 + r2*4] */
3114 /* LEA r1, [r1 + r1*4] */
3115 x86_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3116 x86_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3117 x86_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3120 x86_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3125 x86_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3126 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3128 case OP_IMUL_OVF_UN: {
3129 /* the mul operation and the exception check should most likely be split */
3130 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3131 /*g_assert (ins->sreg2 == X86_EAX);
3132 g_assert (ins->dreg == X86_EAX);*/
3133 if (ins->sreg2 == X86_EAX) {
3134 non_eax_reg = ins->sreg1;
3135 } else if (ins->sreg1 == X86_EAX) {
3136 non_eax_reg = ins->sreg2;
3138 /* no need to save since we're going to store to it anyway */
3139 if (ins->dreg != X86_EAX) {
3141 x86_push_reg (code, X86_EAX);
3143 x86_mov_reg_reg (code, X86_EAX, ins->sreg1, 4);
3144 non_eax_reg = ins->sreg2;
3146 if (ins->dreg == X86_EDX) {
3149 x86_push_reg (code, X86_EAX);
3151 } else if (ins->dreg != X86_EAX) {
3153 x86_push_reg (code, X86_EDX);
3155 x86_mul_reg (code, non_eax_reg, FALSE);
3156 /* save before the check since pop and mov don't change the flags */
3157 if (ins->dreg != X86_EAX)
3158 x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
3160 x86_pop_reg (code, X86_EDX);
3162 x86_pop_reg (code, X86_EAX);
3163 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3167 x86_mov_reg_imm (code, ins->dreg, ins->inst_c0);
3170 g_assert_not_reached ();
3171 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3172 x86_mov_reg_imm (code, ins->dreg, 0);
3175 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3176 x86_mov_reg_imm (code, ins->dreg, 0);
3178 case OP_LOAD_GOTADDR:
3179 g_assert (ins->dreg == MONO_ARCH_GOT_REG);
3180 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
3183 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3184 x86_mov_reg_membase (code, ins->dreg, ins->inst_basereg, 0xf0f0f0f0, 4);
3186 case OP_X86_PUSH_GOT_ENTRY:
3187 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_right->inst_i1, ins->inst_right->inst_p0);
3188 x86_push_membase (code, ins->inst_basereg, 0xf0f0f0f0);
3191 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3195 * Note: this 'frame destruction' logic is useful for tail calls, too.
3196 * Keep in sync with the code in emit_epilog.
3200 /* FIXME: no tracing support... */
3201 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3202 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3203 /* reset offset to make max_len work */
3204 offset = code - cfg->native_code;
3206 g_assert (!cfg->method->save_lmf);
3208 code = emit_load_volatile_arguments (cfg, code);
3210 if (cfg->used_int_regs & (1 << X86_EBX))
3212 if (cfg->used_int_regs & (1 << X86_EDI))
3214 if (cfg->used_int_regs & (1 << X86_ESI))
3217 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
3219 if (cfg->used_int_regs & (1 << X86_ESI))
3220 x86_pop_reg (code, X86_ESI);
3221 if (cfg->used_int_regs & (1 << X86_EDI))
3222 x86_pop_reg (code, X86_EDI);
3223 if (cfg->used_int_regs & (1 << X86_EBX))
3224 x86_pop_reg (code, X86_EBX);
3226 /* restore ESP/EBP */
3228 offset = code - cfg->native_code;
3229 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3230 x86_jump32 (code, 0);
3232 cfg->disable_aot = TRUE;
3236 MonoCallInst *call = (MonoCallInst*)ins;
3239 ins->flags |= MONO_INST_GC_CALLSITE;
3240 ins->backend.pc_offset = code - cfg->native_code;
3242 /* FIXME: no tracing support... */
3243 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3244 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3245 /* reset offset to make max_len work */
3246 offset = code - cfg->native_code;
3248 g_assert (!cfg->method->save_lmf);
3250 //code = emit_load_volatile_arguments (cfg, code);
3252 /* restore callee saved registers */
3253 for (i = 0; i < X86_NREG; ++i)
3254 if (X86_IS_CALLEE_SAVED_REG (i) && cfg->used_int_regs & (1 << i))
3256 if (cfg->used_int_regs & (1 << X86_ESI)) {
3257 x86_mov_reg_membase (code, X86_ESI, X86_EBP, pos, 4);
3260 if (cfg->used_int_regs & (1 << X86_EDI)) {
3261 x86_mov_reg_membase (code, X86_EDI, X86_EBP, pos, 4);
3264 if (cfg->used_int_regs & (1 << X86_EBX)) {
3265 x86_mov_reg_membase (code, X86_EBX, X86_EBP, pos, 4);
3269 /* Copy arguments on the stack to our argument area */
3270 for (i = 0; i < call->stack_usage - call->stack_align_amount; i += 4) {
3271 x86_mov_reg_membase (code, X86_EAX, X86_ESP, i, 4);
3272 x86_mov_membase_reg (code, X86_EBP, 8 + i, X86_EAX, 4);
3275 /* restore ESP/EBP */
3277 offset = code - cfg->native_code;
3278 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3279 x86_jump32 (code, 0);
3281 ins->flags |= MONO_INST_GC_CALLSITE;
3282 cfg->disable_aot = TRUE;
3286 /* ensure ins->sreg1 is not NULL
3287 * note that cmp DWORD PTR [eax], eax is one byte shorter than
3288 * cmp DWORD PTR [eax], 0
3290 x86_alu_membase_reg (code, X86_CMP, ins->sreg1, 0, ins->sreg1);
3293 int hreg = ins->sreg1 == X86_EAX? X86_ECX: X86_EAX;
3294 x86_push_reg (code, hreg);
3295 x86_lea_membase (code, hreg, X86_EBP, cfg->sig_cookie);
3296 x86_mov_membase_reg (code, ins->sreg1, 0, hreg, 4);
3297 x86_pop_reg (code, hreg);
3306 call = (MonoCallInst*)ins;
3307 if (ins->flags & MONO_INST_HAS_METHOD)
3308 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3310 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3311 ins->flags |= MONO_INST_GC_CALLSITE;
3312 ins->backend.pc_offset = code - cfg->native_code;
3313 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3314 /* a pop is one byte, while an add reg, imm is 3. So if there are 4 or 8
3315 * bytes to pop, we want to use pops. GCC does this (note it won't happen
3316 * for P4 or i686 because gcc will avoid using pop push at all. But we aren't
3317 * smart enough to do that optimization yet
3319 * It turns out that on my P4, doing two pops for 8 bytes on the stack makes
3320 * mcs botstrap slow down. However, doing 1 pop for 4 bytes creates a small,
3321 * (most likely from locality benefits). People with other processors should
3322 * check on theirs to see what happens.
3324 if (call->stack_usage == 4) {
3325 /* we want to use registers that won't get used soon, so use
3326 * ecx, as eax will get allocated first. edx is used by long calls,
3327 * so we can't use that.
3330 x86_pop_reg (code, X86_ECX);
3332 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3335 code = emit_move_return_value (cfg, ins, code);
3341 case OP_VOIDCALL_REG:
3343 call = (MonoCallInst*)ins;
3344 x86_call_reg (code, ins->sreg1);
3345 ins->flags |= MONO_INST_GC_CALLSITE;
3346 ins->backend.pc_offset = code - cfg->native_code;
3347 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3348 if (call->stack_usage == 4)
3349 x86_pop_reg (code, X86_ECX);
3351 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3353 code = emit_move_return_value (cfg, ins, code);
3355 case OP_FCALL_MEMBASE:
3356 case OP_LCALL_MEMBASE:
3357 case OP_VCALL_MEMBASE:
3358 case OP_VCALL2_MEMBASE:
3359 case OP_VOIDCALL_MEMBASE:
3360 case OP_CALL_MEMBASE:
3361 call = (MonoCallInst*)ins;
3363 x86_call_membase (code, ins->sreg1, ins->inst_offset);
3364 ins->flags |= MONO_INST_GC_CALLSITE;
3365 ins->backend.pc_offset = code - cfg->native_code;
3366 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature)) {
3367 if (call->stack_usage == 4)
3368 x86_pop_reg (code, X86_ECX);
3370 x86_alu_reg_imm (code, X86_ADD, X86_ESP, call->stack_usage);
3372 code = emit_move_return_value (cfg, ins, code);
3375 x86_push_reg (code, ins->sreg1);
3377 case OP_X86_PUSH_IMM:
3378 x86_push_imm (code, ins->inst_imm);
3380 case OP_X86_PUSH_MEMBASE:
3381 x86_push_membase (code, ins->inst_basereg, ins->inst_offset);
3383 case OP_X86_PUSH_OBJ:
3384 x86_alu_reg_imm (code, X86_SUB, X86_ESP, ins->inst_imm);
3385 x86_push_reg (code, X86_EDI);
3386 x86_push_reg (code, X86_ESI);
3387 x86_push_reg (code, X86_ECX);
3388 if (ins->inst_offset)
3389 x86_lea_membase (code, X86_ESI, ins->inst_basereg, ins->inst_offset);
3391 x86_mov_reg_reg (code, X86_ESI, ins->inst_basereg, 4);
3392 x86_lea_membase (code, X86_EDI, X86_ESP, 12);
3393 x86_mov_reg_imm (code, X86_ECX, (ins->inst_imm >> 2));
3395 x86_prefix (code, X86_REP_PREFIX);
3397 x86_pop_reg (code, X86_ECX);
3398 x86_pop_reg (code, X86_ESI);
3399 x86_pop_reg (code, X86_EDI);
3402 x86_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3404 case OP_X86_LEA_MEMBASE:
3405 x86_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3408 x86_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3411 /* keep alignment */
3412 x86_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
3413 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_LOCALLOC_ALIGNMENT - 1));
3414 code = mono_emit_stack_alloc (code, ins);
3415 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3417 case OP_LOCALLOC_IMM: {
3418 guint32 size = ins->inst_imm;
3419 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3421 if (ins->flags & MONO_INST_INIT) {
3422 /* FIXME: Optimize this */
3423 x86_mov_reg_imm (code, ins->dreg, size);
3424 ins->sreg1 = ins->dreg;
3426 code = mono_emit_stack_alloc (code, ins);
3427 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3429 x86_alu_reg_imm (code, X86_SUB, X86_ESP, size);
3430 x86_mov_reg_reg (code, ins->dreg, X86_ESP, 4);
3435 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3436 x86_push_reg (code, ins->sreg1);
3437 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3438 (gpointer)"mono_arch_throw_exception");
3439 ins->flags |= MONO_INST_GC_CALLSITE;
3440 ins->backend.pc_offset = code - cfg->native_code;
3444 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3445 x86_push_reg (code, ins->sreg1);
3446 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3447 (gpointer)"mono_arch_rethrow_exception");
3448 ins->flags |= MONO_INST_GC_CALLSITE;
3449 ins->backend.pc_offset = code - cfg->native_code;
3452 case OP_CALL_HANDLER:
3453 x86_alu_reg_imm (code, X86_SUB, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3454 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3455 x86_call_imm (code, 0);
3456 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
3457 x86_alu_reg_imm (code, X86_ADD, X86_ESP, MONO_ARCH_FRAME_ALIGNMENT - 4);
3459 case OP_START_HANDLER: {
3460 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3461 x86_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, X86_ESP, 4);
3464 case OP_ENDFINALLY: {
3465 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3466 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3470 case OP_ENDFILTER: {
3471 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3472 x86_mov_reg_membase (code, X86_ESP, spvar->inst_basereg, spvar->inst_offset, 4);
3473 /* The local allocator will put the result into EAX */
3479 ins->inst_c0 = code - cfg->native_code;
3482 if (ins->inst_target_bb->native_offset) {
3483 x86_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3485 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3486 if ((cfg->opt & MONO_OPT_BRANCH) &&
3487 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3488 x86_jump8 (code, 0);
3490 x86_jump32 (code, 0);
3494 x86_jump_reg (code, ins->sreg1);
3507 x86_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3508 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3510 case OP_COND_EXC_EQ:
3511 case OP_COND_EXC_NE_UN:
3512 case OP_COND_EXC_LT:
3513 case OP_COND_EXC_LT_UN:
3514 case OP_COND_EXC_GT:
3515 case OP_COND_EXC_GT_UN:
3516 case OP_COND_EXC_GE:
3517 case OP_COND_EXC_GE_UN:
3518 case OP_COND_EXC_LE:
3519 case OP_COND_EXC_LE_UN:
3520 case OP_COND_EXC_IEQ:
3521 case OP_COND_EXC_INE_UN:
3522 case OP_COND_EXC_ILT:
3523 case OP_COND_EXC_ILT_UN:
3524 case OP_COND_EXC_IGT:
3525 case OP_COND_EXC_IGT_UN:
3526 case OP_COND_EXC_IGE:
3527 case OP_COND_EXC_IGE_UN:
3528 case OP_COND_EXC_ILE:
3529 case OP_COND_EXC_ILE_UN:
3530 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3532 case OP_COND_EXC_OV:
3533 case OP_COND_EXC_NO:
3535 case OP_COND_EXC_NC:
3536 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ], (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3538 case OP_COND_EXC_IOV:
3539 case OP_COND_EXC_INO:
3540 case OP_COND_EXC_IC:
3541 case OP_COND_EXC_INC:
3542 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ], (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3554 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3562 case OP_CMOV_INE_UN:
3563 case OP_CMOV_IGE_UN:
3564 case OP_CMOV_IGT_UN:
3565 case OP_CMOV_ILE_UN:
3566 case OP_CMOV_ILT_UN:
3567 g_assert (ins->dreg == ins->sreg1);
3568 x86_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3571 /* floating point opcodes */
3573 double d = *(double *)ins->inst_p0;
3575 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3577 } else if (d == 1.0) {
3580 if (cfg->compile_aot) {
3581 guint32 *val = (guint32*)&d;
3582 x86_push_imm (code, val [1]);
3583 x86_push_imm (code, val [0]);
3584 x86_fld_membase (code, X86_ESP, 0, TRUE);
3585 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3588 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R8, ins->inst_p0);
3589 x86_fld (code, NULL, TRUE);
3595 float f = *(float *)ins->inst_p0;
3597 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3599 } else if (f == 1.0) {
3602 if (cfg->compile_aot) {
3603 guint32 val = *(guint32*)&f;
3604 x86_push_imm (code, val);
3605 x86_fld_membase (code, X86_ESP, 0, FALSE);
3606 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3609 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_R4, ins->inst_p0);
3610 x86_fld (code, NULL, FALSE);
3615 case OP_STORER8_MEMBASE_REG:
3616 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3618 case OP_LOADR8_MEMBASE:
3619 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3621 case OP_STORER4_MEMBASE_REG:
3622 x86_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3624 case OP_LOADR4_MEMBASE:
3625 x86_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3627 case OP_ICONV_TO_R4:
3628 x86_push_reg (code, ins->sreg1);
3629 x86_fild_membase (code, X86_ESP, 0, FALSE);
3630 /* Change precision */
3631 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3632 x86_fld_membase (code, X86_ESP, 0, FALSE);
3633 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3635 case OP_ICONV_TO_R8:
3636 x86_push_reg (code, ins->sreg1);
3637 x86_fild_membase (code, X86_ESP, 0, FALSE);
3638 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3640 case OP_ICONV_TO_R_UN:
3641 x86_push_imm (code, 0);
3642 x86_push_reg (code, ins->sreg1);
3643 x86_fild_membase (code, X86_ESP, 0, TRUE);
3644 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3646 case OP_X86_FP_LOAD_I8:
3647 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3649 case OP_X86_FP_LOAD_I4:
3650 x86_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3652 case OP_FCONV_TO_R4:
3653 /* Change precision */
3654 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3655 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3656 x86_fld_membase (code, X86_ESP, 0, FALSE);
3657 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3659 case OP_FCONV_TO_I1:
3660 code = emit_float_to_int (cfg, code, ins->dreg, 1, TRUE);
3662 case OP_FCONV_TO_U1:
3663 code = emit_float_to_int (cfg, code, ins->dreg, 1, FALSE);
3665 case OP_FCONV_TO_I2:
3666 code = emit_float_to_int (cfg, code, ins->dreg, 2, TRUE);
3668 case OP_FCONV_TO_U2:
3669 code = emit_float_to_int (cfg, code, ins->dreg, 2, FALSE);
3671 case OP_FCONV_TO_I4:
3673 code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
3675 case OP_FCONV_TO_I8:
3676 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
3677 x86_fnstcw_membase(code, X86_ESP, 0);
3678 x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
3679 x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
3680 x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
3681 x86_fldcw_membase (code, X86_ESP, 2);
3682 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
3683 x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
3684 x86_pop_reg (code, ins->dreg);
3685 x86_pop_reg (code, ins->backend.reg3);
3686 x86_fldcw_membase (code, X86_ESP, 0);
3687 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
3689 case OP_LCONV_TO_R8_2:
3690 x86_push_reg (code, ins->sreg2);
3691 x86_push_reg (code, ins->sreg1);
3692 x86_fild_membase (code, X86_ESP, 0, TRUE);
3693 /* Change precision */
3694 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3695 x86_fld_membase (code, X86_ESP, 0, TRUE);
3696 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3698 case OP_LCONV_TO_R4_2:
3699 x86_push_reg (code, ins->sreg2);
3700 x86_push_reg (code, ins->sreg1);
3701 x86_fild_membase (code, X86_ESP, 0, TRUE);
3702 /* Change precision */
3703 x86_fst_membase (code, X86_ESP, 0, FALSE, TRUE);
3704 x86_fld_membase (code, X86_ESP, 0, FALSE);
3705 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3707 case OP_LCONV_TO_R_UN_2: {
3708 static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3711 /* load 64bit integer to FP stack */
3712 x86_push_reg (code, ins->sreg2);
3713 x86_push_reg (code, ins->sreg1);
3714 x86_fild_membase (code, X86_ESP, 0, TRUE);
3716 /* test if lreg is negative */
3717 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3718 br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3720 /* add correction constant mn */
3721 if (cfg->compile_aot) {
3722 x86_push_imm (code, (((guint32)mn [9]) << 24) | ((guint32)mn [8] << 16) | ((guint32)mn [7] << 8) | ((guint32)mn [6]));
3723 x86_push_imm (code, (((guint32)mn [5]) << 24) | ((guint32)mn [4] << 16) | ((guint32)mn [3] << 8) | ((guint32)mn [2]));
3724 x86_push_imm (code, (((guint32)mn [1]) << 24) | ((guint32)mn [0] << 16));
3725 x86_fld80_membase (code, X86_ESP, 2);
3726 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 12);
3728 x86_fld80_mem (code, mn);
3730 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3732 x86_patch (br, code);
3734 /* Change precision */
3735 x86_fst_membase (code, X86_ESP, 0, TRUE, TRUE);
3736 x86_fld_membase (code, X86_ESP, 0, TRUE);
3738 x86_alu_reg_imm (code, X86_ADD, X86_ESP, 8);
3742 case OP_LCONV_TO_OVF_I:
3743 case OP_LCONV_TO_OVF_I4_2: {
3744 guint8 *br [3], *label [1];
3748 * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
3750 x86_test_reg_reg (code, ins->sreg1, ins->sreg1);
3752 /* If the low word top bit is set, see if we are negative */
3753 br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
3754 /* We are not negative (no top bit set, check for our top word to be zero */
3755 x86_test_reg_reg (code, ins->sreg2, ins->sreg2);
3756 br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
3759 /* throw exception */
3760 tins = mono_branch_optimize_exception_target (cfg, bb, "OverflowException");
3762 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, tins->inst_true_bb);
3763 if ((cfg->opt & MONO_OPT_BRANCH) && x86_is_imm8 (tins->inst_true_bb->max_offset - cpos))
3764 x86_jump8 (code, 0);
3766 x86_jump32 (code, 0);
3768 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
3769 x86_jump32 (code, 0);
3773 x86_patch (br [0], code);
3774 /* our top bit is set, check that top word is 0xfffffff */
3775 x86_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
3777 x86_patch (br [1], code);
3778 /* nope, emit exception */
3779 br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
3780 x86_patch (br [2], label [0]);
3782 if (ins->dreg != ins->sreg1)
3783 x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
3787 /* Not needed on the fp stack */
3790 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3793 x86_fp_op_reg (code, X86_FSUB, 1, TRUE);
3796 x86_fp_op_reg (code, X86_FMUL, 1, TRUE);
3799 x86_fp_op_reg (code, X86_FDIV, 1, TRUE);
3807 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3812 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3819 * it really doesn't make sense to inline all this code,
3820 * it's here just to show that things may not be as simple
3823 guchar *check_pos, *end_tan, *pop_jump;
3824 x86_push_reg (code, X86_EAX);
3827 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3829 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3830 x86_fstp (code, 0); /* pop the 1.0 */
3832 x86_jump8 (code, 0);
3834 x86_fp_op (code, X86_FADD, 0);
3838 x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
3840 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3843 x86_patch (pop_jump, code);
3844 x86_fstp (code, 0); /* pop the 1.0 */
3845 x86_patch (check_pos, code);
3846 x86_patch (end_tan, code);
3848 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3849 x86_pop_reg (code, X86_EAX);
3856 x86_fp_op_reg (code, X86_FADD, 1, TRUE);
3865 g_assert (cfg->opt & MONO_OPT_CMOV);
3866 g_assert (ins->dreg == ins->sreg1);
3867 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3868 x86_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3871 g_assert (cfg->opt & MONO_OPT_CMOV);
3872 g_assert (ins->dreg == ins->sreg1);
3873 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3874 x86_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3877 g_assert (cfg->opt & MONO_OPT_CMOV);
3878 g_assert (ins->dreg == ins->sreg1);
3879 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3880 x86_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3883 g_assert (cfg->opt & MONO_OPT_CMOV);
3884 g_assert (ins->dreg == ins->sreg1);
3885 x86_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3886 x86_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3892 x86_fxch (code, ins->inst_imm);
3897 x86_push_reg (code, X86_EAX);
3898 /* we need to exchange ST(0) with ST(1) */
3901 /* this requires a loop, because fprem somtimes
3902 * returns a partial remainder */
3904 /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3905 /* x86_fprem1 (code); */
3908 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
3910 x86_branch8 (code, X86_CC_NE, 0, FALSE);
3916 x86_pop_reg (code, X86_EAX);
3920 if (cfg->opt & MONO_OPT_FCMOV) {
3921 x86_fcomip (code, 1);
3925 /* this overwrites EAX */
3926 EMIT_FPCOMPARE(code);
3927 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3930 if (cfg->opt & MONO_OPT_FCMOV) {
3931 /* zeroing the register at the start results in
3932 * shorter and faster code (we can also remove the widening op)
3934 guchar *unordered_check;
3935 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3936 x86_fcomip (code, 1);
3938 unordered_check = code;
3939 x86_branch8 (code, X86_CC_P, 0, FALSE);
3940 x86_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3941 x86_patch (unordered_check, code);
3944 if (ins->dreg != X86_EAX)
3945 x86_push_reg (code, X86_EAX);
3947 EMIT_FPCOMPARE(code);
3948 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3949 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
3950 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3951 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3953 if (ins->dreg != X86_EAX)
3954 x86_pop_reg (code, X86_EAX);
3958 if (cfg->opt & MONO_OPT_FCMOV) {
3959 /* zeroing the register at the start results in
3960 * shorter and faster code (we can also remove the widening op)
3962 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3963 x86_fcomip (code, 1);
3965 if (ins->opcode == OP_FCLT_UN) {
3966 guchar *unordered_check = code;
3967 guchar *jump_to_end;
3968 x86_branch8 (code, X86_CC_P, 0, FALSE);
3969 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3971 x86_jump8 (code, 0);
3972 x86_patch (unordered_check, code);
3973 x86_inc_reg (code, ins->dreg);
3974 x86_patch (jump_to_end, code);
3976 x86_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3980 if (ins->dreg != X86_EAX)
3981 x86_push_reg (code, X86_EAX);
3983 EMIT_FPCOMPARE(code);
3984 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
3985 if (ins->opcode == OP_FCLT_UN) {
3986 guchar *is_not_zero_check, *end_jump;
3987 is_not_zero_check = code;
3988 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3990 x86_jump8 (code, 0);
3991 x86_patch (is_not_zero_check, code);
3992 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
3994 x86_patch (end_jump, code);
3996 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3997 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3999 if (ins->dreg != X86_EAX)
4000 x86_pop_reg (code, X86_EAX);
4004 if (cfg->opt & MONO_OPT_FCMOV) {
4005 /* zeroing the register at the start results in
4006 * shorter and faster code (we can also remove the widening op)
4008 guchar *unordered_check;
4009 x86_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4010 x86_fcomip (code, 1);
4012 if (ins->opcode == OP_FCGT) {
4013 unordered_check = code;
4014 x86_branch8 (code, X86_CC_P, 0, FALSE);
4015 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4016 x86_patch (unordered_check, code);
4018 x86_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4022 if (ins->dreg != X86_EAX)
4023 x86_push_reg (code, X86_EAX);
4025 EMIT_FPCOMPARE(code);
4026 x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
4027 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4028 if (ins->opcode == OP_FCGT_UN) {
4029 guchar *is_not_zero_check, *end_jump;
4030 is_not_zero_check = code;
4031 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4033 x86_jump8 (code, 0);
4034 x86_patch (is_not_zero_check, code);
4035 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4037 x86_patch (end_jump, code);
4039 x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4040 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4042 if (ins->dreg != X86_EAX)
4043 x86_pop_reg (code, X86_EAX);
4046 if (cfg->opt & MONO_OPT_FCMOV) {
4047 guchar *jump = code;
4048 x86_branch8 (code, X86_CC_P, 0, TRUE);
4049 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4050 x86_patch (jump, code);
4053 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
4054 EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4057 /* Branch if C013 != 100 */
4058 if (cfg->opt & MONO_OPT_FCMOV) {
4059 /* branch if !ZF or (PF|CF) */
4060 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4061 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4062 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4065 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4066 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4069 if (cfg->opt & MONO_OPT_FCMOV) {
4070 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4073 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4076 if (cfg->opt & MONO_OPT_FCMOV) {
4077 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4078 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4081 if (ins->opcode == OP_FBLT_UN) {
4082 guchar *is_not_zero_check, *end_jump;
4083 is_not_zero_check = code;
4084 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4086 x86_jump8 (code, 0);
4087 x86_patch (is_not_zero_check, code);
4088 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4090 x86_patch (end_jump, code);
4092 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4096 if (cfg->opt & MONO_OPT_FCMOV) {
4097 if (ins->opcode == OP_FBGT) {
4100 /* skip branch if C1=1 */
4102 x86_branch8 (code, X86_CC_P, 0, FALSE);
4103 /* branch if (C0 | C3) = 1 */
4104 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4105 x86_patch (br1, code);
4107 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4111 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4112 if (ins->opcode == OP_FBGT_UN) {
4113 guchar *is_not_zero_check, *end_jump;
4114 is_not_zero_check = code;
4115 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4117 x86_jump8 (code, 0);
4118 x86_patch (is_not_zero_check, code);
4119 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
4121 x86_patch (end_jump, code);
4123 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4126 /* Branch if C013 == 100 or 001 */
4127 if (cfg->opt & MONO_OPT_FCMOV) {
4130 /* skip branch if C1=1 */
4132 x86_branch8 (code, X86_CC_P, 0, FALSE);
4133 /* branch if (C0 | C3) = 1 */
4134 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4135 x86_patch (br1, code);
4138 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4139 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4140 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
4141 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4144 /* Branch if C013 == 000 */
4145 if (cfg->opt & MONO_OPT_FCMOV) {
4146 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4149 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4152 /* Branch if C013=000 or 100 */
4153 if (cfg->opt & MONO_OPT_FCMOV) {
4156 /* skip branch if C1=1 */
4158 x86_branch8 (code, X86_CC_P, 0, FALSE);
4159 /* branch if C0=0 */
4160 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4161 x86_patch (br1, code);
4164 x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
4165 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
4166 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4169 /* Branch if C013 != 001 */
4170 if (cfg->opt & MONO_OPT_FCMOV) {
4171 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4172 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4175 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4176 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4180 x86_push_reg (code, X86_EAX);
4183 x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
4184 x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
4185 x86_pop_reg (code, X86_EAX);
4187 /* Have to clean up the fp stack before throwing the exception */
4189 x86_branch8 (code, X86_CC_NE, 0, FALSE);
4192 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4194 x86_patch (br1, code);
4198 code = mono_x86_emit_tls_get (code, ins->dreg, ins->inst_offset);
4201 case OP_MEMORY_BARRIER: {
4202 /* x86 only needs barrier for StoreLoad and FullBarrier */
4203 switch (ins->backend.memory_barrier_kind) {
4204 case StoreLoadBarrier:
4206 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4207 x86_prefix (code, X86_LOCK_PREFIX);
4208 x86_alu_membase_imm (code, X86_ADD, X86_ESP, 0, 0);
4213 case OP_ATOMIC_ADD_I4: {
4214 int dreg = ins->dreg;
4216 if (dreg == ins->inst_basereg) {
4217 x86_push_reg (code, ins->sreg2);
4221 if (dreg != ins->sreg2)
4222 x86_mov_reg_reg (code, ins->dreg, ins->sreg2, 4);
4224 x86_prefix (code, X86_LOCK_PREFIX);
4225 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4227 if (dreg != ins->dreg) {
4228 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4229 x86_pop_reg (code, dreg);
4234 case OP_ATOMIC_ADD_NEW_I4: {
4235 int dreg = ins->dreg;
4237 /* hack: limit in regalloc, dreg != sreg1 && dreg != sreg2 */
4238 if (ins->sreg2 == dreg) {
4239 if (dreg == X86_EBX) {
4241 if (ins->inst_basereg == X86_EDI)
4245 if (ins->inst_basereg == X86_EBX)
4248 } else if (ins->inst_basereg == dreg) {
4249 if (dreg == X86_EBX) {
4251 if (ins->sreg2 == X86_EDI)
4255 if (ins->sreg2 == X86_EBX)
4260 if (dreg != ins->dreg) {
4261 x86_push_reg (code, dreg);
4264 x86_mov_reg_reg (code, dreg, ins->sreg2, 4);
4265 x86_prefix (code, X86_LOCK_PREFIX);
4266 x86_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, 4);
4267 /* dreg contains the old value, add with sreg2 value */
4268 x86_alu_reg_reg (code, X86_ADD, dreg, ins->sreg2);
4270 if (ins->dreg != dreg) {
4271 x86_mov_reg_reg (code, ins->dreg, dreg, 4);
4272 x86_pop_reg (code, dreg);
4277 case OP_ATOMIC_EXCHANGE_I4: {
4279 int sreg2 = ins->sreg2;
4280 int breg = ins->inst_basereg;
4282 /* cmpxchg uses eax as comperand, need to make sure we can use it
4283 * hack to overcome limits in x86 reg allocator
4284 * (req: dreg == eax and sreg2 != eax and breg != eax)
4286 g_assert (ins->dreg == X86_EAX);
4288 /* We need the EAX reg for the cmpxchg */
4289 if (ins->sreg2 == X86_EAX) {
4290 sreg2 = (breg == X86_EDX) ? X86_EBX : X86_EDX;
4291 x86_push_reg (code, sreg2);
4292 x86_mov_reg_reg (code, sreg2, X86_EAX, 4);
4295 if (breg == X86_EAX) {
4296 breg = (sreg2 == X86_ESI) ? X86_EDI : X86_ESI;
4297 x86_push_reg (code, breg);
4298 x86_mov_reg_reg (code, breg, X86_EAX, 4);
4301 x86_mov_reg_membase (code, X86_EAX, breg, ins->inst_offset, 4);
4303 br [0] = code; x86_prefix (code, X86_LOCK_PREFIX);
4304 x86_cmpxchg_membase_reg (code, breg, ins->inst_offset, sreg2);
4305 br [1] = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4306 x86_patch (br [1], br [0]);
4308 if (breg != ins->inst_basereg)
4309 x86_pop_reg (code, breg);
4311 if (ins->sreg2 != sreg2)
4312 x86_pop_reg (code, sreg2);
4316 case OP_ATOMIC_CAS_I4: {
4317 g_assert (ins->dreg == X86_EAX);
4318 g_assert (ins->sreg3 == X86_EAX);
4319 g_assert (ins->sreg1 != X86_EAX);
4320 g_assert (ins->sreg1 != ins->sreg2);
4322 x86_prefix (code, X86_LOCK_PREFIX);
4323 x86_cmpxchg_membase_reg (code, ins->sreg1, ins->inst_offset, ins->sreg2);
4326 case OP_CARD_TABLE_WBARRIER: {
4327 int ptr = ins->sreg1;
4328 int value = ins->sreg2;
4330 int nursery_shift, card_table_shift;
4331 gpointer card_table_mask;
4332 size_t nursery_size;
4333 gulong card_table = (gulong)mono_gc_get_card_table (&card_table_shift, &card_table_mask);
4334 gulong nursery_start = (gulong)mono_gc_get_nursery (&nursery_shift, &nursery_size);
4335 gboolean card_table_nursery_check = mono_gc_card_table_nursery_check ();
4338 * We need one register we can clobber, we choose EDX and make sreg1
4339 * fixed EAX to work around limitations in the local register allocator.
4340 * sreg2 might get allocated to EDX, but that is not a problem since
4341 * we use it before clobbering EDX.
4343 g_assert (ins->sreg1 == X86_EAX);
4346 * This is the code we produce:
4349 * edx >>= nursery_shift
4350 * cmp edx, (nursery_start >> nursery_shift)
4353 * edx >>= card_table_shift
4354 * card_table[edx] = 1
4358 if (card_table_nursery_check) {
4359 if (value != X86_EDX)
4360 x86_mov_reg_reg (code, X86_EDX, value, 4);
4361 x86_shift_reg_imm (code, X86_SHR, X86_EDX, nursery_shift);
4362 x86_alu_reg_imm (code, X86_CMP, X86_EDX, nursery_start >> nursery_shift);
4363 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
4365 x86_mov_reg_reg (code, X86_EDX, ptr, 4);
4366 x86_shift_reg_imm (code, X86_SHR, X86_EDX, card_table_shift);
4367 if (card_table_mask)
4368 x86_alu_reg_imm (code, X86_AND, X86_EDX, (int)card_table_mask);
4369 x86_mov_membase_imm (code, X86_EDX, card_table, 1, 1);
4370 if (card_table_nursery_check)
4371 x86_patch (br, code);
4374 #ifdef MONO_ARCH_SIMD_INTRINSICS
4376 x86_sse_alu_ps_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4379 x86_sse_alu_ps_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4382 x86_sse_alu_ps_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4385 x86_sse_alu_ps_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4388 x86_sse_alu_ps_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4391 x86_sse_alu_ps_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4394 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4395 x86_sse_alu_ps_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4398 x86_sse_alu_ps_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4401 x86_sse_alu_ps_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4404 x86_sse_alu_ps_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4407 x86_sse_alu_ps_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4410 x86_sse_alu_ps_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4413 x86_sse_alu_ps_reg_reg (code, X86_SSE_RSQRT, ins->dreg, ins->sreg1);
4416 x86_sse_alu_ps_reg_reg (code, X86_SSE_RCP, ins->dreg, ins->sreg1);
4419 x86_sse_alu_sd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4422 x86_sse_alu_sd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4425 x86_sse_alu_sd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4428 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSHDUP, ins->dreg, ins->sreg1);
4431 x86_sse_alu_ss_reg_reg (code, X86_SSE_MOVSLDUP, ins->dreg, ins->sreg1);
4434 case OP_PSHUFLEW_HIGH:
4435 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4436 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 1);
4438 case OP_PSHUFLEW_LOW:
4439 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4440 x86_pshufw_reg_reg (code, ins->dreg, ins->sreg1, ins->inst_c0, 0);
4443 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4444 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->sreg1, ins->inst_c0);
4447 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4448 x86_sse_alu_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4451 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
4452 x86_sse_alu_pd_reg_reg_imm8 (code, X86_SSE_SHUFP, ins->sreg1, ins->sreg2, ins->inst_c0);
4456 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADD, ins->sreg1, ins->sreg2);
4459 x86_sse_alu_pd_reg_reg (code, X86_SSE_DIV, ins->sreg1, ins->sreg2);
4462 x86_sse_alu_pd_reg_reg (code, X86_SSE_MUL, ins->sreg1, ins->sreg2);
4465 x86_sse_alu_pd_reg_reg (code, X86_SSE_SUB, ins->sreg1, ins->sreg2);
4468 x86_sse_alu_pd_reg_reg (code, X86_SSE_MAX, ins->sreg1, ins->sreg2);
4471 x86_sse_alu_pd_reg_reg (code, X86_SSE_MIN, ins->sreg1, ins->sreg2);
4474 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4475 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_COMP, ins->sreg1, ins->sreg2, ins->inst_c0);
4478 x86_sse_alu_pd_reg_reg (code, X86_SSE_AND, ins->sreg1, ins->sreg2);
4481 x86_sse_alu_pd_reg_reg (code, X86_SSE_ANDN, ins->sreg1, ins->sreg2);
4484 x86_sse_alu_pd_reg_reg (code, X86_SSE_OR, ins->sreg1, ins->sreg2);
4487 x86_sse_alu_pd_reg_reg (code, X86_SSE_XOR, ins->sreg1, ins->sreg2);
4490 x86_sse_alu_pd_reg_reg (code, X86_SSE_SQRT, ins->dreg, ins->sreg1);
4493 x86_sse_alu_pd_reg_reg (code, X86_SSE_ADDSUB, ins->sreg1, ins->sreg2);
4496 x86_sse_alu_pd_reg_reg (code, X86_SSE_HADD, ins->sreg1, ins->sreg2);
4499 x86_sse_alu_pd_reg_reg (code, X86_SSE_HSUB, ins->sreg1, ins->sreg2);
4502 x86_sse_alu_sd_reg_reg (code, X86_SSE_MOVDDUP, ins->dreg, ins->sreg1);
4505 case OP_EXTRACT_MASK:
4506 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMOVMSKB, ins->dreg, ins->sreg1);
4510 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAND, ins->sreg1, ins->sreg2);
4513 x86_sse_alu_pd_reg_reg (code, X86_SSE_POR, ins->sreg1, ins->sreg2);
4516 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->sreg1, ins->sreg2);
4520 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDB, ins->sreg1, ins->sreg2);
4523 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDW, ins->sreg1, ins->sreg2);
4526 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDD, ins->sreg1, ins->sreg2);
4529 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDQ, ins->sreg1, ins->sreg2);
4533 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBB, ins->sreg1, ins->sreg2);
4536 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBW, ins->sreg1, ins->sreg2);
4539 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBD, ins->sreg1, ins->sreg2);
4542 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBQ, ins->sreg1, ins->sreg2);
4546 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXUB, ins->sreg1, ins->sreg2);
4549 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUW, ins->sreg1, ins->sreg2);
4552 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXUD, ins->sreg1, ins->sreg2);
4556 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSB, ins->sreg1, ins->sreg2);
4559 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMAXSW, ins->sreg1, ins->sreg2);
4562 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMAXSD, ins->sreg1, ins->sreg2);
4566 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGB, ins->sreg1, ins->sreg2);
4569 x86_sse_alu_pd_reg_reg (code, X86_SSE_PAVGW, ins->sreg1, ins->sreg2);
4573 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINUB, ins->sreg1, ins->sreg2);
4576 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUW, ins->sreg1, ins->sreg2);
4579 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINUD, ins->sreg1, ins->sreg2);
4583 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSB, ins->sreg1, ins->sreg2);
4586 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMINSW, ins->sreg1, ins->sreg2);
4589 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMINSD, ins->sreg1, ins->sreg2);
4593 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQB, ins->sreg1, ins->sreg2);
4596 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQW, ins->sreg1, ins->sreg2);
4599 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPEQD, ins->sreg1, ins->sreg2);
4602 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPEQQ, ins->sreg1, ins->sreg2);
4606 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTB, ins->sreg1, ins->sreg2);
4609 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTW, ins->sreg1, ins->sreg2);
4612 x86_sse_alu_pd_reg_reg (code, X86_SSE_PCMPGTD, ins->sreg1, ins->sreg2);
4615 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PCMPGTQ, ins->sreg1, ins->sreg2);
4618 case OP_PSUM_ABS_DIFF:
4619 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSADBW, ins->sreg1, ins->sreg2);
4622 case OP_UNPACK_LOWB:
4623 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLBW, ins->sreg1, ins->sreg2);
4625 case OP_UNPACK_LOWW:
4626 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLWD, ins->sreg1, ins->sreg2);
4628 case OP_UNPACK_LOWD:
4629 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLDQ, ins->sreg1, ins->sreg2);
4631 case OP_UNPACK_LOWQ:
4632 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKLQDQ, ins->sreg1, ins->sreg2);
4634 case OP_UNPACK_LOWPS:
4635 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4637 case OP_UNPACK_LOWPD:
4638 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKL, ins->sreg1, ins->sreg2);
4641 case OP_UNPACK_HIGHB:
4642 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHBW, ins->sreg1, ins->sreg2);
4644 case OP_UNPACK_HIGHW:
4645 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHWD, ins->sreg1, ins->sreg2);
4647 case OP_UNPACK_HIGHD:
4648 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHDQ, ins->sreg1, ins->sreg2);
4650 case OP_UNPACK_HIGHQ:
4651 x86_sse_alu_pd_reg_reg (code, X86_SSE_PUNPCKHQDQ, ins->sreg1, ins->sreg2);
4653 case OP_UNPACK_HIGHPS:
4654 x86_sse_alu_ps_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4656 case OP_UNPACK_HIGHPD:
4657 x86_sse_alu_pd_reg_reg (code, X86_SSE_UNPCKH, ins->sreg1, ins->sreg2);
4661 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSWB, ins->sreg1, ins->sreg2);
4664 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKSSDW, ins->sreg1, ins->sreg2);
4667 x86_sse_alu_pd_reg_reg (code, X86_SSE_PACKUSWB, ins->sreg1, ins->sreg2);
4670 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PACKUSDW, ins->sreg1, ins->sreg2);
4673 case OP_PADDB_SAT_UN:
4674 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSB, ins->sreg1, ins->sreg2);
4676 case OP_PSUBB_SAT_UN:
4677 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSB, ins->sreg1, ins->sreg2);
4679 case OP_PADDW_SAT_UN:
4680 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDUSW, ins->sreg1, ins->sreg2);
4682 case OP_PSUBW_SAT_UN:
4683 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBUSW, ins->sreg1, ins->sreg2);
4687 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSB, ins->sreg1, ins->sreg2);
4690 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSB, ins->sreg1, ins->sreg2);
4693 x86_sse_alu_pd_reg_reg (code, X86_SSE_PADDSW, ins->sreg1, ins->sreg2);
4696 x86_sse_alu_pd_reg_reg (code, X86_SSE_PSUBSW, ins->sreg1, ins->sreg2);
4700 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULLW, ins->sreg1, ins->sreg2);
4703 x86_sse_alu_sse41_reg_reg (code, X86_SSE_PMULLD, ins->sreg1, ins->sreg2);
4706 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULUDQ, ins->sreg1, ins->sreg2);
4708 case OP_PMULW_HIGH_UN:
4709 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHUW, ins->sreg1, ins->sreg2);
4712 x86_sse_alu_pd_reg_reg (code, X86_SSE_PMULHW, ins->sreg1, ins->sreg2);
4716 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4719 x86_sse_shift_reg_reg (code, X86_SSE_PSRLW_REG, ins->dreg, ins->sreg2);
4723 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4726 x86_sse_shift_reg_reg (code, X86_SSE_PSRAW_REG, ins->dreg, ins->sreg2);
4730 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTW, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4733 x86_sse_shift_reg_reg (code, X86_SSE_PSLLW_REG, ins->dreg, ins->sreg2);
4737 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4740 x86_sse_shift_reg_reg (code, X86_SSE_PSRLD_REG, ins->dreg, ins->sreg2);
4744 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SAR, ins->dreg, ins->inst_imm);
4747 x86_sse_shift_reg_reg (code, X86_SSE_PSRAD_REG, ins->dreg, ins->sreg2);
4751 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTD, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4754 x86_sse_shift_reg_reg (code, X86_SSE_PSLLD_REG, ins->dreg, ins->sreg2);
4758 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHR, ins->dreg, ins->inst_imm);
4761 x86_sse_shift_reg_reg (code, X86_SSE_PSRLQ_REG, ins->dreg, ins->sreg2);
4765 x86_sse_shift_reg_imm (code, X86_SSE_PSHIFTQ, X86_SSE_SHL, ins->dreg, ins->inst_imm);
4768 x86_sse_shift_reg_reg (code, X86_SSE_PSLLQ_REG, ins->dreg, ins->sreg2);
4772 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4775 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4779 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4781 x86_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4782 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4786 x86_movd_reg_xreg (code, ins->dreg, ins->sreg1);
4788 x86_shift_reg_imm (code, X86_SHR, ins->dreg, 16);
4789 x86_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE);
4793 x86_sse_alu_pd_membase_reg (code, X86_SSE_MOVHPD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4795 x86_sse_alu_sd_membase_reg (code, X86_SSE_MOVSD_MEMBASE_REG, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1);
4796 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE);
4800 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->sreg1, ins->sreg2, ins->inst_c0);
4802 case OP_EXTRACTX_U2:
4803 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PEXTRW, ins->dreg, ins->sreg1, ins->inst_c0);
4805 case OP_INSERTX_U1_SLOW:
4806 /*sreg1 is the extracted ireg (scratch)
4807 /sreg2 is the to be inserted ireg (scratch)
4808 /dreg is the xreg to receive the value*/
4810 /*clear the bits from the extracted word*/
4811 x86_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4812 /*shift the value to insert if needed*/
4813 if (ins->inst_c0 & 1)
4814 x86_shift_reg_imm (code, X86_SHL, ins->sreg2, 8);
4815 /*join them together*/
4816 x86_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4817 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4819 case OP_INSERTX_I4_SLOW:
4820 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4821 x86_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4822 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4825 case OP_INSERTX_R4_SLOW:
4826 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4827 /*TODO if inst_c0 == 0 use movss*/
4828 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 0, ins->inst_c0 * 2);
4829 x86_sse_alu_pd_reg_membase_imm (code, X86_SSE_PINSRW, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset + 2, ins->inst_c0 * 2 + 1);
4831 case OP_INSERTX_R8_SLOW:
4832 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4833 if (cfg->verbose_level)
4834 printf ("CONVERTING a OP_INSERTX_R8_SLOW %d offset %x\n", ins->inst_c0, offset);
4836 x86_sse_alu_pd_reg_membase (code, X86_SSE_MOVHPD_REG_MEMBASE, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4838 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4841 case OP_STOREX_MEMBASE_REG:
4842 case OP_STOREX_MEMBASE:
4843 x86_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4845 case OP_LOADX_MEMBASE:
4846 x86_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4848 case OP_LOADX_ALIGNED_MEMBASE:
4849 x86_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
4851 case OP_STOREX_ALIGNED_MEMBASE_REG:
4852 x86_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
4854 case OP_STOREX_NTA_MEMBASE_REG:
4855 x86_sse_alu_reg_membase (code, X86_SSE_MOVNTPS, ins->dreg, ins->sreg1, ins->inst_offset);
4857 case OP_PREFETCH_MEMBASE:
4858 x86_sse_alu_reg_membase (code, X86_SSE_PREFETCH, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
4862 /*FIXME the peephole pass should have killed this*/
4863 if (ins->dreg != ins->sreg1)
4864 x86_movaps_reg_reg (code, ins->dreg, ins->sreg1);
4867 x86_sse_alu_pd_reg_reg (code, X86_SSE_PXOR, ins->dreg, ins->dreg);
4869 case OP_ICONV_TO_R8_RAW:
4870 x86_mov_membase_reg (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, ins->sreg1, 4);
4871 x86_fld_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE);
4874 case OP_FCONV_TO_R8_X:
4875 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4876 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4879 case OP_XCONV_R8_TO_I4:
4880 x86_cvttsd2si (code, ins->dreg, ins->sreg1);
4881 switch (ins->backend.source_opcode) {
4882 case OP_FCONV_TO_I1:
4883 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
4885 case OP_FCONV_TO_U1:
4886 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4888 case OP_FCONV_TO_I2:
4889 x86_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
4891 case OP_FCONV_TO_U2:
4892 x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
4898 /*FIXME this causes a partial register stall, maybe it would not be that bad to use shift + mask + or*/
4899 /*The +4 is to get a mov ?h, ?l over the same reg.*/
4900 x86_mov_reg_reg (code, ins->dreg + 4, ins->dreg, 1);
4901 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4902 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4903 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4906 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 0);
4907 x86_sse_alu_pd_reg_reg_imm (code, X86_SSE_PINSRW, ins->dreg, ins->sreg1, 1);
4908 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4911 x86_movd_xreg_reg (code, ins->dreg, ins->sreg1);
4912 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4915 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, FALSE, TRUE);
4916 x86_movd_xreg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4917 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0);
4920 x86_fst_membase (code, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset, TRUE, TRUE);
4921 x86_movsd_reg_membase (code, ins->dreg, ins->backend.spill_var->inst_basereg, ins->backend.spill_var->inst_offset);
4922 x86_sse_shift_reg_imm (code, X86_SSE_PSHUFD, ins->dreg, ins->dreg, 0x44);
4926 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTDQ2PD, ins->dreg, ins->sreg1);
4929 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTDQ2PS, ins->dreg, ins->sreg1);
4932 x86_sse_alu_sd_reg_reg (code, X86_SSE_CVTPD2DQ, ins->dreg, ins->sreg1);
4935 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPD2PS, ins->dreg, ins->sreg1);
4938 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTPS2DQ, ins->dreg, ins->sreg1);
4941 x86_sse_alu_ps_reg_reg (code, X86_SSE_CVTPS2PD, ins->dreg, ins->sreg1);
4944 x86_sse_alu_pd_reg_reg (code, X86_SSE_CVTTPD2DQ, ins->dreg, ins->sreg1);
4947 x86_sse_alu_ss_reg_reg (code, X86_SSE_CVTTPS2DQ, ins->dreg, ins->sreg1);
4951 case OP_LIVERANGE_START: {
4952 if (cfg->verbose_level > 1)
4953 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4954 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
4957 case OP_LIVERANGE_END: {
4958 if (cfg->verbose_level > 1)
4959 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
4960 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
4963 case OP_NACL_GC_SAFE_POINT: {
4964 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
4965 if (cfg->compile_aot)
4966 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4970 x86_test_mem_imm8 (code, (gpointer)&__nacl_thread_suspension_needed, 0xFFFFFFFF);
4971 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
4972 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc);
4973 x86_patch (br[0], code);
4978 case OP_GC_LIVENESS_DEF:
4979 case OP_GC_LIVENESS_USE:
4980 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
4981 ins->backend.pc_offset = code - cfg->native_code;
4983 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
4984 ins->backend.pc_offset = code - cfg->native_code;
4985 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
4988 g_warning ("unknown opcode %s\n", mono_inst_name (ins->opcode));
4989 g_assert_not_reached ();
4992 if (G_UNLIKELY ((code - cfg->native_code - offset) > max_len)) {
4993 #ifndef __native_client_codegen__
4994 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %d)",
4995 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4996 g_assert_not_reached ();
4997 #endif /* __native_client_codegen__ */
5003 cfg->code_len = code - cfg->native_code;
5006 #endif /* DISABLE_JIT */
5009 mono_arch_register_lowlevel_calls (void)
5014 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
5016 MonoJumpInfo *patch_info;
5017 gboolean compile_aot = !run_cctors;
5019 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5020 unsigned char *ip = patch_info->ip.i + code;
5021 const unsigned char *target;
5023 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5026 switch (patch_info->type) {
5027 case MONO_PATCH_INFO_BB:
5028 case MONO_PATCH_INFO_LABEL:
5031 /* No need to patch these */
5036 switch (patch_info->type) {
5037 case MONO_PATCH_INFO_IP:
5038 *((gconstpointer *)(ip)) = target;
5040 case MONO_PATCH_INFO_CLASS_INIT: {
5042 /* Might already been changed to a nop */
5043 x86_call_code (code, 0);
5044 x86_patch (ip, target);
5047 case MONO_PATCH_INFO_ABS:
5048 case MONO_PATCH_INFO_METHOD:
5049 case MONO_PATCH_INFO_METHOD_JUMP:
5050 case MONO_PATCH_INFO_INTERNAL_METHOD:
5051 case MONO_PATCH_INFO_BB:
5052 case MONO_PATCH_INFO_LABEL:
5053 case MONO_PATCH_INFO_RGCTX_FETCH:
5054 case MONO_PATCH_INFO_GENERIC_CLASS_INIT:
5055 case MONO_PATCH_INFO_MONITOR_ENTER:
5056 case MONO_PATCH_INFO_MONITOR_EXIT:
5057 case MONO_PATCH_INFO_JIT_ICALL_ADDR:
5058 #if defined(__native_client_codegen__) && defined(__native_client__)
5059 if (nacl_is_code_address (code)) {
5060 /* For tail calls, code is patched after being installed */
5061 /* but not through the normal "patch callsite" method. */
5062 unsigned char buf[kNaClAlignment];
5063 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
5064 unsigned char *_target = target;
5066 /* All patch targets modified in x86_patch */
5067 /* are IP relative. */
5068 _target = _target + (uintptr_t)buf - (uintptr_t)aligned_code;
5069 memcpy (buf, aligned_code, kNaClAlignment);
5070 /* Patch a temp buffer of bundle size, */
5071 /* then install to actual location. */
5072 x86_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), _target);
5073 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
5074 g_assert (ret == 0);
5077 x86_patch (ip, target);
5080 x86_patch (ip, target);
5083 case MONO_PATCH_INFO_NONE:
5085 case MONO_PATCH_INFO_R4:
5086 case MONO_PATCH_INFO_R8: {
5087 guint32 offset = mono_arch_get_patch_offset (ip);
5088 *((gconstpointer *)(ip + offset)) = target;
5092 guint32 offset = mono_arch_get_patch_offset (ip);
5093 #if !defined(__native_client__)
5094 *((gconstpointer *)(ip + offset)) = target;
5096 *((gconstpointer *)(ip + offset)) = nacl_modify_patch_target (target);
5104 static G_GNUC_UNUSED void
5105 stack_unaligned (MonoMethod *m, gpointer caller)
5107 printf ("%s\n", mono_method_full_name (m, TRUE));
5108 g_assert_not_reached ();
5112 mono_arch_emit_prolog (MonoCompile *cfg)
5114 MonoMethod *method = cfg->method;
5116 MonoMethodSignature *sig;
5118 int alloc_size, pos, max_offset, i, cfa_offset;
5120 gboolean need_stack_frame;
5121 #ifdef __native_client_codegen__
5122 guint alignment_check;
5125 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
5127 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5128 cfg->code_size += 512;
5130 #if defined(__default_codegen__)
5131 code = cfg->native_code = g_malloc (cfg->code_size);
5132 #elif defined(__native_client_codegen__)
5133 /* native_code_alloc is not 32-byte aligned, native_code is. */
5134 cfg->code_size = NACL_BUNDLE_ALIGN_UP (cfg->code_size);
5135 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
5137 /* Align native_code to next nearest kNaclAlignment byte. */
5138 cfg->native_code = (guint)cfg->native_code_alloc + kNaClAlignment;
5139 cfg->native_code = (guint)cfg->native_code & ~kNaClAlignmentMask;
5141 code = cfg->native_code;
5143 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
5144 g_assert(alignment_check == 0);
5151 /* Check that the stack is aligned on osx */
5152 x86_mov_reg_reg (code, X86_EAX, X86_ESP, sizeof (mgreg_t));
5153 x86_alu_reg_imm (code, X86_AND, X86_EAX, 15);
5154 x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0xc);
5156 x86_branch_disp (code, X86_CC_Z, 0, FALSE);
5157 x86_push_membase (code, X86_ESP, 0);
5158 x86_push_imm (code, cfg->method);
5159 x86_mov_reg_imm (code, X86_EAX, stack_unaligned);
5160 x86_call_reg (code, X86_EAX);
5161 x86_patch (br [0], code);
5165 /* Offset between RSP and the CFA */
5169 cfa_offset = sizeof (gpointer);
5170 mono_emit_unwind_op_def_cfa (cfg, code, X86_ESP, sizeof (gpointer));
5171 // IP saved at CFA - 4
5172 /* There is no IP reg on x86 */
5173 mono_emit_unwind_op_offset (cfg, code, X86_NREG, -cfa_offset);
5174 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5176 need_stack_frame = needs_stack_frame (cfg);
5178 if (need_stack_frame) {
5179 x86_push_reg (code, X86_EBP);
5180 cfa_offset += sizeof (gpointer);
5181 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5182 mono_emit_unwind_op_offset (cfg, code, X86_EBP, - cfa_offset);
5183 x86_mov_reg_reg (code, X86_EBP, X86_ESP, 4);
5184 mono_emit_unwind_op_def_cfa_reg (cfg, code, X86_EBP);
5185 /* These are handled automatically by the stack marking code */
5186 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5188 cfg->frame_reg = X86_ESP;
5191 alloc_size = cfg->stack_offset;
5194 if (method->save_lmf) {
5195 pos += sizeof (MonoLMF);
5197 /* save the current IP */
5198 if (cfg->compile_aot) {
5199 /* This pushes the current ip */
5200 x86_call_imm (code, 0);
5202 mono_add_patch_info (cfg, code + 1 - cfg->native_code, MONO_PATCH_INFO_IP, NULL);
5203 x86_push_imm_template (code);
5205 cfa_offset += sizeof (gpointer);
5206 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5208 /* save all caller saved regs */
5209 x86_push_reg (code, X86_EBP);
5210 cfa_offset += sizeof (gpointer);
5211 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5212 x86_push_reg (code, X86_ESI);
5213 cfa_offset += sizeof (gpointer);
5214 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5215 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5216 x86_push_reg (code, X86_EDI);
5217 cfa_offset += sizeof (gpointer);
5218 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5219 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5220 x86_push_reg (code, X86_EBX);
5221 cfa_offset += sizeof (gpointer);
5222 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5223 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5225 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5227 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5228 * through the mono_lmf_addr TLS variable.
5230 /* %eax = previous_lmf */
5231 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_tls_offset);
5232 /* skip esp + method_info + lmf */
5233 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 12);
5235 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5236 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 4, SLOT_NOREF);
5237 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset + 8, SLOT_NOREF);
5238 /* push previous_lmf */
5239 x86_push_reg (code, X86_EAX);
5241 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5243 code = mono_x86_emit_tls_set (code, X86_ESP, lmf_tls_offset);
5245 /* get the address of lmf for the current thread */
5247 * This is performance critical so we try to use some tricks to make
5251 if (lmf_addr_tls_offset != -1) {
5252 /* Load lmf quicky using the GS register */
5253 code = mono_x86_emit_tls_get (code, X86_EAX, lmf_addr_tls_offset);
5255 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5256 /* FIXME: Add a separate key for LMF to avoid this */
5257 x86_alu_reg_imm (code, X86_ADD, X86_EAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5260 if (cfg->compile_aot)
5261 code = mono_arch_emit_load_got_addr (cfg->native_code, code, cfg, NULL);
5262 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_get_lmf_addr");
5265 /* Skip esp + method info */
5266 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
5269 x86_push_reg (code, X86_EAX);
5270 /* push *lfm (previous_lmf) */
5271 x86_push_membase (code, X86_EAX, 0);
5273 x86_mov_membase_reg (code, X86_EAX, 0, X86_ESP, 4);
5277 if (cfg->used_int_regs & (1 << X86_EBX)) {
5278 x86_push_reg (code, X86_EBX);
5280 cfa_offset += sizeof (gpointer);
5281 mono_emit_unwind_op_offset (cfg, code, X86_EBX, - cfa_offset);
5282 /* These are handled automatically by the stack marking code */
5283 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5286 if (cfg->used_int_regs & (1 << X86_EDI)) {
5287 x86_push_reg (code, X86_EDI);
5289 cfa_offset += sizeof (gpointer);
5290 mono_emit_unwind_op_offset (cfg, code, X86_EDI, - cfa_offset);
5291 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5294 if (cfg->used_int_regs & (1 << X86_ESI)) {
5295 x86_push_reg (code, X86_ESI);
5297 cfa_offset += sizeof (gpointer);
5298 mono_emit_unwind_op_offset (cfg, code, X86_ESI, - cfa_offset);
5299 mini_gc_set_slot_type_from_cfa (cfg, - cfa_offset, SLOT_NOREF);
5305 /* the original alloc_size is already aligned: there is %ebp and retip pushed, so realign */
5306 if (mono_do_x86_stack_align && need_stack_frame) {
5307 int tot = alloc_size + pos + 4; /* ret ip */
5308 if (need_stack_frame)
5310 tot &= MONO_ARCH_FRAME_ALIGNMENT - 1;
5312 alloc_size += MONO_ARCH_FRAME_ALIGNMENT - tot;
5313 for (i = 0; i < MONO_ARCH_FRAME_ALIGNMENT - tot; i += sizeof (mgreg_t))
5314 mini_gc_set_slot_type_from_fp (cfg, - (alloc_size + pos - i), SLOT_NOREF);
5318 cfg->arch.sp_fp_offset = alloc_size + pos;
5321 /* See mono_emit_stack_alloc */
5322 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5323 guint32 remaining_size = alloc_size;
5324 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5325 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 8; /*8 is the max size of x86_alu_reg_imm + x86_test_membase_reg*/
5326 guint32 offset = code - cfg->native_code;
5327 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5328 while (required_code_size >= (cfg->code_size - offset))
5329 cfg->code_size *= 2;
5330 cfg->native_code = mono_realloc_native_code(cfg);
5331 code = cfg->native_code + offset;
5332 cfg->stat_code_reallocs++;
5334 while (remaining_size >= 0x1000) {
5335 x86_alu_reg_imm (code, X86_SUB, X86_ESP, 0x1000);
5336 x86_test_membase_reg (code, X86_ESP, 0, X86_ESP);
5337 remaining_size -= 0x1000;
5340 x86_alu_reg_imm (code, X86_SUB, X86_ESP, remaining_size);
5342 x86_alu_reg_imm (code, X86_SUB, X86_ESP, alloc_size);
5345 g_assert (need_stack_frame);
5348 if (cfg->method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED ||
5349 cfg->method->wrapper_type == MONO_WRAPPER_RUNTIME_INVOKE) {
5350 x86_alu_reg_imm (code, X86_AND, X86_ESP, -MONO_ARCH_FRAME_ALIGNMENT);
5353 #if DEBUG_STACK_ALIGNMENT
5354 /* check the stack is aligned */
5355 if (need_stack_frame && method->wrapper_type == MONO_WRAPPER_NONE) {
5356 x86_mov_reg_reg (code, X86_ECX, X86_ESP, 4);
5357 x86_alu_reg_imm (code, X86_AND, X86_ECX, MONO_ARCH_FRAME_ALIGNMENT - 1);
5358 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5359 x86_branch_disp (code, X86_CC_EQ, 3, FALSE);
5360 x86_breakpoint (code);
5364 /* compute max_offset in order to use short forward jumps */
5366 if (cfg->opt & MONO_OPT_BRANCH) {
5367 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5369 bb->max_offset = max_offset;
5371 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5373 /* max alignment for loops */
5374 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5375 max_offset += LOOP_ALIGNMENT;
5376 #ifdef __native_client_codegen__
5377 /* max alignment for native client */
5378 if (bb->flags & BB_INDIRECT_JUMP_TARGET || bb->flags & BB_EXCEPTION_HANDLER)
5379 max_offset += kNaClAlignment;
5381 MONO_BB_FOR_EACH_INS (bb, ins) {
5382 if (ins->opcode == OP_LABEL)
5383 ins->inst_c1 = max_offset;
5384 #ifdef __native_client_codegen__
5385 switch (ins->opcode)
5397 case OP_VOIDCALL_REG:
5399 case OP_FCALL_MEMBASE:
5400 case OP_LCALL_MEMBASE:
5401 case OP_VCALL_MEMBASE:
5402 case OP_VCALL2_MEMBASE:
5403 case OP_VOIDCALL_MEMBASE:
5404 case OP_CALL_MEMBASE:
5405 max_offset += kNaClAlignment;
5408 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN] - 1;
5411 #endif /* __native_client_codegen__ */
5412 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5417 /* store runtime generic context */
5418 if (cfg->rgctx_var) {
5419 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET && cfg->rgctx_var->inst_basereg == X86_EBP);
5421 x86_mov_membase_reg (code, X86_EBP, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 4);
5424 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5425 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5427 /* load arguments allocated to register from the stack */
5428 sig = mono_method_signature (method);
5431 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5432 inst = cfg->args [pos];
5433 if (inst->opcode == OP_REGVAR) {
5434 g_assert (need_stack_frame);
5435 x86_mov_reg_membase (code, inst->dreg, X86_EBP, inst->inst_offset, 4);
5436 if (cfg->verbose_level > 2)
5437 g_print ("Argument %d assigned to register %s\n", pos, mono_arch_regname (inst->dreg));
5442 cfg->code_len = code - cfg->native_code;
5444 g_assert (cfg->code_len < cfg->code_size);
5450 mono_arch_emit_epilog (MonoCompile *cfg)
5452 MonoMethod *method = cfg->method;
5453 MonoMethodSignature *sig = mono_method_signature (method);
5455 guint32 stack_to_pop;
5457 int max_epilog_size = 16;
5459 gboolean need_stack_frame = needs_stack_frame (cfg);
5461 if (cfg->method->save_lmf)
5462 max_epilog_size += 128;
5464 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5465 cfg->code_size *= 2;
5466 cfg->native_code = mono_realloc_native_code(cfg);
5467 cfg->stat_code_reallocs++;
5470 code = cfg->native_code + cfg->code_len;
5472 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5473 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5475 /* the code restoring the registers must be kept in sync with OP_JMP */
5478 if (method->save_lmf) {
5479 gint32 prev_lmf_reg;
5480 gint32 lmf_offset = -sizeof (MonoLMF);
5482 /* check if we need to restore protection of the stack after a stack overflow */
5483 if (mono_get_jit_tls_offset () != -1) {
5485 code = mono_x86_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5486 /* we load the value in a separate instruction: this mechanism may be
5487 * used later as a safer way to do thread interruption
5489 x86_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 4);
5490 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5492 x86_branch8 (code, X86_CC_Z, 0, FALSE);
5493 /* note that the call trampoline will preserve eax/edx */
5494 x86_call_reg (code, X86_ECX);
5495 x86_patch (patch, code);
5497 /* FIXME: maybe save the jit tls in the prolog */
5499 if ((lmf_tls_offset != -1) && !is_win32 && !optimize_for_xen) {
5501 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5502 * through the mono_lmf_addr TLS variable.
5504 /* reg = previous_lmf */
5505 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5507 /* lmf = previous_lmf */
5508 code = mono_x86_emit_tls_set (code, X86_ECX, lmf_tls_offset);
5510 /* Find a spare register */
5511 switch (mini_type_get_underlying_type (cfg->generic_sharing_context, sig->ret)->type) {
5514 prev_lmf_reg = X86_EDI;
5515 cfg->used_int_regs |= (1 << X86_EDI);
5518 prev_lmf_reg = X86_EDX;
5522 /* reg = previous_lmf */
5523 x86_mov_reg_membase (code, prev_lmf_reg, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 4);
5526 x86_mov_reg_membase (code, X86_ECX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 4);
5528 /* *(lmf) = previous_lmf */
5529 x86_mov_membase_reg (code, X86_ECX, 0, prev_lmf_reg, 4);
5532 /* restore caller saved regs */
5533 if (cfg->used_int_regs & (1 << X86_EBX)) {
5534 x86_mov_reg_membase (code, X86_EBX, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebx), 4);
5537 if (cfg->used_int_regs & (1 << X86_EDI)) {
5538 x86_mov_reg_membase (code, X86_EDI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, edi), 4);
5540 if (cfg->used_int_regs & (1 << X86_ESI)) {
5541 x86_mov_reg_membase (code, X86_ESI, X86_EBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, esi), 4);
5544 /* EBP is restored by LEAVE */
5546 if (cfg->used_int_regs & (1 << X86_EBX)) {
5549 if (cfg->used_int_regs & (1 << X86_EDI)) {
5552 if (cfg->used_int_regs & (1 << X86_ESI)) {
5557 g_assert (need_stack_frame);
5558 x86_lea_membase (code, X86_ESP, X86_EBP, pos);
5561 if (cfg->used_int_regs & (1 << X86_ESI)) {
5562 x86_pop_reg (code, X86_ESI);
5564 if (cfg->used_int_regs & (1 << X86_EDI)) {
5565 x86_pop_reg (code, X86_EDI);
5567 if (cfg->used_int_regs & (1 << X86_EBX)) {
5568 x86_pop_reg (code, X86_EBX);
5572 /* Load returned vtypes into registers if needed */
5573 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
5574 if (cinfo->ret.storage == ArgValuetypeInReg) {
5575 for (quad = 0; quad < 2; quad ++) {
5576 switch (cinfo->ret.pair_storage [quad]) {
5578 x86_mov_reg_membase (code, cinfo->ret.pair_regs [quad], cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), 4);
5580 case ArgOnFloatFpStack:
5581 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), FALSE);
5583 case ArgOnDoubleFpStack:
5584 x86_fld_membase (code, cfg->ret->inst_basereg, cfg->ret->inst_offset + (quad * sizeof (gpointer)), TRUE);
5589 g_assert_not_reached ();
5594 if (need_stack_frame)
5597 if (CALLCONV_IS_STDCALL (sig)) {
5598 MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
5600 stack_to_pop = mono_arch_get_argument_info (NULL, sig, sig->param_count, arg_info);
5601 } else if (cinfo->vtype_retaddr)
5607 g_assert (need_stack_frame);
5608 x86_ret_imm (code, stack_to_pop);
5613 cfg->code_len = code - cfg->native_code;
5615 g_assert (cfg->code_len < cfg->code_size);
5619 mono_arch_emit_exceptions (MonoCompile *cfg)
5621 MonoJumpInfo *patch_info;
5624 MonoClass *exc_classes [16];
5625 guint8 *exc_throw_start [16], *exc_throw_end [16];
5629 /* Compute needed space */
5630 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5631 if (patch_info->type == MONO_PATCH_INFO_EXC)
5636 * make sure we have enough space for exceptions
5637 * 16 is the size of two push_imm instructions and a call
5639 if (cfg->compile_aot)
5640 code_size = exc_count * 32;
5642 code_size = exc_count * 16;
5644 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5645 cfg->code_size *= 2;
5646 cfg->native_code = mono_realloc_native_code(cfg);
5647 cfg->stat_code_reallocs++;
5650 code = cfg->native_code + cfg->code_len;
5653 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5654 switch (patch_info->type) {
5655 case MONO_PATCH_INFO_EXC: {
5656 MonoClass *exc_class;
5660 x86_patch (patch_info->ip.i + cfg->native_code, code);
5662 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5663 g_assert (exc_class);
5664 throw_ip = patch_info->ip.i;
5666 /* Find a throw sequence for the same exception class */
5667 for (i = 0; i < nthrows; ++i)
5668 if (exc_classes [i] == exc_class)
5671 x86_push_imm (code, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5672 x86_jump_code (code, exc_throw_start [i]);
5673 patch_info->type = MONO_PATCH_INFO_NONE;
5678 /* Compute size of code following the push <OFFSET> */
5679 #if defined(__default_codegen__)
5681 #elif defined(__native_client_codegen__)
5682 code = mono_nacl_align (code);
5683 size = kNaClAlignment;
5685 /*This is aligned to 16 bytes by the callee. This way we save a few bytes here.*/
5687 if ((code - cfg->native_code) - throw_ip < 126 - size) {
5688 /* Use the shorter form */
5690 x86_push_imm (code, 0);
5694 x86_push_imm (code, 0xf0f0f0f0);
5699 exc_classes [nthrows] = exc_class;
5700 exc_throw_start [nthrows] = code;
5703 x86_push_imm (code, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
5704 patch_info->data.name = "mono_arch_throw_corlib_exception";
5705 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5706 patch_info->ip.i = code - cfg->native_code;
5707 x86_call_code (code, 0);
5708 x86_push_imm (buf, (code - cfg->native_code) - throw_ip);
5713 exc_throw_end [nthrows] = code;
5725 cfg->code_len = code - cfg->native_code;
5727 g_assert (cfg->code_len < cfg->code_size);
5731 mono_arch_flush_icache (guint8 *code, gint size)
5737 mono_arch_flush_register_windows (void)
5742 mono_arch_is_inst_imm (gint64 imm)
5748 mono_arch_finish_init (void)
5750 if (!getenv ("MONO_NO_TLS")) {
5753 * We need to init this multiple times, since when we are first called, the key might not
5754 * be initialized yet.
5756 appdomain_tls_offset = mono_domain_get_tls_key ();
5757 lmf_tls_offset = mono_get_jit_tls_key ();
5759 /* Only 64 tls entries can be accessed using inline code */
5760 if (appdomain_tls_offset >= 64)
5761 appdomain_tls_offset = -1;
5762 if (lmf_tls_offset >= 64)
5763 lmf_tls_offset = -1;
5766 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5768 appdomain_tls_offset = mono_domain_get_tls_offset ();
5769 lmf_tls_offset = mono_get_lmf_tls_offset ();
5770 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5776 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5780 #ifdef MONO_ARCH_HAVE_IMT
5782 // Linear handler, the bsearch head compare is shorter
5783 //[2 + 4] x86_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
5784 //[1 + 1] x86_branch8(inst,cond,imm,is_signed)
5785 // x86_patch(ins,target)
5786 //[1 + 5] x86_jump_mem(inst,mem)
5789 #if defined(__default_codegen__)
5790 #define BR_SMALL_SIZE 2
5791 #define BR_LARGE_SIZE 5
5792 #elif defined(__native_client_codegen__)
5793 /* I suspect the size calculation below is actually incorrect. */
5794 /* TODO: fix the calculation that uses these sizes. */
5795 #define BR_SMALL_SIZE 16
5796 #define BR_LARGE_SIZE 12
5797 #endif /*__native_client_codegen__*/
5798 #define JUMP_IMM_SIZE 6
5799 #define ENABLE_WRONG_METHOD_CHECK 0
5803 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5805 int i, distance = 0;
5806 for (i = start; i < target; ++i)
5807 distance += imt_entries [i]->chunk_size;
5812 * LOCKING: called with the domain lock held
5815 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
5816 gpointer fail_tramp)
5820 guint8 *code, *start;
5822 for (i = 0; i < count; ++i) {
5823 MonoIMTCheckItem *item = imt_entries [i];
5824 if (item->is_equals) {
5825 if (item->check_target_idx) {
5826 if (!item->compare_done)
5827 item->chunk_size += CMP_SIZE;
5828 item->chunk_size += BR_SMALL_SIZE + JUMP_IMM_SIZE;
5831 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + JUMP_IMM_SIZE * 2;
5833 item->chunk_size += JUMP_IMM_SIZE;
5834 #if ENABLE_WRONG_METHOD_CHECK
5835 item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5840 item->chunk_size += CMP_SIZE + BR_LARGE_SIZE;
5841 imt_entries [item->check_target_idx]->compare_done = TRUE;
5843 size += item->chunk_size;
5845 #if defined(__native_client__) && defined(__native_client_codegen__)
5846 /* In Native Client, we don't re-use thunks, allocate from the */
5847 /* normal code manager paths. */
5848 size = NACL_BUNDLE_ALIGN_UP (size);
5849 code = mono_domain_code_reserve (domain, size);
5852 code = mono_method_alloc_generic_virtual_thunk (domain, size);
5854 code = mono_domain_code_reserve (domain, size);
5857 for (i = 0; i < count; ++i) {
5858 MonoIMTCheckItem *item = imt_entries [i];
5859 item->code_target = code;
5860 if (item->is_equals) {
5861 if (item->check_target_idx) {
5862 if (!item->compare_done)
5863 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5864 item->jmp_code = code;
5865 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5866 if (item->has_target_code)
5867 x86_jump_code (code, item->value.target_code);
5869 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5872 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5873 item->jmp_code = code;
5874 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5875 if (item->has_target_code)
5876 x86_jump_code (code, item->value.target_code);
5878 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5879 x86_patch (item->jmp_code, code);
5880 x86_jump_code (code, fail_tramp);
5881 item->jmp_code = NULL;
5883 /* enable the commented code to assert on wrong method */
5884 #if ENABLE_WRONG_METHOD_CHECK
5885 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5886 item->jmp_code = code;
5887 x86_branch8 (code, X86_CC_NE, 0, FALSE);
5889 if (item->has_target_code)
5890 x86_jump_code (code, item->value.target_code);
5892 x86_jump_mem (code, & (vtable->vtable [item->value.vtable_slot]));
5893 #if ENABLE_WRONG_METHOD_CHECK
5894 x86_patch (item->jmp_code, code);
5895 x86_breakpoint (code);
5896 item->jmp_code = NULL;
5901 x86_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)item->key);
5902 item->jmp_code = code;
5903 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5904 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5906 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5909 /* patch the branches to get to the target items */
5910 for (i = 0; i < count; ++i) {
5911 MonoIMTCheckItem *item = imt_entries [i];
5912 if (item->jmp_code) {
5913 if (item->check_target_idx) {
5914 x86_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5920 mono_stats.imt_thunks_size += code - start;
5921 g_assert (code - start <= size);
5925 char *buff = g_strdup_printf ("thunk_for_class_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5926 mono_disassemble_code (NULL, (guint8*)start, code - start, buff);
5930 if (mono_jit_map_is_enabled ()) {
5933 buff = g_strdup_printf ("imt_%s_%s_entries_%d", vtable->klass->name_space, vtable->klass->name, count);
5935 buff = g_strdup_printf ("imt_thunk_entries_%d", count);
5936 mono_emit_jit_tramp (start, code - start, buff);
5940 nacl_domain_code_validate (domain, &start, size, &code);
5946 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
5948 return (MonoMethod*) regs [MONO_ARCH_IMT_REG];
5953 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
5955 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5959 mono_arch_get_cie_program (void)
5963 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, X86_ESP, 4);
5964 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, X86_NREG, -4);
5970 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5972 MonoInst *ins = NULL;
5975 if (cmethod->klass == mono_defaults.math_class) {
5976 if (strcmp (cmethod->name, "Sin") == 0) {
5978 } else if (strcmp (cmethod->name, "Cos") == 0) {
5980 } else if (strcmp (cmethod->name, "Tan") == 0) {
5982 } else if (strcmp (cmethod->name, "Atan") == 0) {
5984 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5986 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5988 } else if (strcmp (cmethod->name, "Round") == 0 && fsig->param_count == 1 && fsig->params [0]->type == MONO_TYPE_R8) {
5993 MONO_INST_NEW (cfg, ins, opcode);
5994 ins->type = STACK_R8;
5995 ins->dreg = mono_alloc_freg (cfg);
5996 ins->sreg1 = args [0]->dreg;
5997 MONO_ADD_INS (cfg->cbb, ins);
6000 if (cfg->opt & MONO_OPT_CMOV) {
6003 if (strcmp (cmethod->name, "Min") == 0) {
6004 if (fsig->params [0]->type == MONO_TYPE_I4)
6006 } else if (strcmp (cmethod->name, "Max") == 0) {
6007 if (fsig->params [0]->type == MONO_TYPE_I4)
6012 MONO_INST_NEW (cfg, ins, opcode);
6013 ins->type = STACK_I4;
6014 ins->dreg = mono_alloc_ireg (cfg);
6015 ins->sreg1 = args [0]->dreg;
6016 ins->sreg2 = args [1]->dreg;
6017 MONO_ADD_INS (cfg->cbb, ins);
6022 /* OP_FREM is not IEEE compatible */
6023 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6024 MONO_INST_NEW (cfg, ins, OP_FREM);
6025 ins->inst_i0 = args [0];
6026 ins->inst_i1 = args [1];
6035 mono_arch_print_tree (MonoInst *tree, int arity)
6040 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6046 if (appdomain_tls_offset == -1)
6049 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6050 ins->inst_offset = appdomain_tls_offset;
6055 mono_arch_get_patch_offset (guint8 *code)
6057 if ((code [0] == 0x8b) && (x86_modrm_mod (code [1]) == 0x2))
6059 else if (code [0] == 0xba)
6061 else if (code [0] == 0x68)
6064 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x6))
6065 /* push <OFFSET>(<REG>) */
6067 else if ((code [0] == 0xff) && (x86_modrm_reg (code [1]) == 0x2))
6068 /* call *<OFFSET>(<REG>) */
6070 else if ((code [0] == 0xdd) || (code [0] == 0xd9))
6073 else if ((code [0] == 0x58) && (code [1] == 0x05))
6074 /* pop %eax; add <OFFSET>, %eax */
6076 else if ((code [0] >= 0x58) && (code [0] <= 0x58 + X86_NREG) && (code [1] == 0x81))
6077 /* pop <REG>; add <OFFSET>, <REG> */
6079 else if ((code [0] >= 0xb8) && (code [0] < 0xb8 + 8))
6080 /* mov <REG>, imm */
6083 g_assert_not_reached ();
6089 * mono_breakpoint_clean_code:
6091 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6092 * breakpoints in the original code, they are removed in the copy.
6094 * Returns TRUE if no sw breakpoint was present.
6097 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6100 gboolean can_write = TRUE;
6102 * If method_start is non-NULL we need to perform bound checks, since we access memory
6103 * at code - offset we could go before the start of the method and end up in a different
6104 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6107 if (!method_start || code - offset >= method_start) {
6108 memcpy (buf, code - offset, size);
6110 int diff = code - method_start;
6111 memset (buf, 0, size);
6112 memcpy (buf + offset - diff, method_start, diff + size - offset);
6115 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6116 int idx = mono_breakpoint_info_index [i];
6120 ptr = mono_breakpoint_info [idx].address;
6121 if (ptr >= code && ptr < code + size) {
6122 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6124 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6125 buf [ptr - code] = saved_byte;
6132 * mono_x86_get_this_arg_offset:
6134 * Return the offset of the stack location where this is passed during a virtual
6138 mono_x86_get_this_arg_offset (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig)
6144 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
6146 guint32 esp = regs [X86_ESP];
6147 CallInfo *cinfo = NULL;
6154 * The stack looks like:
6158 * <4 pointers pushed by mono_arch_create_trampoline_code ()>
6160 res = (((MonoObject**)esp) [5 + (offset / 4)]);
6166 #define MAX_ARCH_DELEGATE_PARAMS 10
6169 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6171 guint8 *code, *start;
6172 int code_reserve = 64;
6175 * The stack contains:
6181 start = code = mono_global_codeman_reserve (code_reserve);
6183 /* Replace the this argument with the target */
6184 x86_mov_reg_membase (code, X86_EAX, X86_ESP, 4, 4);
6185 x86_mov_reg_membase (code, X86_ECX, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, target), 4);
6186 x86_mov_membase_reg (code, X86_ESP, 4, X86_ECX, 4);
6187 x86_jump_membase (code, X86_EAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6189 g_assert ((code - start) < code_reserve);
6192 /* 8 for mov_reg and jump, plus 8 for each parameter */
6193 #ifdef __native_client_codegen__
6194 /* TODO: calculate this size correctly */
6195 code_reserve = 13 + (param_count * 8) + 2 * kNaClAlignment;
6197 code_reserve = 8 + (param_count * 8);
6198 #endif /* __native_client_codegen__ */
6200 * The stack contains:
6201 * <args in reverse order>
6206 * <args in reverse order>
6209 * without unbalancing the stack.
6210 * So move each arg up a spot in the stack (overwriting un-needed 'this' arg)
6211 * and leaving original spot of first arg as placeholder in stack so
6212 * when callee pops stack everything works.
6215 start = code = mono_global_codeman_reserve (code_reserve);
6217 /* store delegate for access to method_ptr */
6218 x86_mov_reg_membase (code, X86_ECX, X86_ESP, 4, 4);
6221 for (i = 0; i < param_count; ++i) {
6222 x86_mov_reg_membase (code, X86_EAX, X86_ESP, (i+2)*4, 4);
6223 x86_mov_membase_reg (code, X86_ESP, (i+1)*4, X86_EAX, 4);
6226 x86_jump_membase (code, X86_ECX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6228 g_assert ((code - start) < code_reserve);
6231 nacl_global_codeman_validate(&start, code_reserve, &code);
6232 mono_debug_add_delegate_trampoline (start, code - start);
6235 *code_len = code - start;
6237 if (mono_jit_map_is_enabled ()) {
6240 buff = (char*)"delegate_invoke_has_target";
6242 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
6243 mono_emit_jit_tramp (start, code - start, buff);
6252 mono_arch_get_delegate_invoke_impls (void)
6259 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6260 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
6262 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6263 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6264 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
6271 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6273 guint8 *code, *start;
6275 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6278 /* FIXME: Support more cases */
6279 if (MONO_TYPE_ISSTRUCT (sig->ret))
6283 * The stack contains:
6289 static guint8* cached = NULL;
6294 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
6296 start = get_delegate_invoke_impl (TRUE, 0, NULL);
6298 mono_memory_barrier ();
6302 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6305 for (i = 0; i < sig->param_count; ++i)
6306 if (!mono_is_regsize_var (sig->params [i]))
6309 code = cache [sig->param_count];
6313 if (mono_aot_only) {
6314 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6315 start = mono_aot_get_trampoline (name);
6318 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6321 mono_memory_barrier ();
6323 cache [sig->param_count] = start;
6330 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6333 case X86_EAX: return ctx->eax;
6334 case X86_EBX: return ctx->ebx;
6335 case X86_ECX: return ctx->ecx;
6336 case X86_EDX: return ctx->edx;
6337 case X86_ESP: return ctx->esp;
6338 case X86_EBP: return ctx->ebp;
6339 case X86_ESI: return ctx->esi;
6340 case X86_EDI: return ctx->edi;
6342 g_assert_not_reached ();
6348 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
6376 g_assert_not_reached ();
6380 #ifdef MONO_ARCH_SIMD_INTRINSICS
6383 get_float_to_x_spill_area (MonoCompile *cfg)
6385 if (!cfg->fconv_to_r8_x_var) {
6386 cfg->fconv_to_r8_x_var = mono_compile_create_var (cfg, &mono_defaults.double_class->byval_arg, OP_LOCAL);
6387 cfg->fconv_to_r8_x_var->flags |= MONO_INST_VOLATILE; /*FIXME, use the don't regalloc flag*/
6389 return cfg->fconv_to_r8_x_var;
6393 * Convert all fconv opts that MONO_OPT_SSE2 would get wrong.
6396 mono_arch_decompose_opts (MonoCompile *cfg, MonoInst *ins)
6399 int dreg, src_opcode;
6401 if (!(cfg->opt & MONO_OPT_SSE2) || !(cfg->opt & MONO_OPT_SIMD) || COMPILE_LLVM (cfg))
6404 switch (src_opcode = ins->opcode) {
6405 case OP_FCONV_TO_I1:
6406 case OP_FCONV_TO_U1:
6407 case OP_FCONV_TO_I2:
6408 case OP_FCONV_TO_U2:
6409 case OP_FCONV_TO_I4:
6416 /* dreg is the IREG and sreg1 is the FREG */
6417 MONO_INST_NEW (cfg, fconv, OP_FCONV_TO_R8_X);
6418 fconv->klass = NULL; /*FIXME, what can I use here as the Mono.Simd lib might not be loaded yet*/
6419 fconv->sreg1 = ins->sreg1;
6420 fconv->dreg = mono_alloc_ireg (cfg);
6421 fconv->type = STACK_VTYPE;
6422 fconv->backend.spill_var = get_float_to_x_spill_area (cfg);
6424 mono_bblock_insert_before_ins (cfg->cbb, ins, fconv);
6428 ins->opcode = OP_XCONV_R8_TO_I4;
6430 ins->klass = mono_defaults.int32_class;
6431 ins->sreg1 = fconv->dreg;
6433 ins->type = STACK_I4;
6434 ins->backend.source_opcode = src_opcode;
6437 #endif /* #ifdef MONO_ARCH_SIMD_INTRINSICS */
6440 mono_arch_decompose_long_opts (MonoCompile *cfg, MonoInst *long_ins)
6445 if (long_ins->opcode == OP_LNEG) {
6447 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 1, ins->sreg1 + 1);
6448 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_ADC_IMM, ins->dreg + 2, ins->sreg1 + 2, 0);
6449 MONO_EMIT_NEW_UNALU (cfg, OP_INEG, ins->dreg + 2, ins->dreg + 2);
6454 #ifdef MONO_ARCH_SIMD_INTRINSICS
6456 if (!(cfg->opt & MONO_OPT_SIMD))
6459 /*TODO move this to simd-intrinsic.c once we support sse 4.1 dword extractors since we need the runtime caps info */
6460 switch (long_ins->opcode) {
6462 vreg = long_ins->sreg1;
6464 if (long_ins->inst_c0) {
6465 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6466 ins->klass = long_ins->klass;
6467 ins->sreg1 = long_ins->sreg1;
6469 ins->type = STACK_VTYPE;
6470 ins->dreg = vreg = alloc_ireg (cfg);
6471 MONO_ADD_INS (cfg->cbb, ins);
6474 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6475 ins->klass = mono_defaults.int32_class;
6477 ins->type = STACK_I4;
6478 ins->dreg = long_ins->dreg + 1;
6479 MONO_ADD_INS (cfg->cbb, ins);
6481 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6482 ins->klass = long_ins->klass;
6483 ins->sreg1 = long_ins->sreg1;
6484 ins->inst_c0 = long_ins->inst_c0 ? 3 : 1;
6485 ins->type = STACK_VTYPE;
6486 ins->dreg = vreg = alloc_ireg (cfg);
6487 MONO_ADD_INS (cfg->cbb, ins);
6489 MONO_INST_NEW (cfg, ins, OP_EXTRACT_I4);
6490 ins->klass = mono_defaults.int32_class;
6492 ins->type = STACK_I4;
6493 ins->dreg = long_ins->dreg + 2;
6494 MONO_ADD_INS (cfg->cbb, ins);
6496 long_ins->opcode = OP_NOP;
6498 case OP_INSERTX_I8_SLOW:
6499 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6500 ins->dreg = long_ins->dreg;
6501 ins->sreg1 = long_ins->dreg;
6502 ins->sreg2 = long_ins->sreg2 + 1;
6503 ins->inst_c0 = long_ins->inst_c0 * 2;
6504 MONO_ADD_INS (cfg->cbb, ins);
6506 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6507 ins->dreg = long_ins->dreg;
6508 ins->sreg1 = long_ins->dreg;
6509 ins->sreg2 = long_ins->sreg2 + 2;
6510 ins->inst_c0 = long_ins->inst_c0 * 2 + 1;
6511 MONO_ADD_INS (cfg->cbb, ins);
6513 long_ins->opcode = OP_NOP;
6516 MONO_INST_NEW (cfg, ins, OP_ICONV_TO_X);
6517 ins->dreg = long_ins->dreg;
6518 ins->sreg1 = long_ins->sreg1 + 1;
6519 ins->klass = long_ins->klass;
6520 ins->type = STACK_VTYPE;
6521 MONO_ADD_INS (cfg->cbb, ins);
6523 MONO_INST_NEW (cfg, ins, OP_INSERTX_I4_SLOW);
6524 ins->dreg = long_ins->dreg;
6525 ins->sreg1 = long_ins->dreg;
6526 ins->sreg2 = long_ins->sreg1 + 2;
6528 ins->klass = long_ins->klass;
6529 ins->type = STACK_VTYPE;
6530 MONO_ADD_INS (cfg->cbb, ins);
6532 MONO_INST_NEW (cfg, ins, OP_PSHUFLED);
6533 ins->dreg = long_ins->dreg;
6534 ins->sreg1 = long_ins->dreg;;
6535 ins->inst_c0 = 0x44; /*Magic number for swizzling (X,Y,X,Y)*/
6536 ins->klass = long_ins->klass;
6537 ins->type = STACK_VTYPE;
6538 MONO_ADD_INS (cfg->cbb, ins);
6540 long_ins->opcode = OP_NOP;
6543 #endif /* MONO_ARCH_SIMD_INTRINSICS */
6546 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
6548 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
6551 gpointer *sp, old_value;
6553 const unsigned char *handler;
6555 /*Decode the first instruction to figure out where did we store the spvar*/
6556 /*Our jit MUST generate the following:
6558 Which is encoded as: 0x89 mod_rm.
6559 mod_rm (esp, ebp, imm) which can be: (imm will never be zero)
6560 mod (reg + imm8): 01 reg(esp): 100 rm(ebp): 101 -> 01100101 (0x65)
6561 mod (reg + imm32): 10 reg(esp): 100 rm(ebp): 101 -> 10100101 (0xA5)
6563 handler = clause->handler_start;
6565 if (*handler != 0x89)
6570 if (*handler == 0x65)
6571 offset = *(signed char*)(handler + 1);
6572 else if (*handler == 0xA5)
6573 offset = *(int*)(handler + 1);
6578 bp = MONO_CONTEXT_GET_BP (ctx);
6579 sp = *(gpointer*)(bp + offset);
6582 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
6591 * mono_aot_emit_load_got_addr:
6593 * Emit code to load the got address.
6594 * On x86, the result is placed into EBX.
6597 mono_arch_emit_load_got_addr (guint8 *start, guint8 *code, MonoCompile *cfg, MonoJumpInfo **ji)
6599 x86_call_imm (code, 0);
6601 * The patch needs to point to the pop, since the GOT offset needs
6602 * to be added to that address.
6605 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6607 *ji = mono_patch_info_list_prepend (*ji, code - start, MONO_PATCH_INFO_GOT_OFFSET, NULL);
6608 x86_pop_reg (code, MONO_ARCH_GOT_REG);
6609 x86_alu_reg_imm (code, X86_ADD, MONO_ARCH_GOT_REG, 0xf0f0f0f0);
6615 * mono_ppc_emit_load_aotconst:
6617 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
6618 * TARGET from the mscorlib GOT in full-aot code.
6619 * On x86, the GOT address is assumed to be in EBX, and the result is placed into
6623 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
6625 /* Load the mscorlib got address */
6626 x86_mov_reg_membase (code, X86_EAX, MONO_ARCH_GOT_REG, sizeof (gpointer), 4);
6627 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
6628 /* arch_emit_got_access () patches this */
6629 x86_mov_reg_membase (code, X86_EAX, X86_EAX, 0xf0f0f0f0, 4);
6634 /* Can't put this into mini-x86.h */
6636 mono_x86_get_signal_exception_trampoline (MonoTrampInfo **info, gboolean aot);
6639 mono_arch_get_trampolines (gboolean aot)
6641 MonoTrampInfo *info;
6642 GSList *tramps = NULL;
6644 mono_x86_get_signal_exception_trampoline (&info, aot);
6646 tramps = g_slist_append (tramps, info);
6653 #define DBG_SIGNAL SIGBUS
6655 #define DBG_SIGNAL SIGSEGV
6658 /* Soft Debug support */
6659 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
6662 * mono_arch_set_breakpoint:
6664 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
6665 * The location should contain code emitted by OP_SEQ_POINT.
6668 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
6673 * In production, we will use int3 (has to fix the size in the md
6674 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
6677 g_assert (code [0] == 0x90);
6678 x86_alu_reg_mem (code, X86_CMP, X86_EAX, (guint32)bp_trigger_page);
6682 * mono_arch_clear_breakpoint:
6684 * Clear the breakpoint at IP.
6687 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
6692 for (i = 0; i < 6; ++i)
6697 * mono_arch_start_single_stepping:
6699 * Start single stepping.
6702 mono_arch_start_single_stepping (void)
6704 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
6708 * mono_arch_stop_single_stepping:
6710 * Stop single stepping.
6713 mono_arch_stop_single_stepping (void)
6715 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
6719 * mono_arch_is_single_step_event:
6721 * Return whenever the machine state in SIGCTX corresponds to a single
6725 mono_arch_is_single_step_event (void *info, void *sigctx)
6728 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6730 if ((einfo->ExceptionInformation[1] >= ss_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)ss_trigger_page + 128))
6735 siginfo_t* sinfo = (siginfo_t*) info;
6736 /* Sometimes the address is off by 4 */
6737 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128))
6745 mono_arch_is_breakpoint_event (void *info, void *sigctx)
6748 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord; /* Sometimes the address is off by 4 */
6749 if ((einfo->ExceptionInformation[1] >= bp_trigger_page && (guint8*)einfo->ExceptionInformation[1] <= (guint8*)bp_trigger_page + 128))
6754 siginfo_t* sinfo = (siginfo_t*)info;
6755 /* Sometimes the address is off by 4 */
6756 if (sinfo->si_signo == DBG_SIGNAL && (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128))
6763 #define BREAKPOINT_SIZE 6
6766 * mono_arch_skip_breakpoint:
6768 * See mini-amd64.c for docs.
6771 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
6773 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
6777 * mono_arch_skip_single_step:
6779 * See mini-amd64.c for docs.
6782 mono_arch_skip_single_step (MonoContext *ctx)
6784 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 6);
6788 * mono_arch_get_seq_point_info:
6790 * See mini-amd64.c for docs.
6793 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
6801 #if defined(MONOTOUCH) || defined(MONO_EXTENSIONS)
6803 #include "../../../mono-extensions/mono/mini/mini-x86-gsharedvt.c"
6805 #endif /* !MONOTOUCH */